Chip based HEVC (high efficiency video coding) multi-module optimization method and system

A video coding, multi-module technology, applied in TV, electrical components, image communication, etc., can solve the problems of many model parameters, difficult model modeling, actual performance impact, etc., to achieve the effect of reducing computational bottlenecks

Inactive Publication Date: 2013-09-18
CHINA JILIANG UNIV
View PDF4 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] The disadvantage of this method is that it is very difficult to model the rate-distortion-complexity model, and there are many model parameters, which have a strong dependence on the characteristics of the video sequence. Actual performance of class methods is affected

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip based HEVC (high efficiency video coding) multi-module optimization method and system
  • Chip based HEVC (high efficiency video coding) multi-module optimization method and system
  • Chip based HEVC (high efficiency video coding) multi-module optimization method and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] The present invention will be further described below in conjunction with accompanying drawing.

[0036] For the HEVC video encoding multi-module joint optimization method and system implemented by the chip, the following modules and steps are adopted:

[0037] (1) Customizable module algorithm framework

[0038] Such as figure 1 As shown, a multi-module algorithm optimization method based on excellent algorithm integration is proposed; the hardware implementation friendliness of candidate algorithms is quantitatively measured, and the pipeline implementation algorithm is selected for the customizable module; the HEVC encoding pipeline algorithm is determined based on hardware implementation fitness evaluation and multi-module collaborative optimization Basic framework; based on the above methods, determine the initial algorithms of the integer motion estimation (IME), sub-pixel motion estimation (FME), mode selection (MD) and rate control (RC) modules, and determine t...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses chip based HEVC (high efficiency video coding) multi-module optimization method and system. The chip based HEVC (high efficiency video coding) multi-module optimization method includes integer pixel motion estimation, fractional pixel motion estimation, mode selection, coding rate control and video noise reduction. Video pre-analysis in the code rate control, motion prediction in the video noise reduction and the integer pixel motion estimation are in collaborative optimization; video pre-analysis in the code rate control, the fractional pixel motion estimation and the mode selection are combined to be optimized. By the method and system, on the basis of hardware, goodness evaluation and multi-modules collaborative optimization are realized and an HEVC pipeline algorithm basic framework is determined; motion vectors are utilized to the utmost extent and scheduling complexity of separate motion search of multiple modules is reduced; since the video pre-analysis in the code rate control, the factional pixel motion estimation (FME) and the mode selection are combined organically and a layering convergence mode-selection algorithm framework is provided, the computing bottleneck problems caused by a great quantity of HEVC modes are reduced greatly.

Description

technical field [0001] The present invention relates to a video coding optimization method and system, in particular to a chip-based HEVC video coding multi-module joint optimization method and system. Background technique [0002] In recent years, driven by high-definition, multi-view and other application requirements, the industry urgently needs a video coding standard with higher compression performance. The JCT-VC working group launched a new generation of video standard HEVC in 2013. It is foreseeable that in the next 5-10 years, research on HEVC standards and applications will become a hot spot. Designing professional-grade HD encoders compliant with the HEVC standard is extremely important to facilitate adoption of the HEVC standard. The HEVC standard achieves a sharp increase in complexity and doubles the compression performance. Designing a high-performance high-definition HEVC encoder is a very challenging task. In applications such as video surveillance and con...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/26
Inventor 殷海兵李世忠夏哲雷
Owner CHINA JILIANG UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap