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Floating point number multiplication rounding method and device

A floating-point multiplication and floating-point number technology, which is applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., can solve the problems of long mantissa processing time of floating-point multipliers, and achieve the effect of improving performance and simplifying logic

Active Publication Date: 2015-05-20
BEIJING SMART LOGIC TECH CO LTD
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Problems solved by technology

In the previous design, the floating-point multiplication is the critical path of the whole system, the main reason is that the floating-point multiplier takes a long time to process the mantissa

Method used

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  • Floating point number multiplication rounding method and device
  • Floating point number multiplication rounding method and device
  • Floating point number multiplication rounding method and device

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Embodiment Construction

[0032] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below by taking IEEE 754 single-precision floating-point multiplier rounding as a specific implementation case.

[0033] The present invention proposes an effective rounding method for floating-point multiplication, which includes:

[0034] When performing partial product compression, special data is introduced as a partial product to participate in partial product compression; the special data varies according to the rounding method of the floating-point multiplication result, and the specific values ​​are as follows:

[0035] (1) When rounding is rounding towards zero, the special number is 0;

[0036] (2) When the rounding is the nearest even rounding, the special number is 2 N-2 ;

[0037] (3) When rounding is rounding towards positive infinity, if the sign bit of the result is positive, the value is 2 N-1 -1,...

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Abstract

The invention discloses a floating point number multiplication rounding method and device. According to the method, when partial product compression is performed, predetermined data are introduced to serve as partial products to take part in the partial product compression. The predetermined data are different according to the different rounding methods of floating point multiplication results. The value is as follows specifically: when the rounding rounds to zero, a special number is 0; when the rounding rounds to the nearest even, a special number is 2N-2; when the rounding rounds to the positive infinity, if the sign bit of the result is positive, the value is 2N-1-1, otherwise the value is 0; when the rounding rounds to the negative infinity, if the sign bit of the result is negative, the value is 2N-1-1, otherwise, the value is 0. N means the length of the floating point number mantissa. A special datum is introduced in advance in the partial product compression stage, the simplification of the required work for the rounding of the subsequent mantissa is achieved, and the floating point multiplication processing performance is improved.

Description

technical field [0001] The invention belongs to the technical field of floating-point multiplication in integrated circuit design, to be precise, belongs to the technical field of mantissa rounding of floating-point multiplication of the IEEE 754 standard. Background technique [0002] With the continuous development of digital signal processing technology, people's requirements for data accuracy and real-time processing are increasing day by day. Floating-point data operations have been widely adopted in the field of digital signal processing (DSP). [0003] Floating-point multipliers are an important part of DSP processors and high-performance computing systems. Studies have shown that about 31% of floating-point operations are multiplication operations. In the previous design, the floating-point multiplication is the critical path of the whole system, the main reason is that the floating-point multiplier takes a long time to process the mantissa. [0004] The floating-p...

Claims

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Application Information

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IPC IPC(8): G06F7/57
Inventor 肖偌舟王惠娟林玻刘檬张志伟
Owner BEIJING SMART LOGIC TECH CO LTD
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