Memory aggregation device

Abstract

The invention relates to a memory aggregation device (990) for storing a set of input data streams (902) and retrieving data to a set of output data streams (904), both the set of input data streams (902) and the set of output data streams (904) being operable to perform one of sending and stop sending new data in each clock cycle, the memory aggregation device (990) comprising: a set of FIFO memories (901a, 901b,..., 901c) each comprising an input and an output; an input interconnector (903) configured to interconnect each one of the set of input data streams (902) to each input of the set of FIFO memories (901a, 901b,..., 901c) according to an input interconnection matrix; an output interconnector (905) configured to interconnect each output of the set of FIFO memories (901a, 901b,..., 901c) to each one of the set of output data streams (904) according to an output interconnection matrix; an input selector (907) configured to select the input interconnection matrix according to an input data scheduling scheme; an output selector (909) configured to select the output interconnection matrix according to an output data scheduling scheme; and a memory controller (911) coupled to both, the input selector (907) and the output selector (909), wherein the memory controller (911) is configured to control the input data scheduling scheme such that data from the set of input data streams (902) is spread among the set of FIFO memories (901a, 901b,..., 901c) in a round-robin manner and to control the output data scheduling scheme such that data from the set of FIFO memories (901a, 901b,..., 901c) is retrieved to the set of output data streams (904) in a round-robin manner.

Description

Background technique [0001] The invention relates to a memory aggregation device and a method for storing multiple input data streams into a FIFO memory bank and fetching multiple output data streams in said FIFO memory bank. [0002] High-speed hardware often needs to aggregate many data streams into a single data stream. This is commonly used today, using multiple FIFOs in the input of the system, and in a mechanism to dispatch traffic as a single stream. Since different FIFOs use unused memories, and these memories are not shared, there are defects that may lead to a large waste of chip storage area. Contents of the invention [0003] The purpose of the present invention is to provide a single aggregator FIFO concept. [0004] This object is achieved by the features of the independent claims. Embodiments are further understood from the claims, the description and the drawings. [0005] The main idea of ​​the present invention is to provide a single aggregator FIFO usi...

AI Technical Summary

Problems solved by technology

Since different FIFOs use unused memory, and these memories are not shared, there is a defect that may lead to a large waste of chip memory area

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