Instruction classification and multi-issue method based on sprac V8 instruction set

A multi-launch and instruction set technology, applied in the direction of program control design, instrumentation, electrical digital data processing, etc., to achieve the effect of ensuring correctness, small area cost, and improving execution efficiency

Active Publication Date: 2018-02-23
BEIJING MXTRONICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But there is currently no multi-issue method for the SPARC V8 processor

Method used

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  • Instruction classification and multi-issue method based on sprac V8 instruction set
  • Instruction classification and multi-issue method based on sprac V8 instruction set
  • Instruction classification and multi-issue method based on sprac V8 instruction set

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Experimental program
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Embodiment

[0079] When n=4, what the inventive method realized was four emission five-stage pipeline processors, and its structural block diagram is as follows figure 2 shown.

[0080] The five pipeline stages are connected by a common data bus, 3 instruction fetch channels are added at the instruction fetch stage, 3 decoding units are added at the decoding stage, and 4 sets of reservation stations are added between the decoding stage and the execution stage. The group reservation station corresponds to a class of instructions; a reordering buffer is added between the execution level and the memory access level; the instructions to be executed include load / store instructions, multiplication / division instructions, branch instructions and arithmetic logic instructions, according to the instructions to be executed For the arithmetic operations done at the execution level, an adder and a shifter are added to the execution level on the original basis.

[0081] The instruction fetch stage re...

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Abstract

The invention provides an instruction classified multi-emitting method based on an SPRAC V8 (Scalable Processor Architecture V8) instruction set. According to the method, SPARC V8 instructions are divided into four classes; an SPRAC V8 processor is divided into five flow stages including an instruction fetching stage, a decoding stage, an execution stage, a memory accessing stage and a writing-back stage; the five flow stages are connected through a common data bus; (n-1) instruction fetching paths are added at the instruction fetching stage; (n-1) decoding units are added at the decoding stage; n groups of reservation stations are added between the decoding stage and the execution stage; reordering buffer regions are added between the execution stage and the memory accessing stage; corresponding execution units are added in the execution stage; a multi-emitting five-stage flow line structure is built for the SPRAC V8 processor; the conflict among parallel instructions is detected through the reservation stations; different instructions are processed through different execution units; finally, the instruction execution results are sequentially submitted by the reordering buffer regions; the parallel execution of the instructions is realized; and the processing performance of the SPRAC V8 processor is improved.

Description

technical field [0001] The invention relates to an instruction classification multi-launch method based on the SPRAC V8 instruction set, and belongs to the embedded application field. Background technique [0002] RISC structure is a great progress in single-issue processor architecture design. The goal of the pipeline design in the single-issue structure is to achieve an average execution of one instruction per cycle, that is, IPC=1, but due to conflicts caused by control-related, data-related and resource-related issues, the IPC cannot reach 1. Through techniques such as instruction reorganization, branch prediction and forward data path, IPC can be improved so that it is close to 1, but it is impossible to be greater than or equal to 1. In order to break through this upper limit, the overall development trend of the current embedded processor is to improve the overall performance of the processor through innovative instruction sets and pipeline architecture on the premis...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
CPCG06F9/3004
Inventor 赵元富杨雪于立新彭和平周海洋庄伟
Owner BEIJING MXTRONICS CORP
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