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Complex multiply instruction

A complex multiplication and instruction technology, applied in instruction analysis, electrical digital data processing, program control design, etc.

Active Publication Date: 2018-11-23
ARM LTD
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Problems solved by technology

Some DSP algorithms may require multiple multiplications of the form r=(a+ib)*(c+id), so the way the processor handles complex multiplications can be a factor in performance

Method used

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  • Complex multiply instruction
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Embodiment Construction

[0045] Some special examples will be described below. It will be understood that the technology is not limited to these precise examples.

[0046]The data processing apparatus has an instruction decoder supporting decoding of a complex multiply instruction to control the processing circuitry to perform a partial complex multiply operation on the first operand vector and the second operand vector to convert at least one destination of the destination vector to The element is set to a value that depends on the result of adding or subtracting the first product and the second product. The first operand vector and the second operand vector and the destination vector each contain a plurality of data elements including at least one real element representing a real part of a complex number and at least one imaginary part representing an imaginary part of a complex number element.

[0047] Two forms of complex multiply instructions are provided. Both forms set at least one target el...

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Abstract

First and second forms of a complex multiply instruction are provided for operating on first and second operand vectors comprising multiple data elements including at least one real data element for representing the real part of a complex number and at least one imaginary element for representing an imaginary part of the complex number. One of the first and second forms of the instruction targetsat least one real element of the destination vector and the other targets at least one imaginary element. By executing one of each instruction, complex multiplications of the form (a+ib)*(c+id) can becalculated using relatively few instructions and with only two vector register read ports, enabling DSP algorithms such as FFTs to be calculated more efficiently using relatively low power hardware implementations.

Description

technical field [0001] The technology of the present invention relates to the technical field of data processing. Background technique [0002] Some data processing applications involve processing complex numbers with real and imaginary parts, i.e., numbers of the form a+ib, where i represents the square root of -1 (sometimes the square root of -1 can also be denoted as "j", but in this paper we will use "i"). Complex number arithmetic may be especially useful in digital signal processing (DSP) applications, such as for computing Fast Fourier Transforms (FFT). Some DSP algorithms may require multiple multiplications of the form r=(a+ib)*(c+id), so the way a processor handles complex multiplications can be a factor affecting performance. Contents of the invention [0003] At least some examples provide a data processing apparatus comprising: [0004] processing circuitry for performing data processing; and [0005] an instruction decoder for decoding an instruction that...

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/3001G06F9/30036G06F9/30145G06F9/30141
Inventor 托马斯·克里斯多夫·格鲁卡特
Owner ARM LTD
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