Chip packaging structure and manufacturing method thereof
A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of many process steps, unfavorable shape of blind holes, high cost, etc., and achieve the best heat dissipation effect
Active Publication Date: 2019-12-31
何崇文
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However, the cost required by the above method is high and the process steps are also many
In addition, the process and structure of blind holes formed by laser drilling are limited by the process and structure of via holes formed by electroplating and filling, and the density of blind holes is not easy to increase, and the shape of blind holes is not conducive to making linear or block shapes. Bumps, so the above-mentioned process is not easy to achieve the heat dissipation function required by high-power chips
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[0080] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference symbols are used in the drawings and descriptions to refer to the same or like parts.
[0081] Figure 1A to Figure 1F It is a schematic cross-sectional view of a manufacturing method of a chip packaging structure according to an embodiment of the present invention. Please refer to Figure 1A According to the manufacturing method of the chip packaging structure of this embodiment, firstly, a stainless steel plate 10 is provided, wherein the stainless steel plate 10 has at least one first groove 12 ( Figure 1A Two are schematically shown in ) and at least one second groove 14 located on the lower surface 13 ( Figure 1A Two are schematically shown in ). The material of the stainless steel plate 10 is, for example, SUS301, SUS 304, SUS 430 or other suitable models, and the pres...
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The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure includes a first dielectric layer, at least one chip, a first patterned circuit layer, at least one first copper pillar and a plurality of second copper pillars. The first dielectric layer has a first surface and a second surface opposite to each other. The chip is disposed on the first surface of the first dielectric layer. The first patterned circuit layer is disposed on the second surface of the first dielectric layer. The first copper pillar is embedded in the first dielectriclayer and is in direct contact with the active surface of the chip. The second copper pillar is embedded in the first dielectric layer and electrically connected with the plurality of chip pads of the chip and the first patterned circuit layer. The first section width of the first copper pillar is larger than the second section width of each second copper pillar.
Description
technical field [0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] Generally speaking, if it is desired to form a via hole or a conductive hole, after forming a dielectric layer, a blind hole can be formed by eg laser drilling to expose the circuit layer under the dielectric layer. Then, a copper layer is electroplated in the blind hole and on the dielectric layer by means of electroplating to form another circuit layer and a via hole. However, during the electroplating process, since there is no dielectric layer in the blind holes formed by the laser drilling method, it is necessary to fill the holes with copper material by electroplating. In order to avoid the quality problem of depressions on the copper surface above the blind holes, the existing process steps need to increase the thickness of the copper plating ...
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IPC IPC(8): H01L23/48H01L23/367H01L21/50
CPCH01L21/50H01L23/367H01L23/481H01L2224/18H01L2924/181H01L2924/00012
Inventor何崇文
Owner何崇文