Server mainboard of uniprocessor system

Abstract

The invention provides a server mainboard of a uniprocessor system. The server mainboard comprises a plurality of PCIe (Peripheral Component Interconnect Express) ports, a complex programmable logic device, a central processing unit, a substrate management controller and an isolating circuit. The complex programmable logic device is electrically connected to the PCIe port through a plurality of PCIe channels. The central processing unit is used for sending at least one PCIe reset signal to the complex programmable logic device through the plurality of PCIe reset pins, so that the complex programmable logic device resets the PCIe channel according to the PCIe reset signal. The substrate management controller is used for controlling updating of the complex programmable logic device. The isolation circuit is arranged between the complex programmable logic device and the substrate management controller and is used for preventing the complex programmable logic device from mistakenly triggering reset operation of the substrate management controller when the complex programmable logic device performs updating operation.

Description

technical field [0001] The invention relates to a server main board, in particular to a server main board of a single processor system. Background technique [0002] see figure 1 , figure 1 is a schematic diagram of the system architecture of a prior art dual-processor system. Such as figure 1 As shown, a dual processor system PA100 includes two processors (CPU) PA1a and PA1b, a complex programmable logic device (CPLD) PA2, a plurality of buffers (Buffer) PA3 (only one is marked in the figure) and a plurality of PCIe ports PA4 (only one is marked in the figure). [0003] Based on the above, the early dual-processor system PA100 was mostly based on Intel's dual-processor system, so the mainboard of the server will reserve a channel between the two processors PA1a and PA1b during design, so that the connection to the The channels of the complex programmable logic device PA2 are limited, and the complex programmable logic device PA2 also needs to be connected to multiple P...

AI Technical Summary

Problems solved by technology

[0003] Based on the above, the early dual-processor system PA100 was mostly based on Intel's dual-processor system, so the mainboard of the server will reserve a channel between the two processors PA1a and PA1b during design, so that the connection to the The channels of the complex programmable logic device PA2 are limited, and the complex programmable logic device PA2 also needs to be connected to multiple PCIe ports PA4 through the buffer PA3

[0004] In recent years, due to the high performance of the processor launched by AMD in response to the server market, it can replace Intel's dual processor with one processor, so it is widely favored by various manufacturers. However, because the early server system is mainly for Intel's dual processor Therefore, if AMD's processor is used in the existing dual-processor system, it will not only not be able to effectively play its due performance, but also because of the dual-processor motherboard, two processors need to be installed, resulting in poor performance. Therefore, in order to effectively use AMD processors, it is necessary to launch a new single-processor operating system to match AMD processors

[0005] In addition, in the existing dual-processor system PA100, the complex programmable logic device PA2 is also used to control the reset operation of the board management controller (not shown in the figure). However, when the complex programmable logic device PA2 executes the firmware When updating, it is easy to accidentally trigger the reset operation of the board management controller, which will cause the dual-processor system PA100 to fail to operate normally

Images