Discrete time increment type analog-to-digital converter and control method thereof

Abstract

The invention discloses a discrete time increment type analog-to-digital converter and a control method thereof, the analog-to-digital converter comprises a modulator and a digital filter, and the modulator comprises an integrator module, a single-bit quantizer, an FIR feedback digital-to-analog converter, a first compensation path and a second compensation path. The control method comprises the following steps: carrying out noise shaping processing on an input signal and an output signal of a single-bit quantizer to obtain a preliminary output signal; and the digital filter is used for filtering the preliminary output signal to obtain an output signal of the analog-to-digital converter. According to the analog-to-digital converter, hardware consumption and digital power consumption can be reduced, the conversion precision of the analog-to-digital converter is improved, and the signal distortion degree of the analog-to-digital converter is reduced. The circuit can be widely applied to the technical field of mixed signal circuits.

Description

Technical Field

[0001] The present application relates to the technical field of mixed signal circuits, and in particular to a discrete time incremental analog-to-digital converter and a control method thereof. Background Art

[0002] Single-bit quantization has intrinsic linearity, and the required single-bit digital-to-analog converter is not affected by mismatch, so it is more suitable for high-precision applications. The difficulty faced by single-bit quantization is that it will introduce a large level step at the input of the loop filter, which greatly increases the settling speed requirements of the amplifier in the first-stage integrator, thereby increasing the power consumption of the circuit.

[0003] In order to solve the above problems caused by single-bit quantization, one of the related technologies is to use an amplifier based on an inverter. This type of amplifier greatly reduces the quiescent current of the amplifier under the same driving capability through a dynamic working mode, thereby reducing the power consumption of the circuit. However, due to the lack of a stable static bias point, the performance of the amplifier based on the inverter will fluctuate greatly with the process, temperature and power supply voltage; in addition, the gain of this type of amplifier is low, and it is difficult to meet the design requirements of a high-precision Delta-Sigma modulator above 18 bits. Another related technology is to use an FIR digital-to-analog converter. This technology converts a single-bit, large-amplitude feedback signal into a multi-bit, small-amplitude feedback signal by constructing a FIR filter at the feedback branch, thereby greatly reducing the level step at the input of the loop filter; compared with traditional multi-bit quantization, the device mismatch in the FIR digital-to-analog converter will only cause a change in the transfer function of the digital-to-analog converter, and will not cause nonlinearity, so no calibration circuit is required. However, the use of FIR DAC will change the signal transfer function and noise transfer function of the original Delta-Sigma modulator, causing high-frequency spikes on the signal transfer function, thereby amplifying the high-frequency noise in the input signal; the change in the noise transfer function will cause the noise shaping effect of the modulator to deviate from the original design, weakening the suppression of quantization noise. In addition, since the incremental modulator is obtained by applying a reset to the Delta-Sigma modulator, the introduction of FIR DAC in the design of the incremental modulator poses new challenges to the reset logic of the modulator and the design of the digital filter.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to provide a discrete time incremental analog-to-digital converter and a control method thereof, which can reduce hardware consumption and digital power consumption, and improve the conversion accuracy of the analog-to-digital converter and reduce the signal distortion of the analog-to-digital converter.

[0006] To achieve the above-mentioned object, an embodiment of the present application provides a discrete time incremental analog-to-digital converter, wherein the analog-to-digital converter includes a modulator and a digital filter, wherein the modulator includes an integrator module, a single-bit quantizer, a FIR feedback digital-to-analog converter, a first compensation path and a second compensation path, and the output end of the modulator is connected to the input end of the digital filter, wherein:

[0007] The modulator is used to perform noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal;

[0008] The digital filter is used to filter the preliminary output signal to obtain the output signal of the analog-to-digital converter.

[0009] In some embodiments, the integrator module includes a first-stage integrator, a second-stage integrator, a third-stage integrator and a fourth-stage integrator, the output of the FIR feedback digital-to-analog converter is connected to the input of the first-stage integrator, the first output of the first-stage integrator and the input of the first compensation path are connected to the input of the second-stage integrator, the first output of the second-stage integrator is connected to the input of the third-stage integrator, the first output of the third-stage integrator is connected to the input of the fourth-stage integrator, the output of the fourth-stage integrator, the output of the second compensation path, the second output of the first-stage integrator, the second output of the second-stage integrator, and the second output of the third-stage integrator are connected to the input of the single-bit quantizer, and the output of the single-bit quantizer is respectively connected to the input of the FIR feedback digital-to-analog converter, the input of the first compensation path, and the input of the second compensation path, wherein:

[0010] The single-bit quantizer is used to perform quantization processing on the input signal of the single-bit quantizer to obtain the output signal of the single-bit quantizer;

[0011] The FI R feedback digital-to-analog converter is used to convert the output signal of the single-bit quantizer and subtract it from the input signal to obtain the input signal of the first-stage integrator;

[0012] The first compensation path is used to convert the output signal of the single-bit quantizer and subtract it from the output signal of the first-stage integrator to obtain the input signal of the second-stage integrator;

[0013] The second compensation path is used to convert the output signal of the single-bit quantizer and subtract it from the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator to obtain the input signal of the single-bit quantizer.

[0014] In some embodiments, it also includes:

[0015] The first-stage integrator is used to perform integration and noise shaping processing on the input signal of the first-stage integrator to obtain the output signal of the first-stage integrator;

[0016] The second-stage integrator is used to perform integration and noise shaping processing on the input signal of the second-stage integrator to obtain the output signal of the second-stage integrator;

[0017] The third-stage integrator is used to perform integration and noise shaping processing on the input signal of the third-stage integrator to obtain the output signal of the third-stage integrator;

[0018] The fourth-stage integrator is used to perform integration and noise shaping processing on the input signal of the fourth-stage integrator to obtain the output signal of the fourth-stage integrator.

[0019] In some embodiments, the FIR feedback digital-to-analog converter includes a first FIR filter and a first digital-to-analog converter, the first compensation path includes a second FIR filter and a second digital-to-analog converter, and the second compensation path includes a third FIR filter and a third digital-to-analog converter, wherein the output of the first FIR filter is connected to the input of the first digital-to-analog converter, the output of the second FIR filter is connected to the input of the second digital-to-analog converter, and the output of the third FIR filter is connected to the input of the third digital-to-analog converter.

[0020] In some embodiments, the first digital-to-analog converter, the second digital-to-analog converter and the third digital-to-analog converter are all capacitive digital-to-analog converters composed of switched capacitor circuits, and the first FIR filter, the second FIR filter and the third FIR filter are all composed of a number of D flip-flops.

[0021] In some embodiments, the Z-domain transfer function of the first FIR filter is 0.5+0.5Z -1 , the Z-domain transfer function of the second FIR filter is 0.5c1Z -1 , the Z-domain transfer function of the third FIR filter is 0.5a1c1Z -1, wherein a1 represents the output feedforward coefficient of the first-stage integrator, and c1 represents the input scaling coefficient of the first-stage integrator.

[0022] In some embodiments, it also includes:

[0023] The first FIR filter is used to filter the output signal of the single-bit quantizer to obtain a first output digital code;

[0024] The first digital-to-analog converter is used to convert the first output digital code to obtain a first output analog signal;

[0025] The second FIR filter is used to filter the output signal of the single-bit quantizer to obtain a second output digital code;

[0026] The second digital-to-analog converter is used to convert the second output digital code to obtain a second output analog signal;

[0027] The third FIR filter is used to filter the output signal of the single-bit quantizer to obtain a third output digital code;

[0028] The third digital-to-analog converter is used to convert the third output digital code to obtain a third output analog signal.

[0029] In some embodiments, the digital filter includes a digital integrator module and a gain unit, the digital integrator module includes a first-stage digital integrator, a second-stage digital integrator, a third-stage digital integrator and a fourth-stage digital integrator, the first-stage digital integrator, the second-stage digital integrator, the third-stage digital integrator, the fourth-stage digital integrator and the gain unit are connected in sequence, wherein:

[0030] The digital integrator module is used to perform integration processing on the preliminary output signal to obtain the output signal of the digital integrator module;

[0031] The gain unit is used to perform gain amplification processing on the output signal of the digital integrator module to obtain the output signal of the analog-to-digital converter.

[0032] To achieve the above object, another aspect of the embodiment of the present application provides a control method for a discrete time incremental analog-to-digital converter, the method comprising:

[0033] Performing noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal;

[0034] The preliminary output signal is filtered to obtain an output signal of the analog-to-digital converter.

[0035] In some embodiments, performing noise shaping on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal includes:

[0036] Acquire the input signal and the output signal of the single-bit quantizer;

[0037] Converting the output signal of the single-bit quantizer and subtracting it from the input signal to obtain an input signal of the first-stage integrator;

[0038] Convert the output signal of the single-bit quantizer and subtract it from the output signal of the first-stage integrator to obtain an input signal of the second-stage integrator;

[0039] The output signal of the single-bit quantizer is converted and subtracted from the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator to obtain the input signal of the single-bit quantizer;

[0040] The input signal of the single-bit quantizer is quantized to obtain the preliminary output signal.

[0041] The embodiments of the present application include at least the following beneficial effects: The present application provides a discrete-time incremental analog-to-digital converter and a control method thereof. The scheme introduces a FIR feedback digital-to-analog converter, a first compensation path, a second compensation path, and a digital filter, and adopts an incremental modulator of the FIR feedback digital-to-analog converter to reset the integrator, the FIR feedback path, and the two compensation paths to achieve compensation for the FIR feedback. The compensation path eliminates the signal transfer function spike introduced by the FIR feedback digital-to-analog converter and restores the noise transfer function, thereby achieving higher conversion accuracy. The digital filter simplifies the design of the digital filter, reduces hardware consumption and digital power consumption, and thereby reduces the signal distortion of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a structural schematic diagram of a discrete time incremental analog-to-digital converter provided in an embodiment of the present application;

[0043] Figure 2 It is a schematic diagram of the steps of a control method of a discrete time incremental analog-to-digital converter provided in an embodiment of the present application;

[0044] Figure 3 is a schematic diagram comparing modulator signals before and after compensation provided by an embodiment of the present application;

[0045] Figure 4is a schematic diagram comparing the noise transfer functions before and after compensation provided by the embodiment of the present application;

[0046] Figure 5 is a schematic diagram of the reset signal timing provided by an embodiment of the present application;

[0047] Figure 6 is a schematic diagram of the structure of a traditional digital filter provided in an embodiment of the present application;

[0048] Figure 7 is a schematic structural diagram of a simplified digital filter provided in an embodiment of the present application;

[0049] Figure 8 is a schematic diagram of an output spectrum of a fourth-order incremental analog-to-digital converter without FIR feedback enabled provided in an embodiment of the present application;

[0050] Fig. 9 Schematic diagram of the output spectrum of a fourth-order incremental analog-to-digital converter with FIR feedback enabled provided in an embodiment of the present application;

[0051] Fig.10 It is a schematic diagram of the output swing comparison of the first-stage integrator without FIR feedback enabled provided in an embodiment of the present application;

[0052] Fig.11 It is a schematic diagram of the output swing comparison of the first-stage integrator with FIR feedback enabled provided in an embodiment of the present application.

[0053] Figure numerals: 100, FIR feedback digital-to-analog converter; 101, first digital-to-analog converter; 102, first FIR filter; 103 first node; 110, first compensation path; 111, second digital-to-analog converter; 112, second FIR filter; 113 second node; 120, second compensation path; 121, third digital-to-analog converter; 122, third FIR filter; 123 third node; 140, single-bit quantizer; 131, first-stage integrator; 132, second-stage integrator; 133, third-stage integrator; 134, fourth-stage integrator; 201, first-stage digital integrator; 202, second-stage digital integrator; 203, third-stage digital integrator; 204, fourth-stage digital integrator, 205, gain unit. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0055] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0056] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0058] Before describing the embodiments of the present application in detail, some nouns and terms involved in the embodiments of the present application are first described. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0059] As a bridge between the analog domain and the digital domain, analog-to-digital converters occupy an important position in mixed-signal integrated circuits and even the entire integrated circuit field. In applications such as EEG / ECG signal acquisition, new energy vehicle battery management systems, and geological exploration, analog-to-digital converters are often required to have high conversion accuracy, while the requirements for conversion speed are relatively low. For these applications, discrete time incremental analog-to-digital converters are widely used due to their low in-band noise, easy reuse, small conversion delay, and good robustness.

[0060] The discrete time incremental analog-to-digital converter is composed of a discrete time Delta-Sigma modulator, a reset circuit, and a digital filter. The modulator includes a switched capacitor integrator based on an active op amp, a quantizer, and a feedback digital-to-analog converter. For the quantizer, it can be divided into multi-bit quantization and single-bit quantization; for each additional quantization bit, the quantization noise is reduced by 6dB, but multi-bit quantization requires a multi-bit feedback digital-to-analog converter, which will produce serious nonlinearity due to the mismatch error of circuit manufacturing and requires additional calibration circuits; in contrast, single-bit quantization has intrinsic linearity, and the required single-bit digital-to-analog converter is not affected by mismatch, so it is more suitable for high-precision applications. The difficulty faced by single-bit quantization is that it will introduce a large level step at the input of the loop filter, which greatly increases the settling speed requirements for the amplifier in the first-stage integrator, thereby increasing the power consumption of the circuit.

[0061] There are some deficiencies in the related technology. For example, the gain of the inverter-based amplifier is low, which makes it difficult to meet the design requirements of high-precision Delta-Sigma modulators above 18 bits. By constructing a FIR filter at the feedback branch, the signal transfer function and noise transfer function of the original Delta-Sigma modulator will be changed, causing high-frequency spikes in the signal transfer function, thereby amplifying the high-frequency noise in the input signal. The change in the noise transfer function will cause the noise shaping effect of the modulator to deviate from the original design, weakening the suppression of quantization noise.

[0062] In view of this, a discrete-time incremental analog-to-digital converter is provided in an embodiment of the present application. By designing and introducing a FI R feedback digital-to-analog converter, a first compensation path, a second compensation path, and a digital filter, the output voltage swing of the first-stage integrator in the incremental analog-to-digital converter can be greatly reduced, and the circuit distortion can be significantly reduced; the design of the digital filter is simplified, and the hardware consumption and digital power consumption are reduced.

[0063] Reference Figure 1 , Figure 1 A flowchart of a discrete time incremental analog-to-digital converter provided by an embodiment of the present invention, referring to Figure 1 The analog-to-digital converter includes a modulator and a digital filter. The modulator includes an integrator module, a single-bit quantizer 140, a FIR feedback digital-to-analog converter 100, a first compensation path 110 and a second compensation path 120. The output end of the modulator is connected to the input end of the digital filter, wherein:

[0064] The modulator is used to perform noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal;

[0065] It should be further explained that the integrator module includes a first-stage integrator 131, a second-stage integrator 132, a third-stage integrator 133 and a fourth-stage integrator 134, the output end of the FI R feedback digital-to-analog converter is connected to the input end of the first-stage integrator, the first output end of the first-stage integrator and the input end of the first compensation path are connected to the input end of the second-stage integrator, the first output end of the second-stage integrator is connected to the input end of the third-stage integrator, the first output end of the third-stage integrator is connected to the input end of the fourth-stage integrator, the output end of the fourth-stage integrator, the output end of the second compensation path, the second output end of the first-stage integrator, the second output end of the second-stage integrator, and the second output end of the third-stage integrator are connected to the input end of the single-bit quantizer, and the output ends of the single-bit quantizer are respectively connected to the FI The input end of the R feedback digital-to-analog converter, the input end of the first compensation path and the input end of the second compensation path are connected, wherein: the first-stage integrator is used to integrate and perform noise shaping processing on the input signal of the first-stage integrator to obtain the output signal of the first-stage integrator; the second-stage integrator is used to integrate and perform noise shaping processing on the input signal of the second-stage integrator to obtain the output signal of the second-stage integrator; the third-stage integrator is used to integrate and perform noise shaping processing on the input signal of the third-stage integrator to obtain the output signal of the third-stage integrator; the fourth-stage integrator is used to integrate and perform noise shaping processing on the input signal of the fourth-stage integrator to obtain the output signal of the fourth-stage integrator.

[0066] Further, the single-bit quantizer is used to perform quantization processing on an input signal of the single-bit quantizer to obtain an output signal of the single-bit quantizer;

[0067] Further, the FI R feedback digital-to-analog converter is used to convert the output signal of the single-bit quantizer and subtract it from the input signal to obtain the input signal of the first-stage integrator;

[0068] Specifically, the FIR feedback digital-to-analog converter includes a first FIR filter 102 and a first digital-to-analog converter 101, the first compensation path includes a second FIR filter 112 and a second digital-to-analog converter 111, and the second compensation path includes a third FIR filter 122 and a third digital-to-analog converter 121, wherein the output end of the first FIR filter is connected to the input end of the first digital-to-analog converter, the output end of the second FIR filter is connected to the input end of the second digital-to-analog converter, and the output end of the third FIR filter is connected to the input end of the third digital-to-analog converter;

[0069] It should be noted that the first digital-to-analog converter, the second digital-to-analog converter and the third digital-to-analog converter are all capacitive digital-to-analog converters composed of switched capacitor circuits, and the first FIR filter, the second FIR filter and the third FIR filter are all composed of a number of D flip-flops;

[0070] The Z-domain transfer function of the first FIR filter is 0.5+0.5Z -1 , the Z-domain transfer function of the second FIR filter is 0.5c1Z -1 , the Z-domain transfer function of the third FIR filter is 0.5a1c1Z -1 , where a1 represents the output feedforward coefficient of the first-stage integrator, and c1 represents the input scaling coefficient of the first-stage integrator;

[0071] Among them, the first FIR filter is used to filter the output signal of the single-bit quantizer to obtain a first output digital code; the first digital-to-analog converter is used to convert the first output digital code to obtain a first output analog signal; the second FIR filter is used to filter the output signal of the single-bit quantizer to obtain a second output digital code; the second digital-to-analog converter is used to convert the second output digital code to obtain a second output analog signal; the third FIR filter is used to filter the output signal of the single-bit quantizer to obtain a third output digital code; the third digital-to-analog converter is used to convert the third output digital code to obtain a third output analog signal.

[0072] In this embodiment, the FIR feedback digital-to-analog converter is composed of a first FIR filter and a first digital-to-analog converter. The FIR feedback digital-to-analog converter converts the output signal of the single-bit quantizer into an analog signal, subtracts it from the input signal at the first node 103, and forms the input of the first-stage integrator. The input of the first FIR filter is connected to the output of the single-bit quantizer, and the output of the first FIR filter is connected to the input of the first digital-to-analog converter. The first FIR filter is composed of a D flip-flop, which completes the filtering function of the output digital code. The first digital-to-analog converter converts the output digital code of the first FIR filter into an analog output, which is then summed at the first node 103 and enters the first-stage integrator.

[0073] The first compensation path is used to convert the output signal of the single-bit quantizer and subtract it from the output signal of the first-stage integrator to obtain the input signal of the second-stage integrator;

[0074] In the present embodiment, the first compensation path is composed of the second FIR filter and the second digital-to-analog converter, and the first compensation path is responsible for restoring the loop filter transfer function changed by the FIR feedback digital-to-analog converter. The input of the second FIR filter is connected to the output of the single-bit quantizer, and the output of the second FIR filter is connected to the input of the second digital-to-analog converter. The second FIR filter is composed of a D flip-flop, which completes the filtering function of the output digital code. The second digital-to-analog converter converts the output digital code of the second FIR filter into an analog output, which is then summed at the second node 113 and enters the second stage integrator.

[0075] The second compensation path is used to convert the output signal of the single-bit quantizer and subtract it from the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator to obtain the input signal of the single-bit quantizer.

[0076] In the present embodiment, the second compensation path is composed of the third FIR filter and the third digital-to-analog converter, and the second compensation path is responsible for restoring the loop filter transfer function changed by the FIR feedback digital-to-analog converter. The input of the third FIR filter is connected to the output of the single-bit quantizer, and the output of the third FIR filter is connected to the input of the third digital-to-analog converter. The third FIR filter is composed of a D flip-flop, which completes the filtering function of the output digital code. The third digital-to-analog converter converts the output digital code of the third FIR filter into an analog output, which is then summed at the third node 123 and enters the single-bit quantizer.

[0077] The digital filter is used to filter the preliminary output signal to obtain the output signal of the analog-to-digital converter.

[0078] The digital filter includes a digital integrator module and a gain unit 205. The digital integrator module includes a first-stage digital integrator 201, a second-stage digital integrator 202, a third-stage digital integrator 203 and a fourth-stage digital integrator 204. The first-stage digital integrator, the second-stage digital integrator, the third-stage digital integrator, the fourth-stage digital integrator and the gain unit are connected in sequence, wherein:

[0079] The digital integrator module is used to perform integration processing on the preliminary output signal to obtain the output signal of the digital integrator module;

[0080] The gain unit is used to perform gain amplification processing on the output signal of the digital integrator module to obtain the output signal of the analog-to-digital converter.

[0081] In this embodiment, Figure 7 A diagram of a digital filter used in the analog-to-digital converter proposed by the present invention is provided, and the filter performs a decimation filtering function on the modulator output. The digital filter 200 includes a first-stage digital integrator, a second-stage digital integrator, a third-stage digital integrator, a fourth-stage digital integrator, and a gain unit. The input of the first-stage digital integrator is connected to the output of the single-bit quantizer, and the output of the first-stage digital integrator is connected to the input of the second-stage digital integrator. The output of the second-stage digital integrator is connected to the input of the third-stage digital integrator. The output of the third-stage digital integrator is connected to the input of the fourth-stage digital integrator. The output of the fourth-stage digital integrator is connected to the input of the gain unit. The gain unit provides the output of the final analog-to-digital converter.

[0082] See also Figure 2 The embodiment of the present application also provides a control method of a discrete time incremental analog-to-digital converter, which can implement the above-mentioned discrete time incremental analog-to-digital converter, and the system includes:

[0083] S100, performing noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal;

[0084] It should be noted that, in some embodiments, step S100 may include: S110, obtaining an input signal and an output signal of a single-bit quantizer; S120, converting the output signal of the single-bit quantizer and subtracting it from the input signal to obtain an input signal of the first-stage integrator; S130, converting the output signal of the single-bit quantizer and subtracting it from the output signal of the first-stage integrator to obtain an input signal of the second-stage integrator; S140, converting the output signal of the single-bit quantizer and subtracting it from the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator to obtain the input signal of the single-bit quantizer; S150, quantizing the input signal of the single-bit quantizer to obtain a preliminary output signal.

[0085] S200, filtering the preliminary output signal to obtain an output signal of the analog-to-digital converter;

[0086] It should be noted that the present application proposes a digital filter suitable for an incremental modulator using a FIR feedback digital-to-analog converter. Figure 1 Taking the modulator in as an example, the specific principle is as follows:

[0087] The output x1[m] of the first-stage integrator in the mth clock cycle is:

[0088]

[0089] Where U[i] is the input signal of the i-th clock cycle, and V[i] is the quantizer output of the i-th clock cycle. Similarly, the outputs of the second to fourth stage integrators are:

[0090]

[0091]

[0092]

[0093] Note that due to oversampling, U[i] can be regarded as a constant. Then, from the output of the fourth-stage integrator, we can get the relationship between the analog input and the digital output after the conversion of OSR clock cycles:

[0094]

[0095] The coefficient According to the relationship between analog input and digital output, in order to recover the correct analog input from the single-bit output, the structure of the traditional digital filter is as follows: Figure 6 As shown, it consists of a first-order FIR filter, a fourth-order integrator, a third-order integrator and a summing circuit.

[0096] Further simplifying the relationship between analog input and digital output, we can get:

[0097]

[0098] Thus, the digital filter used by the incremental analog-to-digital converter proposed in this application is obtained, such as Figure 7 This filter is a simple four-stage cascade integrator filter. Figure 6 The structure eliminates three digital integrators and one FIR filter.

[0099] In summary, the present application proposes to introduce two compensation paths, namely, a first compensation path and a second compensation path, at the output of the first-stage integrator and the input of the single-bit quantizer. The Z-domain transfer functions of the first compensation path and the second compensation path are 0.5c1Z -1 、0.5a1c1Z -1 , to achieve compensation for FIR feedback; the transfer function is also implemented by a D flip-flop circuit, where a1 is the output feedforward coefficient of the first-stage integrator, and c1 is the input scaling coefficient of the first-stage integrator. Figure 1 A behavioral level diagram is given taking a fourth-order Delta-Sigma modulator as an example. Figure 3 and Figure 4 A comparison of the modulator signal transfer function and noise transfer function with and without the compensation path is given. It can be seen from the figure that the compensation path eliminates the signal transfer function spike introduced by the FIR feedback digital-to-analog converter and restores the noise transfer function, achieving higher conversion accuracy.

[0100] It should be further explained that the present application proposes a reset strategy applicable to the above-mentioned Delta-Sigma modulator. The traditional incremental modulator only resets the integrator. For the incremental modulator using the FIR feedback digital-to-analog converter proposed in the present application, the integrator, the FIR feedback path and the two compensation paths are reset, wherein the reset signal RSTN2 of the FIR feedback path and the two compensation paths is delayed by one modulator clock cycle compared to the reset signal RSTN1 of the integrator, thereby achieving a complete reset of the modulator after each conversion, avoiding the current conversion information from being retained until the next conversion. The timing diagram of the reset signal is shown in FIG. Figure 5 shown.

[0101] Finally, the design method proposed in this application was verified by a fourth-order single-bit quantized incremental analog-to-digital converter with a sampling clock frequency of 10.24MHz and a bandwidth of 20kHz. Figure 8 and Fig. 9 The output spectrum of the incremental ADC without FIR feedback and with FIR feedback is compared under the same power consumption; the former has SNR = 105.6dB, SNDR = 99.7dB, and the latter has SNR = 109.2dB, SNDR = 106.3dB; the introduction of FIR feedback and its compensation branch improves the SNDR of the circuit by 6.6dB. The FIR feedback ADC reduces the level step value of the feedback signal, such as Fig.10 and Fig.11 As shown in the figure, the nonlinearity in the establishment process of the switched capacitor integrator is reduced, thereby significantly reducing the distortion of the analog-to-digital converter, and the designed compensation branch ensures that the modulator still has good noise shaping capability after the introduction of FIR feedback, so that the modulator has a high SNR; finally, the proposed digital filter completes the filtering of the modulator output with very small hardware consumption and obtains the correct output signal.

[0102] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0103] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A discrete time incremental analog-to-digital converter, characterized in that: The analog-to-digital converter comprises a modulator and a digital filter, wherein the modulator comprises an integrator module, a single-bit quantizer, an FIR feedback digital-to-analog converter, a first compensation path and a second compensation path, and the output end of the modulator is connected to the input end of the digital filter, wherein: The modulator is used to perform noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal; The digital filter is used to filter the preliminary output signal to obtain the output signal of the analog-to-digital converter.

2. The analog-to-digital converter according to claim 1, characterized in that The integrator module includes a first-stage integrator, a second-stage integrator, a third-stage integrator and a fourth-stage integrator, the output end of the FIR feedback digital-to-analog converter is connected to the input end of the first-stage integrator, the first output end of the first-stage integrator and the input end of the first compensation path are connected to the input end of the second-stage integrator, the first output end of the second-stage integrator is connected to the input end of the third-stage integrator, the first output end of the third-stage integrator is connected to the input end of the fourth-stage integrator, the output end of the fourth-stage integrator, the output end of the second compensation path, the second output end of the first-stage integrator, the second output end of the second-stage integrator, and the second output end of the third-stage integrator are connected to the input end of the single-bit quantizer, and the output end of the single-bit quantizer is respectively connected to the input end of the FIR feedback digital-to-analog converter, the input end of the first compensation path, and the input end of the second compensation path, wherein: The single-bit quantizer is used to perform quantization processing on the input signal of the single-bit quantizer to obtain the output signal of the single-bit quantizer; The FIR feedback digital-to-analog converter is used to convert the output signal of the single-bit quantizer and subtract it from the input signal to obtain the input signal of the first-stage integrator; The first compensation path is used to convert the output signal of the single-bit quantizer and subtract it from the output signal of the first-stage integrator to obtain the input signal of the second-stage integrator; The second compensation path is used to convert the output signal of the single-bit quantizer and subtract it from the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator to obtain the input signal of the single-bit quantizer.

3. The analog-to-digital converter according to claim 2, characterized in that: Also includes: The first-stage integrator is used to perform integration and noise shaping processing on the input signal of the first-stage integrator to obtain the output signal of the first-stage integrator; The second-stage integrator is used to perform integration and noise shaping processing on the input signal of the second-stage integrator to obtain the output signal of the second-stage integrator; The third-stage integrator is used to perform integration and noise shaping processing on the input signal of the third-stage integrator to obtain the output signal of the third-stage integrator; The fourth-stage integrator is used to perform integration and noise shaping processing on the input signal of the fourth-stage integrator to obtain the output signal of the fourth-stage integrator.

4. The analog-to-digital converter according to claim 1, characterized in that: The FIR feedback digital-to-analog converter includes a first FIR filter and a first digital-to-analog converter, the first compensation path includes a second FIR filter and a second digital-to-analog converter, and the second compensation path includes a third FIR filter and a third digital-to-analog converter, wherein the output end of the first FIR filter is connected to the input end of the first digital-to-analog converter, the output end of the second FIR filter is connected to the input end of the second digital-to-analog converter, and the output end of the third FIR filter is connected to the input end of the third digital-to-analog converter.

5. The analog-to-digital converter according to claim 4, characterized in that: The first digital-to-analog converter, the second digital-to-analog converter and the third digital-to-analog converter are all capacitive digital-to-analog converters composed of switched capacitor circuits, and the first FIR filter, the second FIR filter and the third FIR filter are all composed of a plurality of D flip-flops.

6. The analog-to-digital converter according to claim 4, characterized in that: The Z-domain transfer function of the first FIR filter is 0.5+0.5Z -1 , the Z-domain transfer function of the second FIR filter is 0.5c1Z -1 , the Z-domain transfer function of the third FIR filter is 0.5a1c1Z -1 , wherein a1 represents the output feedforward coefficient of the first-stage integrator, and c1 represents the input scaling coefficient of the first-stage integrator.

7. The analog-to-digital converter according to claim 4, characterized in that: Also includes: The first FIR filter is used to filter the output signal of the single-bit quantizer to obtain a first output digital code; The first digital-to-analog converter is used to convert the first output digital code to obtain a first output analog signal; The second FIR filter is used to filter the output signal of the single-bit quantizer to obtain a second output digital code; The second digital-to-analog converter is used to convert the second output digital code to obtain a second output analog signal; The third FIR filter is used to filter the output signal of the single-bit quantizer to obtain a third output digital code; The third digital-to-analog converter is used to convert the third output digital code to obtain a third output analog signal.

8. The analog-to-digital converter according to claim 1, characterized in that: The digital filter comprises a digital integrator module and a gain unit, the digital integrator module comprises a first-stage digital integrator, a second-stage digital integrator, a third-stage digital integrator and a fourth-stage digital integrator, the first-stage digital integrator, the second-stage digital integrator, the third-stage digital integrator, the fourth-stage digital integrator and the gain unit are connected in sequence, wherein: The digital integrator module is used to perform integration processing on the preliminary output signal to obtain the output signal of the digital integrator module; The gain unit is used to perform gain amplification processing on the output signal of the digital integrator module to obtain the output signal of the analog-to-digital converter.

9. A control method for a discrete time incremental analog-to-digital converter, characterized in that: The method comprises the following steps: Performing noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal; The preliminary output signal is filtered to obtain an output signal of the analog-to-digital converter.

10. The method according to claim 9, characterized in that The step of performing noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal includes: Acquire the input signal and the output signal of the single-bit quantizer; Converting the output signal of the single-bit quantizer and subtracting it from the input signal to obtain an input signal of the first-stage integrator; Convert the output signal of the single-bit quantizer and subtract it from the output signal of the first-stage integrator to obtain an input signal of the second-stage integrator; The output signal of the single-bit quantizer is converted and subtracted from the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator to obtain the input signal of the single-bit quantizer; The input signal of the single-bit quantizer is quantized to obtain the preliminary output signal.

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