Dynamic training system for DDR sampling based on FPGA

Abstract

The invention provides an FPGA-based DDR sampling dynamic training system, which comprises a PLL module, a training module, a DDRPAD module and a DDR module, and is characterized in that the PLL module generates a local clock and a phase offset clock used for data sampling, a phase adjustment sub-module can adjust the phase of the phase offset clock, the DDR module stores preset data from the training module and sends out return data, and the training module is connected with the DDRPAD module and the DDR module. The training module is used for sending preset data and comparing data returned by the DDR module, the phase adjustment sub-module is used for controlling the phase offset clock to obtain stable data returned by the DDR module, the DDRPAD module is used for receiving the data and converting the data, carrying out local clock synchronization processing on the converted data and then sending the data to the training module for processing, and the DDRPAD module is used for outputting the processed data. And completing initialization training of the DDR particles. According to the invention, a low-cost and high-frequency DDR data training function is realized, the sampled data is more stable, and the rate is higher.

Description

Technical Field

[0001] The present invention relates to the field of data storage, and in particular to a dynamic training system for DDR sampling based on FPGA. Background Art

[0002] With the rapid development of the information age, all walks of life have increased the demand for the use of memory chips for further processing of images or data. DDR chips are the product of the development of the times. From SDRAM to DDR1 to DDR5, each generation of improvement is a significant improvement in speed and capacity. The conventional DDR1 core frequency supports 133MHz, 166Mhz, 200Mhz, 300MHz, etc. to suit different application scenarios.

[0003] Since DDR reading and writing are asynchronous operations, when the core frequency of DDR increases, the frequency of returned data will also become higher and higher. At this time, special training is required for the data returned by DDR to ensure stable data acquisition.

[0004] DDR uses both edges of DQS to output data simultaneously, that is, data is transmitted at both the rising and falling edges of the clock, and then the data is sent to the master end for further processing through serial-to-parallel conversion. This dual-edge transmission method effectively reduces the number of pins of DDR particles, which is conducive to simplifying the layout and wiring on the board when making circuit boards, but it also increases the transmission rate between the particles and the master end, causing difficulties in data sampling at the master end. As a result, a read-write master circuit for DDR is produced, generally called DDR PHY.

[0005] DDR is generally composed of 8 DQ pins, a corresponding set of DQS pins, several address control pins and a dedicated differential clock output. A DQS as a data sampling pulse at the sending or receiving end can write 2, 4, or 8 data to DDR at a time, which is called burst transmission, and the corresponding number of DQS pulses is 1, 2, or 4.

[0006] FPGA is called Field Programmable Gate Array, which is a hardware programmable device composed of a large number of switches, registers, and wiring resources. It can quickly perform read and write training control on DDR, and can use FPGA to replace DDR PHY to achieve fast verification and application, thereby speeding up the update and launch of products.

[0007] The Chinese invention patent with patent application number 200710034742.6 applies for "a method for sampling data of off-chip DRAM with configurable sampling points". This scheme uses a delayed DDR input clock to sample data, and then uses PLL to output clocks of different phases to sample data. By judging whether the returned value is the expected value, the specific phase clock of the PLL is selected, and the DDR data can be stably read using this clock. This method occupies few resources and has a simple implementation principle. It is a method for collecting DDR return data with a low-frequency clock.

[0008] In the DDR data sampling process, the above-mentioned prior art generally uses a method of fixedly generating multiple phase clocks. First, the input sampling clock is dynamically delayed, and then the delayed clock is used to sample the DDR input data. After the local clock synchronization of the data is achieved, the returned data is compared with the preset value. By continuously adjusting the delay module, the returned data is made the same as the preset value, thereby obtaining a stable delay value. The "delay value" is written into the delay module and fixed, and the phase position of the sampling clock can be determined. In this process, multiple delay modules must be used to delay the clock, which increases the use of resources. In particular, when the sampling controller is integrated into a hard-core DDR PHY, the delay module will increase the production cost, so it is not applicable in certain application scenarios that need to reduce costs and power consumption. Therefore, the present invention provides a dynamic training system for DDR sampling based on FPGA to solve the above problems. Summary of the invention

[0009] The purpose of the present invention is to provide a dynamic training system for DDR sampling based on FPGA to realize the function of low-cost and high-frequency data collection, and the sampled data is more stable and the sampling rate can be higher, thereby realizing the design and production of a high-performance soft DDR PHY controller.

[0010] In order to achieve the purpose of the present invention, the technical solution adopted by the present invention is:

[0011] The FPGA-based dynamic training system for DDR sampling includes a PLL module, a training module, a DDR_PAD module and a DDR module, wherein:

[0012] The PLL module includes a clock generation submodule and a phase adjustment submodule, wherein the clock generation submodule is used to generate a local clock and a phase-shiftable clock, the phase-shiftable clock is used for data sampling, and the phase adjustment submodule can perform phase adjustment on the phase-shiftable clock;

[0013] The DDR module is used to store preset data and send return data;

[0014] The training module is used to realize the generation and processing of data and the control of the DDR module and the phase adjustment submodule to obtain stable data returned by the DDR module that can be sampled;

[0015] The DDR_PAD module is used to receive data and implement data conversion, and performs local clock synchronization processing on the converted data before sending it to the training module for processing.

[0016] Further, the DDR_PAD module includes a CMD submodule, an ODDR submodule, an IDDR submodule and a FIFO submodule, wherein:

[0017] The CMD submodule is used to receive preset data and realize read-write enable signal conversion, and send the converted preset data and read-write enable signal to the ODDR submodule;

[0018] The ODDR submodule is used to realize parallel-to-serial conversion of preset data and read-write enable signals, thereby realizing frequency enhancement. The preset data and read-write enable signals after frequency enhancement are sent to the DDR module;

[0019] The IDDR submodule is used to receive the return data from the DDR module and send the return data to the FIFO submodule after down-converting.

[0020] The FIFO submodule is used to receive the return data from the IDDR submodule and perform local clock synchronization processing on the return data to obtain valid data and then send the valid data to the training module for processing.

[0021] Furthermore, the training module includes a data reading and writing unit, a data receiving unit, a data judging unit, a pulse signal generating unit, an offset storage unit and a sampling position calculating unit, wherein:

[0022] The data reading and writing unit is used to send preset data and a data reading and writing enable signal to the CMD submodule;

[0023] The data receiving unit is used to receive the valid data returned by the FIFO submodule;

[0024] The data judging unit is used to judge whether the valid data received by the data receiving unit is the same as the preset data;

[0025] The pulse signal generating unit is used to generate a phase modulated pulse signal when the valid data is different from the preset data and send it to the phase adjustment submodule so that the phase adjustment submodule performs phase adjustment on the phase shiftable clock;

[0026] The offset storage unit is used to store the number of offsets of the phase-shiftable clock;

[0027] The sampling position calculation unit is used to calculate the number of offsets of the phase-shiftable clock stored in the offset storage unit and obtain a fixed sampling position.

[0028] Furthermore, the CMD submodule includes a valid data locating unit, and the valid data locating unit is used to generate a valid data signal to locate a valid data interval of the data returned by the DDR module.

[0029] Further, the offset storage unit includes a screening subunit and a boundary storage subunit, wherein:

[0030] The screening subunit is used to screen out the number of shifts of the phase-shiftable clock when the first returned data sampled by the phase-shiftable clock is the same as the preset data, and record it as the effective left boundary left_bound; and the number of shifts of the phase-shiftable clock when the first returned data is different from the preset data after the returned data is the same as the preset data, and record it as the effective right boundary right_bound;

[0031] The boundary storage subunit is used to store the values ​​of the effective left boundary left_bound and the effective right boundary right_bound.

[0032] Furthermore, the sampling position calculation unit includes a valid interval calculation subunit and a final value calculation subunit, wherein:

[0033] The valid interval calculation subunit is used to calculate the valid interval of the phase-shiftable clock, that is, the value of right_bound minus left_bound;

[0034] The final value calculation subunit is used to calculate the final offset times of the phase-shiftable clock, that is, left_bound+1 / 2(right_bound-left_bound).

[0035] Furthermore, the return data sent by the DDR module includes a DQS clock signal and a DQ data signal. A high-level signal of the DQS clock signal pulse returned by the DDR module (4) is obtained within the valid data interval located by the valid data signal as an input enable signal of the FIFO submodule (34). The input enable signal is used to determine whether the return data is within the valid data interval.

[0036] Furthermore, the DDR_PAD module also includes an inverter, and the valid data returned by the FIFO submodule is passed through the inverter to obtain a data validity determination signal, and the data validity determination signal is used to determine whether the data after local clock synchronization of the FIFO submodule (34) is valid, and the data validity determination signal and the valid data are transmitted together to the data receiving unit.

[0037] Furthermore, the training module also includes an address selection unit, and the address selection unit is used to select an address of the DDR module that can effectively store data.

[0038] Furthermore, the local clock and the phase-shifted clock are consistent in phase and frequency in an initial state.

[0039] Beneficial effects of the present invention:

[0040] 1. The present invention uses the clock generation submodule of the PLL module to generate a phase-shiftable clock to sample the return data of the DDR module. The training module accurately calculates the position of the return data of the DDR module, and adjusts the phase-shiftable clock to perform phase adjustment, so that the sampling can be accurately located at the position of the return data of the DDR module, so that the sampling frequency can be higher. Compared with the prior art, the use of the delay module is saved. The delay module is a hard-core device with a high production cost. The present invention reduces the production cost by eliminating the use of the delay module, and is also applicable in certain application scenarios where cost and power consumption need to be reduced.

[0041] 2. The present invention does not use a delay module, which saves resources, and only uses a set of offset clocks. Compared with the traditional PLL module that outputs 4 different phase clocks, it further saves resources and has simpler logic. Compared with the prior art, the prior art uses a delay module to dynamically delay the input sampling clock, which generally requires the use of multiple fixed phase clocks. During the sampling process, multiple delay modules are required to delay the clock, which occupies more resources and affects the layout design of other functional modules. The present invention only uses a set of offset clocks and omits the use of delay modules, which provides space for the layout design of other functional modules and is more flexible, which can speed up the design progress.

[0042] 3. The present invention provides a valid data locating unit to accurately locate valid data, thereby further improving the accuracy and stability of sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is an overall module block diagram of the dynamic training system of DDR sampling based on FPGA of the present invention;

[0044] Figure 2It is an overall flow chart of the dynamic training system of DDR sampling based on FPGA of the present invention;

[0045] Figure 3 It is a flow chart of a training module of a dynamic training system for DDR sampling based on FPGA of the present invention;

[0046] Figure 4 It is a read data sampling timing diagram of the DDR_PAD module of the dynamic training system for DDR sampling based on FPGA of the present invention;

[0047] Figure 5 This is a timing diagram of the left and right boundaries of the return data of the DDR module of the dynamic training system for DDR sampling based on FPGA of the present invention.

[0048] The reference numerals are as follows:

[0049] 1. PLL module; 101. clock generation submodule; 102. phase adjustment submodule;

[0050] 2. Training module; 21. Site selection unit; 22. Data reading and writing unit; 23. Data receiving unit; 24. Data judgment unit; 25. Pulse signal generating unit; 26. Offset storage unit; 261. Screening subunit; 262. Boundary storage subunit; 27. Sampling position calculation unit; 271. Valid interval calculation subunit; 272. Final value calculation subunit;

[0051] 3. DDR_PAD module; 31. CMD submodule; 311. Valid data location unit; 32. ODDR submodule; 33. IDDR submodule; 34. FIFO submodule;

[0052] 4. DDR module;

[0053] 5. Inverter. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0055] The embodiment of the present invention provides a dynamic training system for DDR sampling based on FPGA, referring to Figure 1 , including PLL module 1, training module 2, DDR_PAD module 3 and DDR module 4. Each module is composed of existing resources of FPGA. The chip model of FPGA is EG4D20EG176, and the chip has a built-in x32 DDR particle. Among them, PLL module 1 includes clock generation submodule 101 and phase adjustment submodule 102. Clock generation submodule 101 generates two clocks, one is local clock and the other is phase-shiftable clock. The reading and writing of DDR module 4 are asynchronous operations. The phase-shiftable clock is used to sample asynchronous data. The phase adjustment submodule 102 can adjust the phase of the phase-shiftable clock. The local clock and the phase-shiftable clock have the same phase and frequency in the initial state. DDR module 4 is used to store preset data and send return data. Training module 2 realizes the generation and processing of data and the control of DDR module 4 and phase adjustment submodule 102. The DDR_PAD module 3 receives data and implements data conversion, performs local clock synchronization processing on the converted data and then sends it to the training module 2. The training module 2 determines whether the returned data is valid, thereby controlling the phase adjustment submodule 102 to adjust the phase of the phase-shifted clock to obtain stable data returned by the DDR module 4 that can be sampled, thereby completing the initialization training of the DDR particles.

[0056] This embodiment uses the clock generation submodule 101 of the PLL module 1 to output a phase-shifted clock to dynamically sample the return data of the DDR module 4. The phase-shifted clock is adjusted by the training module 2 and the DDR_PAD module 3 so that the sampling enable can be accurately located at the position of the return data of the DDR module 4, thereby making the sampling frequency higher. Compared with the prior art, this solution eliminates the use of the clock input delay module and saves resources. Sampling through the phase-shifted clock is more flexible and suitable for DDR particles of various performances. And only one set of phase-shifted clocks is used, which saves more resources and has simpler logic than the traditional PLL module 1 outputting 4 phase clocks that are blocked.

[0057] Specifically, refer to Figure 2, DDR_PAD module 3 includes CMD submodule 31, ODDR submodule 32, IDDR submodule 33 and FIFO submodule 34. When read and write operations are required, training module 2 will send data read and write enable signals and preset data. CMD submodule 31 receives preset data and data read and write enable signals and converts the data read and write enable signals into data read and write commands. ODDR submodule 32 receives data read and write commands and preset data from CMD submodule 31, converts preset data and data read and write commands into data formats with valid double edges of the sending clock. DDR module 4 has its own address and can store preset data in a fixed address. ODDR submodule 32 sends preset data to a fixed position of DDR module 4 for storage. All commands sent to DDR module 4 need to be converted from parallel to serial by ODDR submodule 32, and then sent to DDR module 4 so that DDR module 4 stores data and sends return data. Data read and write commands include read commands and write commands. DDR module 4 will write data into storage when receiving a write command, and will read data and send return data when receiving a read command.

[0058] DDR module 4 will return two signals, one is DQS clock signal, the other is DQ data signal. The returned data is sometimes correct and sometimes wrong, which is difficult to detect. In addition, the returned data sent by DDR module 4 is double data, and the returned data needs to be parsed. Therefore, the DQS clock signal and DQ data signal returned by DDR module 4 are in the phase-shiftable clock domain, and each passes through IDDR submodule 33. IDDR submodule 33 can parse the returned data into single data, and convert high-speed serial data into low-speed parallel data. The frequency of the returned data after parsing is reduced, so that it can be better judged, which is conducive to the stability of clock sampling. IDDR submodule 33 then returns the parsed data to FIFO submodule 34, and FIFO submodule 34 is used to perform local clock synchronization processing on the returned data.

[0059] Furthermore, the CMD submodule 31 also includes a valid data locating unit 311. When the CMD submodule 31 receives a data read / write enable signal, converts the data read / write enable signal into a data read / write command and sends a read command, the valid data locating unit 311 generates a valid data signal to locate the valid interval of the DQ data returned by the DDR module 4. In this embodiment, the valid data signal is defined as the rdqs_gate signal. The DQS clock signal itself is also a pulse signal. The rdqs_gate signal is generated by utilizing the inherent parameter tCL of the DDR particle and is delayed by corresponding tCL clock cycles after the read command. It is used to frame the valid interval of the DQ data signal returned by the DDR module 4 to ensure that the data is not interfered with by other signals. After the read command is issued, the DDR module 4 will return the DQS clock signal and the DQ data signal at intervals of tCL cycles. The DQS clock signal and the DQ data signal from the IDDR submodule 33 output two sets of corresponding data under the rdqs_gate signal, which are defined as the fifo_en signal and the fifo_rdata signal respectively. The fifo_en signal is used as the input enable signal of the FIFO submodule 34, and the fifo_rdata signal is used as the input data signal of the FIFO submodule 34. The fifo_en signal is a high-level signal of the DQS clock signal pulse returned by the DDR module 4 obtained within the effective interval of the rdqs_gate, and is used to determine whether the returned data is within the effective interval of the rdqs_gate signal. The phase-shiftable clock samples the data returned by the IDDR submodule 33, and does not directly use the DQS clock signal. The DQ data signal is actually sampled, and the high-level signal of the DQS clock signal pulse is used as the input enable signal of the FIFO, which effectively solves the problem of the data returned by the DDR module 4 not being aligned with the clock. Data within the range of the rdqs_gate signal indicates that the sampling is reasonable, and data outside the range indicates that it is abnormal and will be sampled incorrectly. The collected data is sent to the FIFO submodule 34 for local clock synchronization, and the data from the FIFO submodule 34 enters the training module 2 for comparison to determine whether the returned data is consistent with the preset data.

[0060] The FIFO submodule 34 is a first-in, first-out module, with write enable, write data and write clock ports in the data writing direction, and empty flag signal, read enable port and read data port in the output direction. Once the FIFO submodule 34 is written with the phase-shiftable clock, input enable signal and valid data, the empty signal will be immediately pulled low, indicating that data has been stored in the FIFO submodule 34, and the empty signal is used as the read data enable signal of the FIFO submodule 34, and the data read operation is performed in the local clock domain, so that once data is written to the FIFO submodule 34, the FIFO submodule 34 can be read out at the fastest speed. The data returned by the FIFO submodule 34 will pass through an inverter and then to the training module 2. When the FIFO submodule 34 returns data, it will simultaneously generate a signal for judging the validity of the data, which is defined as the "train_gate" signal, which is the FIFO empty signal inverted by the inverter and delayed by one beat under the local clock. This signal is aligned with the return data read out by the FIFO submodule 34, and serves as an enable signal for the subsequent training module 2 to determine whether the current data after the return of the local clock synchronization is valid. The data stored in the FIFO submodule 34 and the returned data that can be read are considered valid.

[0061] Specifically, refer to Figure 2 and Figure 3 The training module 2 includes an address selection unit 21, a data read / write unit 22, a data receiving unit 23, a data judgment unit 24, a pulse signal generating unit 25, an offset storage unit 26 and a sampling position calculation unit 27. The address selection unit 21 selects a fixed address of the DDR module 4 that can effectively store data. The data read / write unit 22 sends preset data and a data read / write enable signal to the DDR_PAD module 3, and the preset data will be written into the fixed address selected by the address selection unit 21. The data read / write enable signal includes a read enable signal and a write enable signal. After receiving the data read / write enable signal, the CMD submodule 31 converts the data read / write enable signal into a data read / write command, converts the read enable signal into a read command, and converts the write enable signal into a write command. Both the write command and the read command are sent to the DDR module 4 through the ODDR submodule 32 so that the DDR module 4 stores the preset data, and the DDR module 4 sends the return data to the IDDR submodule 33 and then to the FIFO submodule 34. The data receiving unit 23 receives the valid signal and valid data returned from the FIFO submodule 34. The data judging unit 24 judges whether the valid data received by the data receiving unit 23 is the same as the preset data. When the valid data is different from the preset data, the pulse signal generating unit 25 generates a phase modulated pulse signal and sends it to the phase adjusting submodule 102 so that the phase adjusting submodule 102 adjusts the phase of the phase shiftable clock.

[0062] The offset storage unit 26 stores the number of offsets of the phase-shiftable clock. The offset storage unit 26 includes a screening subunit 261 and a boundary storage subunit 262. The screening subunit 261 screens out the number of offsets of the phase-shiftable clock when the first return data is the same as the preset data and records it as the effective left boundary left_bound, and the number of offsets of the phase-shiftable clock when the return data is the same as the preset data and the first return data is different from the preset data and is recorded as the effective right boundary. The boundary storage subunit 262 stores the values ​​of the effective left boundary left_bound and the effective right boundary right_bound. The sampling position calculation unit 27 calculates the number of offsets of the phase-shiftable clock screened by the screening subunit 261 and obtains a fixed sampling position. The sampling position calculation unit 27 includes a valid interval calculation subunit 271 and a final value calculation subunit 272. The valid interval calculation subunit 271 calculates the valid interval of the phase-shiftable clock, i.e., right_bound minus left_bound. The final value calculation subunit 272 calculates the final number of shifts of the phase-shiftable clock, i.e., left_bound+1 / 2(right_bound-left_bound). Thus, the training module 2 obtains the final number of shifts of the phase-shiftable clock, and the sampling position of the phase-shiftable clock is fixed.

[0063] The implementation principle of this embodiment is as follows: the clock generation submodule 101 of the PLL module 1 generates a local clock, the phase adjustment submodule 102 generates a phase-shiftable clock, the address selection unit 21 of the training module 2 sends a fixed address signal, the data read and write unit 22 sends a write enable signal to the CMD submodule 31 in the DDR_PAD module 3, the CMD submodule 31 receives the fixed address signal and converts the write enable signal into a write command and then sends the fixed address signal and the write command to the ODDR submodule 32, the ODDR submodule 32 converts the fixed address signal and the write command into a data format in which both edges of the sending clock are valid, the ODDR submodule 32 then sends the write command and the fixed address signal to the DDR module 4, and after receiving the write command, the DDR module 4 reserves the fixed address required to store the preset data according to the fixed address signal and prepares to write the preset data.

[0064] Then the data read and write unit 22 sends out preset data. After receiving the preset data, the data read and write unit 22 sends out a read enable signal to the CMD sub-module 31 in the DDR_PAD module 3. The CMD sub-module 31 receives the preset data and the read enable signal and converts the read enable signal into a read command and then sends the preset data and the read command to the ODDR sub-module 32. The ODDR sub-module 32 converts the preset data and the read command into a data format with both edges of the sending clock valid and then sends it to the DDR module 4. After receiving the preset data and the read command, the DDR module 4 writes the preset data to a fixed address for storage. At this time, the training module 2 waits for the DDR module 4 to execute the read command. It can be known from the DDR protocol that after tCL cycles, the DDR module 4 will return data.

[0065] Reference Figure 4 When the DDR module 4 returns data, the valid data positioning unit 311 of the CMD submodule 31 generates the rdqs_gate signal to frame the valid interval of the DQ data signal returned by the DDR module 4. The DQS clock signal and the DQ data signal pass through the IDDR submodule 33 in the phase-shiftable clock domain. The IDDR submodule 33 parses the returned data and returns the parsed data to the FIFO submodule 34. The DQS clock signal and the DQ data signal from the IDDR submodule 33 output the fifo_en signal and the fifo_rdata signal under the rdqs_gate signal. The fifo_en signal is used as the input enable signal of the FIFO submodule 34, and the fifo_rdata signal is used as the input data signal of the FIFO submodule 34. After receiving the signal, the FIFO submodule 34 performs local clock synchronization processing on the returned data.

[0066] When the FIFO submodule 34 returns the data after local clock synchronization to the training module 2, the data receiving unit 23 determines whether the returned data after local clock synchronization is valid according to the "train_gate" signal and receives the valid signal and valid data returned from the FIFO submodule 34, and then sends the valid signal and valid data to the data judgment unit 24, and the data judgment unit 24 determines whether the returned valid data is the same as the preset data. When the valid data is different from the preset data, the pulse signal generating unit 25 generates a phase modulation pulse signal and sends it to the phase adjustment submodule 102. The phase-shiftable clock can return to the initial phase position by dynamically moving forward or backward N times relative to the local clock. When the phase modulation pulse signal changes from a low level to a high level, an offset pulse signal is generated. The phase adjustment submodule 102 receives the offset pulse signal and controls the phase-shiftable clock to shift by 1 / N phases. When the phase adjustment submodule 102 receives several delayed pulse signals, the phase of the phase-shiftable clock moves a corresponding number of times with a 1 / N offset. The offset storage unit 26 records and stores the number of offsets of the phase-shiftable clock during the phase-shiftable clock offset process.

[0067] The sampling position calculation unit 27 calculates and obtains a fixed sampling position through the number of phase shift clock shifts stored in the shift storage unit 26. Figure 5 , when the phase-shiftable clock accumulates offsets until the first valid data returned is sampled to be the same as the preset data, the screening subunit 261 screens out the number of offsets of the phase-shiftable clock at this time, and the boundary storage subunit 262 stores the number of offsets of the phase-shiftable clock at this time, and the sampling position calculation unit 27 uses the number of offsets as the effective left boundary of the returned data window, defined as "left_bound". Similarly, it is necessary to continue to find the right boundary to determine the effective clock sampling interval of the returned data. At this time, the training module 2 continues to repeatedly read the preset data and wait for judgment. Since the correct boundary of the returned valid data has been found, the phase-shiftable clock continues to be moved for sampling, and there will be a period of continuous correct sampling values. Therefore, when the phase-shiftable clock is adjusted until the first valid data returned is different from the preset data, that is, the judgment is wrong, the number of offsets of the phase-shiftable clock at this time is screened and stored as the effective right boundary of the returned data window, defined as "right_bound".

[0068] The phase-shiftable clock samples the left and right boundaries of the returned valid data, and the middle position of the two boundaries is the eye diagram size of the returned data. When the phase-shiftable clock sampling finds the right boundary of the returned valid data, the sampling position calculation unit 27 performs effective interval alignment calculation on the phase-shiftable clock, and the eye diagram window is called a UI, that is, the value of right_bound minus left_bound. After resetting the PLL module 1, the edges of the local clock and the phase-shiftable clock are aligned, and the phase adjustment submodule 102 needs to shift the phase-shiftable clock by half a UI plus the value of the left boundary. At this point, the phase-shiftable clock sampling position is fixed, and the read and write data training is immediately completed. The system can stably realize the reading of the data returned by the DDR module 4.

[0069] Beneficial effects of the present invention:

[0070] The present invention uses the clock generation submodule 101 of the PLL module 1 to generate a phase-shiftable clock to sample the return data of the DDR module 4. The training module 2 accurately calculates the position of the return data of the DDR module 4, and adjusts the phase-shiftable clock to perform phase adjustment, so that the sampling can be accurately located at the position of the return data of the DDR module 4, so that the sampling frequency can be higher. Compared with the prior art, the use of the delay module is saved. The delay module is a hard-core device with a high production cost. The present invention reduces the production cost by eliminating the use of the delay module, and is also applicable to certain application scenarios that require cost and power consumption reduction.

[0071] The present invention does not use a delay module, which saves resources, and only uses a set of offset clocks, which further saves resources and has simpler logic than the traditional PLL module 1 that outputs four phase clocks that are not connected. Compared with the prior art, the prior art uses a delay module to dynamically delay the input sampling clock, which generally requires the use of a fixed multiple phase clock method. During the sampling process, multiple delay modules are required to delay the clock, which occupies more resources and affects the layout design of other functional modules. The present invention only uses a set of offset clocks and omits the use of delay modules, which provides space for the layout design of other functional modules and is more flexible, and can speed up the design progress.

[0072] The present invention can accurately locate valid data by setting a valid data positioning unit 311, further improving the accuracy and stability of sampling. The present invention uses the DQS clock signal returned by the DDR module 4 to transform into an enable judgment signal of the training module 2, effectively utilizes the read command, delays tCL cycles to generate the rdqs_gate signal to locate the valid data interval of the returned data, and in this interval, the DQS clock signal returned by the DDR module 4 is obtained and becomes the input enable signal of the FIFO submodule 34, effectively solving the problem that the data returned by the DDR module 4 is not aligned with the clock, and further improving the stability of sampling.

[0073] The systems, modules or units described in the above embodiments can be implemented by computer chips or physical configuration programs, or by products with certain functions. For the convenience of description, the above systems are described separately by functions in various units. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0074] The present invention is described with reference to the flowcharts and / or block diagrams of the system and configuration program according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0075] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0076] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0077] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0078] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0079] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0080] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A dynamic training system for DDR sampling based on FPGA, characterized by: It includes a PLL module (1), a training module (2), a DDR_PAD module (3) and a DDR module (4), wherein: The PLL module (1) comprises a clock generation submodule (101) and a phase adjustment submodule (102), wherein the clock generation submodule (101) is used to generate a local clock and a phase-shiftable clock, the phase-shiftable clock is used for data sampling, and the phase adjustment submodule (102) can perform phase adjustment on the phase-shiftable clock; The DDR module (4) is used to store preset data and send return data; The training module (2) is used to realize the generation and processing of data and the control of the DDR module (4) and the phase adjustment submodule (102) to obtain stable data returned by the DDR module (4) that can be sampled; The DDR_PAD module (3) is used to receive data and implement data conversion, and to perform local clock synchronization processing on the converted data before sending it to the training module (2) for processing.

2. The FPGA-based DDR sampling dynamic training system according to claim 1, characterized in that: The DDR_PAD module (3) comprises a CMD submodule (31), an ODDR submodule (32), an IDDR submodule (33) and a FIFO submodule (34), wherein: The CMD submodule (31) is used to receive preset data and realize read / write enable signal conversion, and send the converted preset data and read / write enable signal to the ODDR submodule (32); The ODDR submodule (32) is used to realize parallel-to-serial conversion of preset data and read-write enable signals, thereby realizing frequency increase, and the preset data and read-write enable signals after frequency increase are sent to the DDR module (4); The IDDR submodule (33) is used to receive the return data from the DDR module (4) and down-convert the return data before sending it to the FIFO submodule (34); The FIFO submodule (34) is used to receive the return data from the IDDR submodule (33), perform local clock synchronization processing on the return data to obtain valid data, and then send the valid data to the training module (2) for processing.

3. The FPGA-based DDR sampling dynamic training system as claimed in claim 2, characterized in that: The training module (2) comprises a data reading and writing unit (22), a data receiving unit (23), a data judging unit (24), a pulse signal generating unit (25), an offset storage unit (26) and a sampling position calculating unit (27), wherein: The data reading and writing unit (22) is used to send preset data and a data reading and writing enable signal to the CMD submodule (31); The data receiving unit (23) is used to receive valid data returned by the FIFO submodule (34); The data judging unit (24) is used to judge whether the valid data received by the data receiving unit (23) is the same as the preset data; The pulse signal generating unit (25) is used to generate a phase modulated pulse signal when the valid data is different from the preset data and send the signal to the phase adjustment submodule (102) so that the phase adjustment submodule (102) performs phase adjustment on the phase-shiftable clock; The offset storage unit (26) is used to store the number of offsets of the phase-shiftable clock; The sampling position calculation unit (27) is used to calculate the number of shifts of the phase-shiftable clock stored in the shift storage unit (26) and obtain a fixed sampling position.

4. The FPGA-based DDR sampling dynamic training system as claimed in claim 2, characterized in that: The CMD submodule (31) comprises a valid data locating unit (311), and the valid data locating unit (311) is used to generate a valid data signal to locate a valid data interval of data returned by the DDR module (4).

5. The FPGA-based DDR sampling dynamic training system as claimed in claim 3, characterized in that: The offset storage unit (26) comprises a screening subunit (261) and a boundary storage subunit (262), wherein: The screening subunit (261) is used to screen out the number of times the phase shiftable clock is shifted when the first returned data sampled by the phase shiftable clock is the same as the preset data, and record it as the effective left boundary left_bound; and the number of times the phase shiftable clock is shifted when the first returned data is different from the preset data after the returned data is the same as the preset data, and record it as the effective right boundary right_bound; The boundary storage subunit (262) is used to store the value of the effective left boundary left_bound and the value of the effective right boundary right_bound.

6. The FPGA-based DDR sampling dynamic training system as claimed in claim 5, characterized in that: The sampling position calculation unit (27) comprises a valid interval calculation subunit (271) and a final value calculation subunit (272), wherein: The valid interval calculation subunit (271) is used to calculate the valid interval of the phase-shiftable clock corresponding to the valid return data, that is, the value of right_bound minus left_bound; The final value calculation subunit (272) is used to calculate the final offset times of the phase-shiftable clock, i.e., left_bound+1 / 2(right_bound-left_bound).

7. The FPGA-based DDR sampling dynamic training system as claimed in claim 4, characterized in that: The return data sent by the DDR module includes a DQS clock signal and a DQ data signal. The high-level signal of the DQS clock signal pulse returned by the DDR module (4) is obtained within the valid data interval located by the valid data signal as an input enable signal of the FIFO submodule (34). The input enable signal is used to determine whether the return data is within the valid data interval.

8. The FPGA-based DDR sampling dynamic training system as claimed in claim 3, characterized in that: The DDR_PAD module (3) further comprises an inverter (5), and the valid data returned by the FIFO submodule (34) is passed through the inverter (5) to obtain a data validity determination signal, and the data validity determination signal is used to determine whether the data after being synchronized with the local clock of the FIFO submodule (34) is valid, and the data validity determination signal and the valid data are transmitted together to the data receiving unit (23).

9. The FPGA-based DDR sampling dynamic training system as claimed in claim 3, characterized in that: The training module (2) further comprises an address selection unit (21), wherein the address selection unit (21) is used to select an address of the DDR module (4) that can effectively store data.

10. The FPGA-based DDR sampling dynamic training system according to claim 1, characterized in that: The local clock and the phase-shifted clock are consistent in phase and frequency in an initial state.

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