High-frequency LVDS receiver based on 12nm technology

Abstract

The invention relates to differential signal transmission, in particular to a 12nm process-based high-frequency LVDS (Low Voltage Differential Signaling) receiver and an input stage, which are used for amplifying an external differential LVDS signal through a rail-to-rail input folding operational amplifier, effectively inhibiting the influence of common-mode interference on the signal, and realizing the high-frequency LVDS signal transmission by selecting direct current and device characteristic parameters of the differential input amplifier. The upper limit of the common-mode input range of the NMOS differential input amplifier reaches DVDD, the lower limit of the common-mode input range of the PMOS differential input amplifier reaches GND, and the NMOS differential input amplifier and the PMOS differential input amplifier are connected in parallel to realize rail-to-rail input of a common mode by utilizing the complementary characteristic of the common-mode input ranges of the NMOS differential input amplifier and the PMOS differential input amplifier; in the middle stage, the gain is further improved through a five-tube operational amplifier by adopting a fully differential input and output structure; according to the technical scheme provided by the invention, the defect that the data transmission rate is greatly limited due to relatively low maximum working frequency can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to differential signal transmission, and in particular to a high-frequency LVDS receiver based on a 12nm process. Background Art

[0002] LVDS signal transmission is a small amplitude differential current signal transmission technology, and its transmission rate can reach hundreds of megabits or even higher. Theoretically, it has the characteristics of low power consumption, high noise immunity, high switching speed, etc. In recent years, LVDS signal transmission technology has been verified in processes above 65nm and has been widely used in LAN / WAN, servers, automated measurement and other fields.

[0003] With the improvement of signal processor chip integration and process, the realization of LVDS signal transmission technology in advanced processes has brought new challenges. The function of LVDS receiver is to amplify the low-swing high-speed clock signal input from the outside, and finally output the digital signal for system use. The operating frequency of traditional LVDS receiver is affected by factors such as process advancement and circuit structure. The maximum operating frequency is only about 800MHz, which leads to a significant limitation on data transmission rate. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a high-frequency LVDS receiver based on a 12nm process, which can effectively overcome the defect of the prior art that the data transmission rate is greatly limited due to the low maximum operating frequency.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: A high-frequency LVDS receiver based on 12nm process, including input stage, intermediate stage and output stage; At the input stage, the external differential LVDS signal is amplified through a rail-to-rail input folding operational amplifier, and the influence of common-mode interference on the signal is effectively suppressed. By selecting the DC current and device characteristic parameters of the differential input amplifier, the upper limit of the common-mode input range of the NMOS differential input amplifier reaches DVDD, and the lower limit of the common-mode input range of the PMOS differential input amplifier reaches GND. By utilizing the complementary characteristics of the common-mode input ranges of the NMOS differential input amplifier and the PMOS differential input amplifier, the two are used in parallel to achieve rail-to-rail input common mode. In the middle stage, the gain is further increased by using a five-transistor op amp with a fully differential input and output structure to achieve a lower input swing. The output stage uses a five-tube operational amplifier to convert the differential signal into a single-ended signal, realizing the differential to single-ended comparator while further improving the gain, and realizing the conversion of the power supply voltage from DVDD to VDD. Finally, the comparison result of the differential LVDS signal is shaped and output through the inverter.

[0006] Preferably, the input stage comprises a PMOS tube P1, a gate of the PMOS tube P1 is connected to an external signal PVB1, a source of the PMOS tube P1 is connected to DVDD, and a drain of the PMOS tube P1 is connected to sources of the PMOS tubes P2 and P3; The gate of the PMOS tube P2 is connected to the external signal RXI_N and the gate of the NMOS tube N1, and the drain of the PMOS tube P2 is connected to the source of the NMOS tube N5 and the drain of the NMOS tube N7; The gate of the PMOS tube P3 is connected to the external signal RXI_P and the gate of the NMOS tube N2, and the drain of the PMOS tube P3 is connected to the source of the NMOS tube N4 and the drain of the NMOS tube N6; The source of the NMOS tube N1 is connected to the drain of the NMOS tube N3 and the source of the NMOS tube N2, and the drain of the NMOS tube N1 is connected to the drain of the PMOS tube P5 and the source of the PMOS tube P7; The drain of the NMOS tube N2 is connected to the drain of the PMOS tube P4 and the source of the PMOS tube P6; The gate of the NMOS tube N3 is connected to the external signal NVB1, and the source of the NMOS tube N3 is connected to GND; The gate of the PMOS tube P4 is connected to the gates of the PMOS tubes P5, PMOS tubes P6, PMOS tubes P7, NMOS tubes N4, NMOS tubes N5, and one end of the resistors R1 and R2, and the sources of the PMOS tubes P4 and PMOS tubes P5 are connected to DVDD; The drain of the PMOS tube P6 is connected to the drain of the NMOS tube N4, the gate of the NMOS tube N9, and the other end of the resistor R1; The drain of the PMOS tube P7 is connected to the drain of the NMOS tube N5, the gate of the NMOS tube N8, and the other end of the resistor R2; The gate of the NMOS transistor N6 is connected to the gate of the NMOS transistor N7 and the external signal NVB2, and the sources of the NMOS transistors N6 and NMOS transistors N7 are connected to GND.

[0007] Preferably, the intermediate stage includes a PMOS tube P8, a gate of the PMOS tube P8 is connected to a gate of the PMOS tube P9 and an external signal PVB2, a source of the PMOS tube P8 is connected to DVDD, and a drain of the PMOS tube P8 is connected to a drain of the NMOS tube N8 and a gate of the NMOS tube N11; The source of the PMOS tube P9 is connected to DVDD, and the drain of the PMOS tube P9 is connected to the drain of the NMOS tube N9 and the gate of the NMOS tube N12; The source of the NMOS tube N8 is connected to the source of the NMOS tube N9 and the drain of the NMOS tube N10; The gate of the NMOS transistor N10 is connected to the external signal NVB1, and the source of the NMOS transistor N10 is connected to GND.

[0008] Preferably, the output stage includes a PMOS tube P10, a gate of the PMOS tube P10 is connected to a gate of the PMOS tube P11, and drains of the PMOS tube P10 and the NMOS tube N11, and a source of the PMOS tube P10 is connected to VDD; The source of the PMOS tube P11 is connected to VDD, and the drain of the PMOS tube P11 is connected to the drain of the NMOS tube N12 and the input end of the inverter M1; The source of the NMOS tube N11 is connected to the source of the NMOS tube N12 and the drain of the NMOS tube N13; The gate of the NMOS tube N13 is connected to the external signal NVB1, and the source of the NMOS tube N13 is connected to GND; The output terminal of the inverter M1 is DOUT.

[0009] Compared with the prior art, the high-frequency LVDS receiver based on the 12nm process provided by the present invention can realize 1.2GHz LVDS signal transmission under the 12nm process, greatly improving the maximum operating frequency of the LVDS receiver and improving the integration of the chip, and can be applied to small-amplitude LVDS signal transmission in high-performance signal processing systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 is an overall circuit diagram of a high-frequency LVDS receiver of the present invention; Figure 2 This is a diagram of the simulation results of the 1.2 GHz operating frequency of the high-frequency LVDS receiver of the present invention. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] High-frequency LVDS receiver based on 12nm process, such as Figure 1 As shown, it includes an input stage, an intermediate stage and an output stage; At the input stage, the external differential LVDS signal is amplified through a rail-to-rail input folding operational amplifier, and the influence of common-mode interference on the signal is effectively suppressed. By selecting the DC current and device characteristic parameters of the differential input amplifier, the upper limit of the common-mode input range of the NMOS differential input amplifier reaches DVDD, and the lower limit of the common-mode input range of the PMOS differential input amplifier reaches GND. By utilizing the complementary characteristics of the common-mode input ranges of the NMOS differential input amplifier and the PMOS differential input amplifier, the two are used in parallel to achieve rail-to-rail input common mode. In the middle stage, the gain is further increased by using a five-transistor op amp with a fully differential input and output structure to achieve a lower input swing. The output stage uses a five-tube operational amplifier to convert the differential signal into a single-ended signal, realizing the differential to single-ended comparator while further improving the gain, and realizing the conversion of the power supply voltage from DVDD to VDD. Finally, the comparison result of the differential LVDS signal is shaped and output through the inverter.

[0014] ① The input stage includes a PMOS tube P1, the gate of the PMOS tube P1 is connected to the external signal PVB1, the source of the PMOS tube P1 is connected to DVDD, and the drain of the PMOS tube P1 is connected to the source of the PMOS tube P2 and the PMOS tube P3; The gate of the PMOS tube P2 is connected to the external signal RXI_N and the gate of the NMOS tube N1, and the drain of the PMOS tube P2 is connected to the source of the NMOS tube N5 and the drain of the NMOS tube N7; The gate of the PMOS tube P3 is connected to the external signal RXI_P and the gate of the NMOS tube N2, and the drain of the PMOS tube P3 is connected to the source of the NMOS tube N4 and the drain of the NMOS tube N6; The source of the NMOS tube N1 is connected to the drain of the NMOS tube N3 and the source of the NMOS tube N2, and the drain of the NMOS tube N1 is connected to the drain of the PMOS tube P5 and the source of the PMOS tube P7; The drain of the NMOS tube N2 is connected to the drain of the PMOS tube P4 and the source of the PMOS tube P6; The gate of the NMOS tube N3 is connected to the external signal NVB1, and the source of the NMOS tube N3 is connected to GND; The gate of the PMOS tube P4 is connected to the gates of the PMOS tubes P5, PMOS tubes P6, PMOS tubes P7, NMOS tubes N4, NMOS tubes N5, and one end of the resistors R1 and R2, and the source electrodes of the PMOS tubes P4 and PMOS tubes P5 are connected to DVDD; The drain of the PMOS tube P6 is connected to the drain of the NMOS tube N4, the gate of the NMOS tube N9, and the other end of the resistor R1; The drain of the PMOS tube P7 is connected to the drain of the NMOS tube N5, the gate of the NMOS tube N8, and the other end of the resistor R2; The gate of the NMOS transistor N6 is connected to the gate of the NMOS transistor N7 and the external signal NVB2, and the sources of the NMOS transistors N6 and NMOS transistors N7 are connected to GND.

[0015] ② The middle stage includes a PMOS tube P8, the gate of the PMOS tube P8 is connected to the gate of the PMOS tube P9 and the external signal PVB2, the source of the PMOS tube P8 is connected to DVDD, and the drain of the PMOS tube P8 is connected to the drain of the NMOS tube N8 and the gate of the NMOS tube N11; The source of the PMOS tube P9 is connected to DVDD, and the drain of the PMOS tube P9 is connected to the drain of the NMOS tube N9 and the gate of the NMOS tube N12; The source of the NMOS tube N8 is connected to the source of the NMOS tube N9 and the drain of the NMOS tube N10; The gate of the NMOS transistor N10 is connected to the external signal NVB1, and the source of the NMOS transistor N10 is connected to GND.

[0016] ③ The output stage includes a PMOS tube P10, the gate of the PMOS tube P10 is connected to the gate of the PMOS tube P11, as well as the drains of the PMOS tube P10 and the NMOS tube N11, and the source of the PMOS tube P10 is connected to VDD; The source of the PMOS tube P11 is connected to VDD, and the drain of the PMOS tube P11 is connected to the drain of the NMOS tube N12 and the input end of the inverter M1; The source of the NMOS tube N11 is connected to the source of the NMOS tube N12 and the drain of the NMOS tube N13; The gate of the NMOS tube N13 is connected to the external signal NVB1, and the source of the NMOS tube N13 is connected to GND; The output terminal of the inverter M1 is DOUT.

[0017] The high-frequency LVDS receiver provided by the technical solution of this application can realize 1.2GHz LVDS signal transmission under 12nm process. The simulation results are as follows Figure 2 As shown, the maximum operating frequency of the LVDS receiver is greatly improved, and the integration of the chip is improved, which can be applied to small-amplitude LVDS signal transmission in high-performance signal processing systems.

[0018] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. High-frequency LVDS receiver based on 12nm process, characterized by: It includes input stage, intermediate stage and output stage; At the input stage, the external differential LVDS signal is amplified through a rail-to-rail input folding operational amplifier, and the influence of common-mode interference on the signal is effectively suppressed. By selecting the DC current and device characteristic parameters of the differential input amplifier, the upper limit of the common-mode input range of the NMOS differential input amplifier reaches DVDD, and the lower limit of the common-mode input range of the PMOS differential input amplifier reaches GND. By utilizing the complementary characteristics of the common-mode input ranges of the NMOS differential input amplifier and the PMOS differential input amplifier, the two are used in parallel to achieve rail-to-rail input common mode. In the middle stage, the gain is further increased by using a five-transistor op amp with a fully differential input and output structure to achieve a lower input swing; The output stage uses a five-tube operational amplifier to convert the differential signal into a single-ended signal, realizing the differential to single-ended comparator while further improving the gain, and realizing the conversion of the power supply voltage from DVDD to VDD. Finally, the comparison result of the differential LVDS signal is shaped and output through the inverter.

2. The high-frequency LVDS receiver based on 12nm process according to claim 1, characterized in that: The input stage includes a PMOS tube P1, a gate of the PMOS tube P1 is connected to an external signal PVB1, a source of the PMOS tube P1 is connected to DVDD, and a drain of the PMOS tube P1 is connected to sources of the PMOS tubes P2 and PMOS tubes P3; The gate of the PMOS tube P2 is connected to the external signal RXI_N and the gate of the NMOS tube N1, and the drain of the PMOS tube P2 is connected to the source of the NMOS tube N5 and the drain of the NMOS tube N7; The gate of the PMOS tube P3 is connected to the external signal RXI_P and the gate of the NMOS tube N2, and the drain of the PMOS tube P3 is connected to the source of the NMOS tube N4 and the drain of the NMOS tube N6; The source of the NMOS tube N1 is connected to the drain of the NMOS tube N3 and the source of the NMOS tube N2, and the drain of the NMOS tube N1 is connected to the drain of the PMOS tube P5 and the source of the PMOS tube P7; The drain of the NMOS tube N2 is connected to the drain of the PMOS tube P4 and the source of the PMOS tube P6; The gate of the NMOS tube N3 is connected to the external signal NVB1, and the source of the NMOS tube N3 is connected to GND; The gate of the PMOS tube P4 is connected to the gates of the PMOS tubes P5, PMOS tubes P6, PMOS tubes P7, NMOS tubes N4, NMOS tubes N5, and one end of the resistors R1 and R2, and the sources of the PMOS tubes P4 and PMOS tubes P5 are connected to DVDD; The drain of the PMOS tube P6 is connected to the drain of the NMOS tube N4, the gate of the NMOS tube N9, and the other end of the resistor R1; The drain of the PMOS tube P7 is connected to the drain of the NMOS tube N5, the gate of the NMOS tube N8, and the other end of the resistor R2; The gate of the NMOS transistor N6 is connected to the gate of the NMOS transistor N7 and the external signal NVB2, and the sources of the NMOS transistors N6 and NMOS transistors N7 are connected to GND.

3. The high-frequency LVDS receiver based on 12nm process according to claim 2, characterized in that: The intermediate stage includes a PMOS tube P8, a gate of the PMOS tube P8 is connected to a gate of the PMOS tube P9 and an external signal PVB2, a source of the PMOS tube P8 is connected to DVDD, and a drain of the PMOS tube P8 is connected to a drain of the NMOS tube N8 and a gate of the NMOS tube N11; The source of the PMOS tube P9 is connected to DVDD, and the drain of the PMOS tube P9 is connected to the drain of the NMOS tube N9 and the gate of the NMOS tube N12; The source of the NMOS tube N8 is connected to the source of the NMOS tube N9 and the drain of the NMOS tube N10; The gate of the NMOS transistor N10 is connected to the external signal NVB1, and the source of the NMOS transistor N10 is connected to GND.

4. The high-frequency LVDS receiver based on 12nm process according to claim 3, characterized in that: The output stage includes a PMOS tube P10, a gate of the PMOS tube P10 is connected to a gate of the PMOS tube P11, and drains of the PMOS tube P10 and the NMOS tube N11, and a source of the PMOS tube P10 is connected to VDD; The source of the PMOS tube P11 is connected to VDD, and the drain of the PMOS tube P11 is connected to the drain of the NMOS tube N12 and the input end of the inverter M1; The source of the NMOS tube N11 is connected to the source of the NMOS tube N12 and the drain of the NMOS tube N13; The gate of the NMOS tube N13 is connected to the external signal NVB1, and the source of the NMOS tube N13 is connected to GND; The output terminal of the inverter M1 is DOUT.

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