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Processor for executing conditional instruction and method thereof

An execution condition, processor technology, applied in concurrent instruction execution, machine execution device, electrical digital data processing, etc., can solve the problems of occupying pipeline processing time, occupation, inefficiency of branch or jump instructions, etc., and achieve good execution performance , the effect of improving program coding density

Inactive Publication Date: 2006-08-02
SUNPLUS TECH CO LTD
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide a processor capable of executing conditional instructions and its method, which can solve the problem of inefficiency of using branch or jump instructions in processors with pipeline processing
It can also avoid the problem of occupying too many coding fields in the known technology and occupying pipeline processing time when the instruction does not need to be executed, so as to achieve the purpose of improving the code density and execution efficiency of the program

Method used

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  • Processor for executing conditional instruction and method thereof
  • Processor for executing conditional instruction and method thereof
  • Processor for executing conditional instruction and method thereof

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Embodiment Construction

[0040] 3 shows a block diagram of a processor capable of executing conditional instructions of the present invention, which mainly includes: a flag 310, an instruction fetching device 320, an instruction decoding device 330, an instruction executing device 340 and a mode switching device 350. The instruction fetching device 320 is used to fetch at least one instruction to be executed, wherein the instruction set executed by the processor includes M-bit instructions and N-bit instructions (M and N are positive integers, and M>N , such as M=32 and N=16), in the instruction set of the processor, in addition to the general M-bit and N-bit instructions, it also includes N-bit or M-bit conditional execution instructions (such as comparison instructions ), and M-bit parallel conditional execution instructions, and parallel conditional execution instructions are M-bit instructions with at least two N-bit instructions, as shown in Figure 4, a 32-bit parallel conditional execution instr...

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Abstract

The present invention proposes one kind of processor capable of executing conditional command in the M bit command set and N bit command set. The processor includes one flag, one command pick-up unit, one command decoder, one command executor to execute the command the command decoder outputs and to set the flag state based on execution result of the conditional command, and one mode switching unit. When the command the command pick-up unit picks up is one parallel conditional execution command, the mode switching unit switches the command decoder between the first N bit command and the second N bit command for the command executor to execute based on the state of the flag. The present invention also relates to the method of executing the conditional command in the processor.

Description

technical field [0001] The present invention relates to a processor, in particular to a processor capable of executing conditional instructions. The present invention also relates to a method for executing conditional instructions in the above-mentioned processor. Background technique [0002] When a general processor executes a conditional instruction, it will generate a situation where the condition is true and the condition is not true, and use the branch (branch) or jump (jump) instruction to execute the subsequent program according to the result. This situation is due to the use of branches. Or skip instructions will refresh the instructions already in the pipeline in order to read the instructions at the destination of the branch or jump instruction, which is quite inefficient for processors with pipeline processing. [0003] Aiming at the inefficiency of using branch or jump instructions for processors with pipeline processing, in the US Patent No. 5,961,633 announce...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/00G06F9/38G06F9/48
Inventor 梁伯嵩
Owner SUNPLUS TECH CO LTD
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