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A fast divider with divisor 15í‡2n

A device and fast technology, applied in the field of fast dividers, can solve the problems of many components, slow operation speed and complex structure.

Inactive Publication Date: 2004-11-17
HEBEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention aims to solve the problems of complex structure, many components and parts, and slow operation speed in the existing divider technology, thus providing the first divisor with a divisor of 15×2 n , where n is a fast divider for 0, 1, 2, 3, ... n integers

Method used

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  • A fast divider with divisor 15í‡2n
  • A fast divider with divisor 15í‡2n
  • A fast divider with divisor 15í‡2n

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] The dividend is 0~119×2 n +2 n -1, the divisor is 15×2 n , a divider with fast operation when n=0. Its circuit schematic diagram is as figure 1 shown. The connection relationship of the circuit is that I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, which constitute the binary dividend I1I2I3I4I5I6I7; I1, I2, I3, I4, I5, I6, and I7 are sequentially connected to the adder ADD435 Y3 pin, Y2 pin, Y1 pin, X4 pin, X3 pin, X2 pin, X1 pin; I1, I2, I3 are simultaneously connected to the adder ADD313 1 The X3 pin, X2 pin, X1 pin of ADD435; the output F1 pin, F2 pin, F3 pin, F4 pin of ADD435 are connected to the X1 pin, X2 pin, X3 pin, X4 pin of the adder ADD414 in turn; the output F5 pin of ADD435 is connected to the adder ADD313 1 The Y1 pin of the adder ADD414 is connected to the Y1 pin of the adder ADD414 at the same time; the output F1 pin, F2 pin, F3 pin, and F4 pin of the ADD414 are connected to the 1 pin, 2 pin, 3 pin, and 4 pin of the AND gat...

Embodiment 2

[0044] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , when n=0, the circuit schematic diagram of the divider with fast operation is as follows figure 2 As shown, the connection relationship of the circuit is that I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, which constitute the binary dividend I1I2I3I4I5I6I7; Pin, 2 pin, 1 pin, 4 pin; the output pin 5 of the AND gate A1 is connected to the output O0 pin of the divider; the adder ADD313 2 The output terminals F1, F2, and F3 of the divider are connected in turn to the output O3, O2, and O1 of the divider to form the binary quotient O0O1O2O3 of the division result; the output 3 feet of the AND gates A3, A4, A5, and A6 are connected in turn The output terminals O4, O5, O6, and O7 of the divider form the binary remainder O4O5O6O7 of the division result; other circuit connections are the same as those in Embodiment 1.

[0045] When I1I2I3I4I5I6I7=(1000110)B=(70)D, because I1, I2, I3, and I4...

Embodiment 3

[0055] The dividend is 0~239, and the divisor is 15×2 n , when n=1, the circuit schematic diagram of the fast operation divider is as follows image 3 As shown, the connection relationship of its circuit is in figure 1 Based on the addition of a connection from input to output I8 1 -O8 1 . When ADD435 adopts four-bit binary numbers plus four-bit binary numbers and five-bit adders, all positions other than the lowest three bits of the second addend are 0. Other circuit connections are the same as in Embodiment 1.

[0056] When I1I2I3I4I5I6I7I8 1 During =(11000111) B=(199) D, because X4, X3, X2, X1 of ADD435 constitute the first addend of ADD435, Y3, Y2, Y1 of ADD435 constitute the second addend of ADD435, the ADD435 like this The first addend is (0011)B, the second addend is (110)B, (0011)B+(110)B=(01001)B, so F5, F4, F3, F2, F1 of ADD435 are respectively 0, 1, 0, 0, 1; ADD435 we use a four-digit binary number plus a four-digit binary number and a five-bit adder to imple...

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PUM

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Abstract

The invention is a kind of divider whose divisor is 15í‡2n. The character lies in: it uses different adder, and-gate or not gate to form the divider, the input end is the binary dividend, one output end forms the binary quotient of the dividing result, and another end output the binary remainder of the dividing. The divider can carry on division whose divisor is 15í‡2n, the dividend is 0-1272n +2n -1, (n=0, 1, 2, 3®®n). The divider is simple, the cost is low.

Description

technical field [0001] The invention belongs to a divider in an electronic device, in particular to a divisor whose divisor is 15×2 n The fast divider of , where n is 0, 1, 2, 3, ... n integers. Background technique [0002] Among the various operations of digital signal processing, division is the most complex operation with the most potential to be tapped. In general-purpose CPUs and DSPs, a divider is often not specifically implemented with hardware, because the proportion of division in general applications is very small, and the design of the divider is much more complicated than other computing components, so the usual practice It is to write software on the basis of other computing components such as ALU and / or multiplier to form a division subroutine. However, in specific application fields such as number system conversion and data unpacking, the situation is different. If the division operation occupies a considerable proportion, simply using software for division...

Claims

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Application Information

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IPC IPC(8): G06F7/52
Inventor 武金木武优西李艳姚芳李波
Owner HEBEI UNIV OF TECH