Electrostatic-proof protection structure using NMOS

Abstract

In the invention, NMOS with grid being connected to ground is as basic part to constitute static protection circuit. Number of NMOS is even, and at least is four. Using N well at drain pole injects NWELL enhanced NMOS triggered at low voltage to drain area. Each NMOS is setup at centers of the static protection circuit, and their grid poles are connected to each other and their drain poles are connected to each other. Besides NMOS setup in centers, drain poles of NMOS at two sides are connected, and their source poles and grid poles are connected respectively in parallel. Source poles of NMOS in centers are connected to base pole of parasitic NPN of NMOS at two sides connected in parallel. When parasitic NPN of NMOS at centers are in on and effusion state, current is shunted to parasitic NPN of NMOS at two sides also so as to turn to on state between base pole and emitter of NMOS at two sides. The invention conducts effusion uniformly, and raises ESD protective power.

Description

technical field [0001] The invention relates to an antistatic circuit structure, in particular to an antistatic protection structure using NMOS. Background technique [0002] The current popular process technology uses CMOS (Complementary Metal-Oxide-Semiconductor Transistor) as an electrostatic discharge (ESD, ElectroStatic Discharge) protection device. When ESD occurs, the discharged electrostatic charge will cause the protection tube Nmos ( The parasitic triode of N-channel metal-oxide semiconductor (N-channel metal-oxide semiconductor) is turned on, as shown in Figure 3, and the phenomenon of Snapback (that is, step recovery) will occur, as shown in Figure 4; when entering normal effusion Before the BC region of the state, the protection tube needs to reach the turn-on voltage of point A. The turn-on voltage is determined by the substrate current and substrate resistance formed by the reverse leakage of the PN junction at the drain end. Because the circuit structure wil...

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Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide an anti-static protection structure using NMOS, which can solve the ESD protection ability caused by the inability of the protection tube to uniformly conduct and discharge when the GGNMOS (Gate Ground NMOS grid-grounded NMOS) structure is used as ESD protection. not high problem

[0005] In the case of not changing the process conditions, by changing the connection mode of the parallel NMOS and adding NWELL injection in the drain region, the principle that the NMOS can be triggered at a low voltage effectively solves the problem that the turn-on voltage of the parallel NMOS protection device is not stable when ESD occurs. First, the problem that the ESD protection ability cannot be fully exerted

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