Methods for fabricating semiconductor devices having local contacts

a technology of local contacts and semiconductors, applied in the direction of semiconductor/solid-state device manufacturing, electric devices, solid-state devices, etc., can solve the problems of reducing yield and difficulty in avoiding inadvertent electrical connection

Inactive Publication Date: 2012-07-26
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the size and spacing of the transistors decrease, it is more difficult to avoid inadvertent creation of electrical connections between adjacent devices, which, in turn, reduces yield.

Method used

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  • Methods for fabricating semiconductor devices having local contacts
  • Methods for fabricating semiconductor devices having local contacts
  • Methods for fabricating semiconductor devices having local contacts

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Embodiment Construction

[0010]The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

[0011]FIGS. 1-9 illustrate a CMOS semiconductor device structure 100 and related process steps for fabricating the CMOS semiconductor device structure 100 with conductive electrical contacts (also referred to herein as local contacts) to doped source / drain regions formed in a semiconductor substrate. Although the subject matter is described herein in the context of a CMOS semico...

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Abstract

Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure that includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact that is electrically connected to the doped region within the first layer and the second layer.

Description

TECHNICAL FIELD[0001]Embodiments of the subject matter generally relate to semiconductor device fabrication methods, and more particularly, relate to fabrication methods for forming local contacts to doped regions formed in a semiconductor substrate.BACKGROUND[0002]Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are the core building block of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processor devices, can include millions of transistors. For such devices, decreasing transistors size, and thus increasing transistor density, has traditionally been a high priority in the semiconductor manufacturing industry. As the size and spacing of the transistors decrease, it is more difficult to avoid inadvertent creation of electrical connections between adjacent devices, which, in turn, reduces yield.BRIEF SUMMARY[0003]A method is provided for fabricating a semiconductor device structure. The semiconductor...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L21/768
CPCH01L21/823412H01L21/823425H01L21/823475H01L21/823807H01L21/823814H01L21/823871H01L29/78H01L2924/0002H01L29/7843H01L23/53295H01L21/76801H01L2924/00
InventorRICHTER, RALFHUISINGA, TORSTENHEINRICH, JENS
OwnerGLOBALFOUNDRIES INC