Vertical transistor with hardening implantation

a technology of vertical transistors and implantation holes, which is applied in the direction of bulk negative resistance effect devices, basic electric elements, electric devices, etc., can solve the problems of limiting the size of switching devices to achieve greater areal densities, the memory cell is the size of such devices, and it is difficult to form the pillar structure of vertical transistors. to achieve the effect of improving performan

Inactive Publication Date: 2014-04-10
SEAGATE TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patent is about a process for making a better vertical transistor. It uses a hardening implant step to make the side surfaces of the transistor rounded while keeping the top surface flat. This allows for easier further processing. The method also includes the formation of a gate oxide layer on the rounded side surfaces. The technical effect of this patent is a better performing vertical transistor with improved performance.

Problems solved by technology

While operable, a limitation with the use of MOSFETs and other types of switching devices in a memory cell is the areal extent (size) of such devices.
Since this is significantly larger than the areal size of many types of memory elements, the switching device size can be a limiting factor in achieving greater areal densities in a memory array.
While advantageously promoting an enhanced areal data density, it can be difficult to form the pillar structure of the vertical transistor so that the transistor can operate optimally.

Method used

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  • Vertical transistor with hardening implantation
  • Vertical transistor with hardening implantation
  • Vertical transistor with hardening implantation

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Embodiment Construction

[0031]In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. The definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.

[0032]Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the ...

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Abstract

A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

Description

CROSS-REFERENCE[0001]This application is a divisional of application Ser. No. 12 / 891,966 filed Sep. 28, 2010, the contents of each is hereby incorporated by reference in its entirety.BACKGROUND[0002]Solid state memories (SSMs) provide an efficient mechanism for storing and transferring data in a wide variety of applications, such as hand-held portable electronic devices. Individual memory cells within such memories can be volatile or non-volatile, and can store data by the application of suitable write currents to the cells to store a sequence of bits. The stored bits can be subsequently read during a read access operation by applying suitable read currents and sensing voltage drops across the cells.[0003]Some SSM cell configurations employ a memory element coupled to a channel based switching device such as a metal oxide semiconductor field effect transistor (MOSFET). The switching device provides selective access to the memory element during read and write operations. Examples of ...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L45/00
CPCH01L45/1206H01L45/1233H10B63/34H10B61/22H10N70/826H10N70/253
InventorKIM, YOUNG PILLEE, HYUNG-KEWMANOS, PETER NICHOLASJUNG, CHULMINKHOURY, MAROUN GEORGESSETIADI, DADI
OwnerSEAGATE TECH LLC