Three-dimensional flash memory and its array layout structure

Abstract

The present invention discloses a three-dimensional flash memory and its array layout structure. The three-dimensional flash memory includes a gate stack structure, an annular channel column, a first source / drain column, a second source / drain column and a charge storage structure. The gate stack structure is arranged on a dielectric substrate and includes a plurality of gate layers electrically insulated from each other. The annular channel column is arranged on the dielectric substrate and penetrates the gate stack structure. The first source / drain column and the second source / drain column are arranged on the dielectric substrate and are located in the channel column and penetrate the gate stack structure, wherein the first source / drain column and the second source / drain column are separated from each other and are respectively connected to the channel column. The charge storage structure is arranged between each of the plurality of gate layers and the channel column.

Description

Technical Field

[0001] The invention relates to a three-dimensional flash memory and its array layout, and in particular to a three-dimensional flash memory and its array layout structure. Background Art

[0002] Non-volatile memory (eg, flash memory) has become a widely used memory in personal computers and other electronic devices because it has the advantage that the stored data will not disappear after power failure.

[0003] The three-dimensional flash memory commonly used in the industry at present includes NOR flash memory and NAND flash memory. In addition, another three-dimensional flash memory is AND flash memory, which can be applied to multi-dimensional flash memory arrays and has high integration and high area utilization, and has the advantages of fast operation speed. Therefore, the development of three-dimensional flash memory has gradually become the current trend. Summary of the invention

[0004] The invention provides a three-dimensional flash memory, wherein an annular channel column is arranged in a gate stack structure, and two source / drain columns are arranged in the channel column and connected to the channel column.

[0005] The present invention provides a three-dimensional flash memory array layout structure, which includes the above-mentioned three-dimensional flash memory.

[0006] The three-dimensional flash memory of the present invention comprises a gate stack structure, an annular channel column, a first source / drain column, a second source / drain column and a charge storage structure. The gate stack structure is arranged on a dielectric substrate and comprises a plurality of gate layers electrically insulated from each other. The annular channel column is arranged on the dielectric substrate and penetrates the gate stack structure. The first source / drain column and the second source / drain column are arranged on the dielectric substrate and are located in the channel column and penetrate the gate stack structure, wherein the first source / drain column and the second source / drain column are separated from each other and are respectively connected to the channel column. The charge storage structure is arranged between each of the plurality of gate layers and the channel column.

[0007] In one embodiment of the three-dimensional flash memory of the present invention, an insulating column is disposed between the first source / drain column and the second source / drain column.

[0008] In an embodiment of the three-dimensional flash memory of the present invention, the first source / drain column and the second source / drain column each include a central portion and a peripheral portion surrounding the central portion, and the doping concentration of the central portion is greater than the doping concentration of the peripheral portion.

[0009] In an embodiment of the three-dimensional flash memory of the present invention, each of the first source / drain pillar and the second source / drain pillar includes a central portion and a peripheral portion surrounding the central portion, and the central portion includes a metal silicide layer.

[0010] In one embodiment of the three-dimensional flash memory of the present invention, it also includes a first buried column and a second buried column arranged in the dielectric substrate, wherein the first buried column is connected to the first source / drain column, and the second buried column is connected to the second source / drain column.

[0011] In an embodiment of the three-dimensional flash memory of the present invention, the charge storage structure covers the upper surface and the lower surface of each of the plurality of gate layers.

[0012] In an embodiment of the three-dimensional flash memory of the present invention, the charge storage structure covers the outer surface of the channel pillar.

[0013] In an embodiment of the three-dimensional flash memory of the present invention, the channel column is continuous in its extension direction.

[0014] In an embodiment of the three-dimensional flash memory of the present invention, the channel column is discontinuous in its extension direction, and the channel column only corresponds to the position of each of the plurality of gate layers.

[0015] In an embodiment of the three-dimensional flash memory of the present invention, the channel column includes a plurality of parts, the plurality of parts are arranged in sequence in the extension direction of the channel column and do not contact each other, and the plurality of parts each correspond to a position of one of the plurality of gate layers.

[0016] In an embodiment of the three-dimensional flash memory of the present invention, the three-dimensional flash memory further includes a first transistor and a second transistor, wherein the first transistor is electrically connected to the first source / drain column, and the second transistor is electrically connected to the second source / drain column.

[0017] In one embodiment of the three-dimensional flash memory of the present invention, the first transistor and the second transistor are composed of a transistor gate layer, a first transistor channel column, a second transistor channel column, a first gate insulating layer and a second gate insulating layer. The transistor gate layer is stacked on the gate stack structure and is electrically insulated from the gate stack structure. The first transistor channel column penetrates the transistor gate layer and is connected to the first source / drain column. The second transistor channel column penetrates the transistor gate layer and is connected to the second source / drain column. The first gate insulating layer is disposed between the first transistor channel column and the transistor gate layer. The second gate insulating layer is disposed between the second transistor channel column and the transistor gate layer. One end of the first transistor channel column relative to the first source / drain column has a first doped region. One end of the second transistor channel column relative to the second source / drain column has a second doped region.

[0018] In one embodiment of the three-dimensional flash memory of the present invention, charges are locally trapped in the charge storage structure adjacent to the first source / drain column and / or adjacent to the second source / drain column.

[0019] In one embodiment of the three-dimensional flash memory of the present invention, multiple three-dimensional flash memories are stacked on each other, and the first source / drain column of the three-dimensional flash memory in the upper layer is connected to the first source / drain column of the three-dimensional flash memory in the lower layer, and the second source / drain column of the three-dimensional flash memory in the upper layer is connected to the second source / drain column of the three-dimensional flash memory in the lower layer.

[0020] In one embodiment of the three-dimensional flash memory of the present invention, the gate stack structure has parallel channels on opposite sides, and from a top view, the connection between the first source / drain column and the second source / drain column is parallel or perpendicular to the extension direction of the channel.

[0021] In one embodiment of the three-dimensional flash memory of the present invention, parallel channels are provided at opposite sides of the gate stack structure, and from a top view, an acute angle is formed between the connection between the first source / drain column and the second source / drain column and the extension direction of the channel.

[0022] In one embodiment of the three-dimensional flash memory of the present invention, it also includes a conductive layer arranged on the dielectric substrate and adjacent to at least one side wall of the gate stack structure, wherein the conductive layer extends along the at least one side wall of the gate stack structure, and the two opposite end portions of the conductive layer in its extension direction each have an electrical connection point.

[0023] The three-dimensional flash memory array layout of the present invention comprises a plurality of the above-mentioned three-dimensional flash memories, a plurality of circuit patterns and a plurality of conductive lines. The plurality of three-dimensional flash memories are arranged in an array on the dielectric substrate. The plurality of circuit patterns are each electrically connected to one of the first source / drain column and the second source / drain column of the plurality of three-dimensional flash memories. The plurality of conductive lines are each electrically connected to a corresponding one of the plurality of circuit patterns through a contact window, wherein the plurality of conductive lines are arranged parallel to each other.

[0024] In one embodiment of the three-dimensional flash memory array layout of the present invention, each of the plurality of line patterns includes a first portion extending along the column direction of the array and a second portion extending along the row direction of the array. The first portion is connected to one of the first source / drain column and the second source / drain column. The contact window is disposed on the second portion, and the plurality of conductive lines extend along the row direction.

[0025] In an embodiment of the three-dimensional flash memory array layout of the present invention, the plurality of conductive lines include source lines or bit lines.

[0026] Based on the above, in the three-dimensional flash memory of the present invention, the annular channel column is disposed in the gate stack structure, and two source / drain columns are disposed in the channel column and connected thereto. In this way, the three-dimensional flash memory of the present invention can have high integration and high area utilization, and meet the requirements of high operating speed.

[0027] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1A to 1E It is a schematic top view of the manufacturing process of a three-dimensional flash memory according to the first embodiment of the present invention.

[0029] FIG. 2A to FIG. 2E Based on Figures 1A to 1E Schematic diagram of the cross-section of the manufacturing process of the three-dimensional flash memory shown by the AA' section line.

[0030] Figure 3 FIG. 4 is a schematic diagram of an array layout of a three-dimensional flash memory according to a first embodiment of the present invention.

[0031] Figure 4 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory according to a second embodiment of the present invention.

[0032] Figure 5 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory according to a third embodiment of the present invention.

[0033] Figure 6FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory according to a fourth embodiment of the present invention.

[0034] Figure 7 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory according to a fifth embodiment of the present invention.

[0035] Figure 8 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory according to a sixth embodiment of the present invention.

[0036] Fig. 9 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory according to a seventh embodiment of the present invention.

[0037] Fig.10 FIG. 4 is a schematic top view of a three-dimensional flash memory according to another embodiment of the present invention.

[0038] Fig.11 FIG. 4 is a schematic top view of a three-dimensional flash memory according to another embodiment of the present invention.

[0039] Fig.12 FIG. 4 is a cross-sectional schematic diagram of a three-dimensional flash memory according to another embodiment of the present invention.

[0040] Fig.13 FIG. 4 is a schematic top view of a three-dimensional flash memory according to another embodiment of the present invention.

[0041]

Explanation of symbols

[0042] 10, 40, 50, 60, 70, 80, 90: 3D flash memory

[0043] 12: Storage unit

[0044] 100: Dielectric substrate

[0045] 101a, 101b: Channel

[0046] 102: Laminated structure

[0047] 103a, 103b: extension direction

[0048] 104, 114, 116, 806, 810: Insulation layer

[0049] 105: Online 106: Sacrificial Layer

[0050] 107: Conductive layer

[0051] 108, 118, 120: Opening

[0052] 109a, 109b: electrical connection points

[0053] 110, 902: Charge storage structure

[0054] 112: Channel layer

[0055] 112a, 112b, 112c: Partial

[0056] 122, 402, 502: first source / drain column

[0057] 124, 404, 504: Second source / drain column

[0058] 126: Gate layer

[0059] 300: Line pattern

[0060] 302: Part 1

[0061] 304: Part 2

[0062] 306: Bit line

[0063] 402a, 404a, 502a, 504a: Central part

[0064] 402b, 404b, 502b, 504b: Peripheral part

[0065] 602: First embedded column

[0066] 604: Second embedded column

[0067] 802: First transistor

[0068] 804: Second transistor

[0069] 808: Transistor Gate Layer

[0070] 812: Gate insulation layer

[0071] 814: Transistor channel column

[0072] 816: Doping area DETAILED DESCRIPTION

[0073] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0074] Figures 1A to 1E It is a schematic top view of the manufacturing process of a three-dimensional flash memory according to the first embodiment of the present invention. FIG. 2A to FIG. 2E Based on Figures 1A to 1E Schematic diagram of the cross-section of the manufacturing process of the three-dimensional flash memory shown by the AA' section line.

[0075] First, refer to Figure 1A and Figure 2A, a stacked structure 102 is formed on a dielectric substrate 100. The dielectric substrate 100 is, for example, a dielectric layer formed on a silicon substrate, such as a silicon oxide layer. In the present embodiment, the stacked structure 102 is composed of an insulating layer 104 and a sacrificial layer 106 which are sequentially and alternately stacked on the dielectric substrate 100. In other embodiments, the stacked structure 102 may be composed of a sacrificial layer 106 and an insulating layer 104 which are sequentially and alternately stacked on the dielectric substrate 100. In addition, in the present embodiment, the topmost layer of the stacked structure 102 is an insulating layer 104. The insulating layer 104 is, for example, a silicon oxide layer. The sacrificial layer 106 is, for example, a silicon nitride layer. In the present embodiment, the stacked structure 102 has 4 layers of insulating layers 104 and 3 layers of sacrificial layers 106, but the present invention is not limited thereto. In other embodiments, more layers of insulating layers 104 and more layers of sacrificial layers 106 may be formed according to actual needs.

[0076] Next, an opening 108 is formed in the stacked structure 102. In the present embodiment, the opening 108 exposes the dielectric substrate 100, but the present invention is not limited thereto. In other embodiments, when the bottom layer of the stacked structure 102 is the insulating layer 104, the bottom of the opening 108 may be located in the bottom insulating layer 104, that is, the opening 108 does not expose the dielectric substrate 100. Alternatively, in other embodiments, the bottom of the opening 108 may be located in the dielectric substrate 100. In the present embodiment, the opening 108 has a circular profile from a top view, but the present invention is not limited thereto. In other embodiments, the opening 108 may have a profile of other shapes, such as a polygon.

[0077] Then, refer to Figure 1B and Figure 2B, a charge storage structure 110 is formed on the inner surface of the opening 108. In the present embodiment, the charge storage structure 110 is, for example, composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence. The charge storage structure 110 is formed by, for example, sequentially forming a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer on the top surface of the uppermost insulating layer 104 and on the inner surface and bottom of the opening 108, and then performing an anisotropic etching process to remove the silicon oxide layer and the silicon nitride layer on the insulating layer 104 and the bottom of the opening 108. Next, a channel layer 112 is formed on the charge storage structure 110. The channel layer 112 is, for example, an undoped polysilicon layer. The channel layer 112 is formed by, for example, forming a channel material layer on the top surface of the uppermost insulating layer 104 and on the inner surface and bottom of the opening 108, and then performing an anisotropic etching process to remove the channel material layer on the insulating layer 104 and the bottom of the opening 108. In the present embodiment, since the channel layer 112 is formed on the inner surface of the opening 108, the channel layer 112 can be regarded as an annular channel column, and the channel layer 112 is continuous in its extension direction (between the top and the bottom of the opening 108). "The channel layer 112 is continuous in its extension direction" means that the channel layer 112 is integral in its extension direction and is not divided into a plurality of unconnected parts. In the present embodiment, since the opening 108 has a circular profile when viewed from a top view, the channel column also has a circular profile when viewed from a top view, but the present invention is not limited thereto. In other embodiments, depending on the shape of the opening 108, the channel column may also have a profile of other shapes (e.g., a polygon) when viewed from a top view. In addition, the charge storage structure 110 is located between the channel layer 112 and the inner surface of the opening 108, and thus covers the outer surface of the channel column (channel layer 112).

[0078] Next, an insulating layer 114 is formed in the opening 108. The insulating layer 114 is, for example, a silicon oxide layer. The insulating layer 114 is formed by, for example, a chemical vapor deposition process. Importantly, the insulating layer 114 does not fill the opening 108, but retains the central portion of the opening 108. Afterwards, an insulating layer 116 is formed in the opening 108 to fill the central portion of the opening 108. In the present embodiment, the insulating layer 116 can be regarded as an insulating column. The insulating layer 116 is, for example, a silicon nitride layer. The insulating layer 116 is formed by, for example, a chemical vapor deposition process. In other embodiments, the opening 108 may be first filled with the insulating layer 114, and then an opening exposing the dielectric substrate 100 is formed in the insulating layer 114 and the opening is filled with the insulating layer 116.

[0079] Then, refer to Figure 1C and Figure 2C, forming an opening 118 and an opening 120 in the insulating layer 114. The opening 118 and the opening 120 expose the dielectric substrate 100. In the present embodiment, the opening 118 and the opening 120 have a circular profile when viewed from a top view, but the present invention is not limited to this. In other embodiments, the opening 118 and the opening 120 may have profiles of other shapes, such as a polygon. In the present embodiment, the opening 118 and the opening 120 are respectively formed on opposite sides of the insulating layer 116 and are not in contact with the insulating layer 116 and the channel layer 112, but the present invention is not limited to this. In other embodiments, the opening 118 and the opening 120 may be in contact with the insulating layer 116 and / or the channel layer 112. The opening 118 and the opening 120 are used to define the position of the source / drain of the three-dimensional flash memory of the present embodiment.

[0080] Next, refer to Figure 1D and Figure 2D , the size of the opening 118 and the opening 120 is enlarged so that the opening 118 and the opening 120 are respectively in contact with the insulating layer 116 and the channel layer 112. In the present embodiment, the method of enlarging the size of the opening 118 and the opening 120 is, for example, to perform an anisotropic etching process on the opening 118 and the opening 120. In detail, when performing the anisotropic etching process, the insulating layer 114 (silicon oxide layer) around the opening 118 and the opening 120 will be removed, and the insulating layer 116 (silicon nitride layer) and the channel layer 112 (polysilicon layer) can be used as etching stop layers. In this way, the enlarged opening 118 and the opening 120 can be in contact with the insulating layer 116 and the channel layer 112. Then, a doped polysilicon layer is formed in the expanded openings 118 and 120 to form the first source / drain column 122 and the second source / drain column 124 of the three-dimensional flash memory of this embodiment. In this way, the first source / drain column 122 and the second source / drain column 124 can be located in the annular channel column (channel layer 112), separated from each other by the insulating column (insulating layer 116), and connected to the channel column (channel layer 112).

[0081] Afterwards, refer to Figure 1E and Figure 2E , the sacrificial layer 106 in the stacked structure 102 is removed to form a channel between adjacent insulating layers 104. The method of removing the sacrificial layer 106 is well known to those skilled in the art and will not be described in detail herein. After removing the sacrificial layer 106, a gate layer 126 is formed in the formed channel. The material of the gate layer 126 is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ) or cobalt silicide (CoSi x). In addition, in other embodiments, before forming the gate layer 126, a buffer layer and a barrier layer may be sequentially formed in the channel. The material of the buffer layer is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides or combinations thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or combinations thereof.

[0082] In this way, the manufacturing of the three-dimensional flash memory 10 of this embodiment is completed. In the three-dimensional flash memory 10 of this embodiment, a gate stack structure consisting of three gate layers 126 is arranged on a dielectric substrate 100, an annular channel column (channel layer 112) is arranged on the dielectric substrate 100 and penetrates the gate stack structure, a first source / drain column 122 and a second source / drain column 124 are arranged on the dielectric substrate 100 and are located in the channel column and penetrate the gate stack structure, and a charge storage structure 110 is arranged between each gate layer 126 and the channel column. In addition, in the annular channel column, the first source / drain column 122 and the second source / drain column 124 are each connected to the channel column and separated from each other by an insulating column.

[0083] In this embodiment, if Figure 1E As shown, the left side of the gate stack structure has a channel 101a, and the right side of the gate stack structure has a channel 101b, and the extension direction 103a of the channel 101a is parallel to the extension direction 103b of the channel 101b. In addition, the connection 105 between the first source / drain column 122 and the second source / drain column 124 is perpendicular to the extension directions 103a and 103b, but the present invention is not limited to this. In other embodiments, the connection 105 between the first source / drain column 122 and the second source / drain column 124 can be parallel to the extension directions 103a and 103b (such as Fig.10 Alternatively, the connection 105 between the first source / drain column 122 and the second source / drain column 124 may have an acute angle with the extension directions 103a and 103b (eg Fig.11 The above-mentioned angle is preferably 45°.

[0084] In addition, in this embodiment, the three-dimensional flash memory 10 has a plurality of storage units 12, and the plurality of three-dimensional flash memories 10 can be arranged in an array. Figure 1E and Figure 2EAs shown, in the three-dimensional flash memory 10, there are three storage units 12 stacked on top of each other, and 18 three-dimensional flash memories 10 are arranged in an array, wherein the three-dimensional flash memories 10 in the first and third columns are aligned with each other, the three-dimensional flash memories 10 in the second and fourth columns are aligned with each other, and the three-dimensional flash memories 10 in two adjacent columns are staggered with each other. In addition, the number, position, orientation, spacing, etc. of these three-dimensional flash memories 10 are not limited to Figure 1E shown.

[0085] In addition, in another embodiment, the three-dimensional flash memory of the present invention may further include a conductive layer as a heater to heat the gate stack structure. Fig.13 As shown, the conductive layer 107 is disposed on the dielectric substrate 100 and is adjacent to the sidewall of the gate stack structure and extends along the sidewall of the gate stack structure. In addition, in the present embodiment, the conductive layer 107 is disposed beside two opposite sidewalls of the gate stack structure, but the present invention is not limited thereto. In other embodiments, the conductive layer 107 may be disposed only beside one sidewall of the gate stack structure, or the conductive layer 107 may be disposed around the gate stack structure, depending on actual needs. In the present embodiment, the method of using the conductive layer 107 as a heater is to apply a relatively high voltage and a relatively low voltage to the electrical connection points 109a and 109b at the opposite ends of the conductive layer 107 to form a voltage difference. In this way, a current can be generated. When the current passes through the conductive layer 107, the conductive layer 107 generates heat, which can heat the adjacent gate stack structure.

[0086] Generally speaking, as the size of electronic devices is miniaturized, the spacing between components is also reduced. For the array composed of the three-dimensional flash memory 10 of the present embodiment, in order to avoid the difficulty in configuring the bit lines electrically connected to these three-dimensional flash memories 10 due to the small spacing between adjacent three-dimensional flash memories 10, the present invention proposes a three-dimensional flash memory array layout. Figure 1E The structure shown is used as an example to explain this.

[0087] Figure 3 FIG. 1 is a schematic diagram of an array layout of a three-dimensional flash memory according to a first embodiment of the present invention. Figure 3 In Figure 1E The structure shown is used as an example to illustrate the three-dimensional flash memory array layout of the present invention. In the following, when the first source / drain column 122 is used as the source, the second source / drain column 124 is used as the drain, and the conductive line connected to the first source / drain column 122 is called a source line, and the conductive line connected to the second source / drain column 124 is called a bit line.

[0088] Please refer to Figure 3In order to operate the three-dimensional flash memory 10, after the three-dimensional flash memory 10 is manufactured, a conductive line electrically connected to the three-dimensional flash memory 10 is formed above the three-dimensional flash memory 10. In the present embodiment, a conductive line electrically connected to the first source / drain column 122 as a source is formed as a source line, and a conductive line electrically connected to the second source / drain column 124 as a drain is formed as a bit line, and these source lines and bit lines are arranged parallel to each other without contacting each other. However, for the three-dimensional flash memories 10 of the first and third columns aligned with each other or the three-dimensional flash memories 10 of the second and fourth columns aligned with each other, if the spacing between the components is too small, the conductive lines formed subsequently will not be arranged in a manner of being arranged parallel to each other without contacting each other.

[0089] Therefore, in the present embodiment, before forming these conductive lines, a line pattern 300 electrically connected to the first source / drain column 122 and the second source / drain column 124 is formed on each three-dimensional flash memory 10. In the present embodiment, these line patterns 300 are identical to each other, but the present invention is not limited thereto. In other embodiments, these line patterns 300 are different from each other. In the present embodiment, the line pattern 300 has an "L"-shaped pattern, but the present invention is not limited thereto. In detail, the line pattern 300 includes a first portion 302 and a second portion 304, wherein the first portion 302 extends along the column direction of the array of the three-dimensional flash memory 10, and the second portion 304 extends along the row direction of the array of the three-dimensional flash memory 10. In addition, the first portion 302 is connected to the first source / drain column 122 or the second source / drain column 124. After forming the line pattern 300, a generally known process step can be performed to form a conductive line 306 electrically connected to the line pattern 300 through a contact window (not shown) located on the second portion 304.

[0090] In the three-dimensional flash memory array layout of this embodiment, by using the line pattern 300 and adjusting the position of the line pattern 300, the conductive lines 306 electrically connected to the first source / drain pillar 122 and the second source / drain pillar 124 can be arranged in parallel without contacting each other. In this way, the conductive lines (source lines and bit lines) can be simply arranged when the spacing between components is too small, and the difficulty of layout design is reduced.

[0091] In addition, in this embodiment, the source lines and the bit lines are arranged in parallel, but the present invention is not limited thereto. In other embodiments, the above structure can also be applied to a three-dimensional flash memory array layout in which the source lines and the bit lines are interlaced with each other.

[0092] The operation of the storage unit 12 in the three-dimensional flash memory 10 is described below.

[0093] For the three-dimensional flash memory 10, each memory cell 12 can be operated individually. An operating voltage can be applied to the first source / drain column 122, the second source / drain column 124 and the gate layer 126 of the memory cell 12 to perform programming, reading or erasing operations. When a voltage is applied to the first source / drain column 122 and the second source / drain column 124, since the first source / drain column 122 and the second source / drain column 124 are connected to the channel column (channel layer 112), electrons can be transferred along the channel column and stored in the entire charge storage structure 110, that is, a 1-bit operation can be performed on the memory cell 12. In addition, for operations using channel-hot-electron injection or band-to-band tunneling hot carrier injection, electrons or holes can be locally captured in the charge storage structure 110 adjacent to the first source / drain column 122 or adjacent to the second source / drain column 124. In this way, a 2-bit operation can be performed on the storage unit 12 .

[0094] It is particularly noted that the 3D flash memory of the present invention is not limited to the structure of the 3D flash memory 10, and other structures will be described below. In the following embodiments, the same elements as those in the first embodiment will be represented by the same element symbols and will not be described again.

[0095] Figure 4 FIG. 1 is a cross-sectional diagram of a three-dimensional flash memory according to a second embodiment of the present invention. The differences between this embodiment and the first embodiment are as follows. Figure 4 In the present embodiment, the three-dimensional flash memory 40 includes a gate stack structure composed of a gate layer 126, a ring-shaped channel column (channel layer 112), a first source / drain column 402, a second source / drain column 404, and a charge storage structure 110. The first source / drain column 402 and the second source / drain column 404 are, for example, doped polysilicon layers. The first source / drain column 402 includes a central portion 402a and a peripheral portion 402b surrounding the central portion 402a, and the doping concentration of the central portion 402a is greater than the doping concentration of the peripheral portion 404b. The second source / drain column 404 includes a central portion 404a and a peripheral portion 404b surrounding the central portion 404a, and the doping concentration of the central portion 404a is greater than the doping concentration of the peripheral portion 404b. This concentration difference can be used for electrical adjustment of the junction.

[0096] Figure 5 FIG. 1 is a cross-sectional diagram of a three-dimensional flash memory according to a third embodiment of the present invention. The differences between this embodiment and the first embodiment are as follows. Figure 5In this embodiment, the three-dimensional flash memory 50 includes a gate stack structure composed of a gate layer 126, a ring-shaped channel column (channel layer 112), a first source / drain column 502, a second source / drain column 504, and a charge storage structure 110. The first source / drain column 502 includes a central portion 502a and a peripheral portion 502b surrounding the central portion 502a. The second source / drain column 504 includes a central portion 504a and a peripheral portion 504b surrounding the central portion 504a. The peripheral portion 502b and the peripheral portion 504b are, for example, doped polysilicon layers. The central portion 502a and the central portion 504a are, for example, metal silicide layers, and the material thereof may be titanium silicide (TiSi x ), cobalt silicide (CoSi x ), nickel silicide (NiSi x ) or tungsten silicide (WSi x As a result, the first source / drain column 502 and the second source / drain column 504 can have a lower resistance value, which is beneficial to the performance of the three-dimensional flash memory.

[0097] Figure 6 FIG. 4 is a cross-sectional diagram of a three-dimensional flash memory according to a fourth embodiment of the present invention. The differences between this embodiment and the first embodiment are as follows. Figure 6 In this embodiment, the three-dimensional flash memory 60 includes a gate stack structure composed of a gate layer 126, a ring-shaped channel column (channel layer 112), a first source / drain column 502, a second source / drain column 504, a charge storage structure 110, a first buried column 602, and a second buried column 604. The first buried column 602 and the second buried column 604 are disposed in the dielectric substrate 100 and do not penetrate the dielectric substrate 100. The first buried column 602 is connected to the first source / drain column 122, and is, for example, aligned with the position of the first source / drain column 122, that is, the width of the first buried column 602 is, for example, the same as that of the first source / drain column 122. The second buried column 604 is connected to the second source / drain column 124, and is, for example, aligned with the position of the second source / drain column 124, that is, the width of the second buried column 604 is, for example, the same as that of the second source / drain column 124. The first buried pillar 602 and the second buried pillar 604 are, for example, polysilicon layers.

[0098] In this embodiment, before forming the stacked structure 102 on the dielectric substrate 100, the first buried pillar 602 and the second buried pillar 604 are first formed in the dielectric substrate 100. Figure 1C and Figure 2CIn the above steps, when the anisotropic etching process is used to form the openings 118 and 120, the first buried pillar 602 and the second buried pillar 604 can be used as an etching stop layer to avoid over-etching. In addition, when forming the first buried pillar 602 and the second buried pillar 604, the same mask as that used to form the openings 118 and 120 can be used, thereby not causing an increase in manufacturing costs.

[0099] Figure 7 FIG. 5 is a cross-sectional diagram of a three-dimensional flash memory according to a fifth embodiment of the present invention. The differences between this embodiment and the first embodiment are as follows. Figure 7 In this embodiment, the three-dimensional flash memory 70 includes a gate stack structure composed of a gate layer 126, a ring-shaped channel column (channel layer 112), a first source / drain column 122, a second source / drain column 124, and a charge storage structure 110. In addition, the channel column (channel layer 112) is discontinuous in its extension direction, and the channel column only corresponds to the position of each gate layer 126. "The channel layer 112 is discontinuous in its extension direction" means that the channel layer 112 is not a whole in its extension direction, but is divided into multiple unconnected parts.

[0100] Specifically, in this embodiment, Figure 1A and Figure 2A After the opening 108 is formed, an etch-back process is performed to remove a portion of the sacrificial layer 106 so that the sidewall of the sacrificial layer 106 is not flush with the sidewall of the insulating layer 104, that is, a channel is formed between adjacent insulating layers 104. Figure 1B and Figure 2B In the steps described above, a charge storage structure 110 is formed. At this time, the charge storage structure 110 is formed on the sidewalls of the channel in addition to being formed on the inner surface of the opening 108. Next, a channel layer 112 is formed on the charge storage structure 110, and the channel layer 112 fills the channel. Afterwards, an etching process is performed to remove the channel layer 112 outside the channel. In this way, the channel layer 112 is disposed in the channel between adjacent insulating layers 104. In other words, the formed channel column includes a plurality of parts (channel column segment 112a, channel column segment 112b, channel column segment 112c), each of which is located in the channel between adjacent insulating layers 104 and corresponds to the position of a gate layer 126. In other words, the channel column segment 112a, the channel column segment 112b, and the channel column segment 112c are arranged in sequence in the extension direction of the channel column 112 and do not contact each other. Therefore, in this embodiment, the channel column can be regarded as discontinuous in its extension direction.

[0101] Figure 8 FIG. 6 is a cross-sectional diagram of a three-dimensional flash memory according to a sixth embodiment of the present invention. The differences between this embodiment and the first embodiment are as follows. Figure 8 In this embodiment, the three-dimensional flash memory 80 includes a gate stack structure composed of a gate layer 126, a ring-shaped channel column (channel layer 112), a first source / drain column 122, a second source / drain column 124, a charge storage structure 110, a first transistor 802, and a second transistor 804. The first transistor 802 is electrically connected to the first source / drain column 122, and the second transistor 804 is electrically connected to the second source / drain column 124. In this embodiment, the first transistor 802 and the second transistor 804 are arranged above the topmost storage unit 12, and the first transistor 802 is connected to the first source / drain column 122, and the second transistor 804 is connected to the second source / drain column 124. The first transistor 802 and the second transistor 804 each include a transistor gate layer 808, a gate insulation layer 812, a transistor channel column 814, and a doping region 816

[0102] In detail, in this embodiment, when forming Figure 1E and Figure 2E After the structure is formed, an insulating layer 806, a transistor gate layer 808 and an insulating layer 810 are sequentially formed on the top insulating layer 104. The insulating layer 806 and the transistor gate layer 808 are, for example, silicon oxide layers. The transistor gate layer 808 is, for example, a doped polysilicon layer. Then, openings are formed in the insulating layer 806, the transistor gate layer 808 and the insulating layer 810 to expose the first source / drain column 122 and the second source / drain column 124. Next, a gate insulating layer 812 is formed on the inner surface of the opening. The gate insulating layer 812 is, for example, a silicon oxide layer. Then, the opening is filled with a transistor channel column 814. The transistor channel column 814 is, for example, an undoped polysilicon layer. Then, a doped region 816 is formed at the top of the transistor channel column 814 to serve as the source / drain of the first transistor 802 and the second transistor 804.

[0103] In this embodiment, through the first transistor 802 connected to the first source / drain column 122 and the second transistor 802 connected to the second source / drain column 124, better control of the three-dimensional flash memory of this embodiment can be achieved, especially for a three-dimensional flash memory with a more stacked layer structure, each storage unit can be controlled more accurately.

[0104] In addition, for the array layout of the three-dimensional flash memory of the embodiment of the present invention, since transistors are arranged above the three-dimensional flash memory, and these transistors are respectively connected to the first source / drain column 122 or the second source / drain column 124 of the three-dimensional flash memory, Figure 3 The plurality of circuit patterns and the plurality of conductive lines arranged in parallel and not in contact with each other are disposed above the transistors. Figure 3The circuit pattern 300 in FIG. 1 includes a first portion 302 and a second portion 304 ) is disposed on these transistors and each is connected to the doping region 816 of the transistor (for example, the first portion 302 is connected to the doping region 816 ). Figure 3 As described above, these circuit patterns can be electrically connected to the conductive lines (eg, the conductive lines 306 ) through contact windows disposed thereon (eg, disposed on the second portion 304 ).

[0105] In the second to sixth embodiments described above, the charge storage structure 110 is formed on the inner surface of the opening 108 after forming the opening 108 and before forming the channel layer 112, but the present invention is not limited thereto. In other embodiments, the charge storage structure 110 may also be formed after removing the sacrificial layer 106 and before forming the gate layer 126. This will be described below.

[0106] Fig. 9 FIG. 7 is a cross-sectional diagram of a three-dimensional flash memory according to a seventh embodiment of the present invention. The differences between this embodiment and the first embodiment are as follows. Fig. 9 In this embodiment, the three-dimensional flash memory 90 includes a gate stack structure consisting of a gate layer 126, a ring-shaped channel column (channel layer 112), a first source / drain column 122, a second source / drain column 124, and a charge storage structure 902. In addition to being located between the gate layer 126 and the channel column (channel layer 112), the charge storage structure 902 also covers the upper surface and the lower surface of the gate layer 126, that is, it is located between the gate layer 126 and the insulating layer 104.

[0107] Specifically, in this embodiment, Figure 1A and Figure 2A After the opening 108 is formed, the charge storage structure 110 is not formed on the inner surface of the opening 108, but the channel layer 112 is formed on the inner surface of the opening 108. Figure 1E and Figure 2E After the sacrificial layer 106 is removed, before the gate layer 126 is formed, the charge storage structure 902 is conformally formed on the sidewall and bottom of the channel between the adjacent insulating layers 104. Afterwards, the gate layer 126 is formed to fill the channel. In this way, the charge storage structure 902 is disposed between the gate layer 126 and the channel pillar (channel layer 112), and covers the upper surface and the lower surface of the gate layer 126.

[0108] In the first to seventh embodiments described above, various structures of the three-dimensional flash memory of the present invention are described, but the present invention is not limited thereto. In other embodiments, the structure of the three-dimensional flash memory can also be achieved by combining two or more of the first to seventh embodiments described above.

[0109] In addition, when a more-layered memory cell stack structure is required for high integration and high area utilization, multiple three-dimensional flash memory stacks of the present invention can be formed on a substrate. Figure 1E and Figure 2E After the three-dimensional flash memory 10 shown, the manufacturing steps of the three-dimensional flash memory 10 can be repeated once or multiple times to stack another or more three-dimensional flash memories 10 on the three-dimensional flash memory 10. In this way, the process complexity of the multi-layer three-dimensional flash memory can be effectively reduced. In this case, the connection between the upper three-dimensional flash memory and the lower three-dimensional flash memory can be achieved by contacting the source / drain column of the upper three-dimensional flash memory with the source / drain column of the lower three-dimensional flash memory (such as Fig.12 As shown in FIG. 1 ). Since the source / drain pillars in the three-dimensional flash memory of the present invention have larger sizes than other components, the three-dimensional flash memory of the upper layer and the three-dimensional flash memory of the lower layer can be easily aligned without the problem of mismatch, and the channel pillars of the three-dimensional flash memory of the upper layer and the channel pillars of the three-dimensional flash memory of the lower layer do not need to be completely aligned.

[0110] In summary, in the three-dimensional flash memory of the present invention, the annular channel column is disposed in the gate stack structure, and the two source / drain columns are disposed in the channel column and connected thereto. In this way, the three-dimensional flash memory of the present invention can generate a 1-bit operation or a 2-bit operation through different operation methods. In addition, the three-dimensional flash memory of the present invention can therefore have a high degree of integration and a high area utilization rate, and meet the requirements of a fast operation speed.

[0111] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-dimensional flash memory, comprising: A gate stack structure is disposed on a dielectric substrate and includes a plurality of gate layers electrically insulated from each other; An annular channel column is disposed on the dielectric substrate and penetrates the gate stack structure; A first source / drain column and a second source / drain column are disposed on the dielectric substrate and are located in the channel column and penetrate the gate stack structure, wherein the first source / drain column and the second source / drain column are separated from each other and are respectively connected to the channel column; as well as a charge storage structure disposed between each of the plurality of gate layers and the channel pillar; An insulating column is arranged between the first source / drain column and the second source / drain column; and an insulating layer is formed on a portion of the channel column where the source / drain column, the second source / drain column and the insulating column are not formed.

2. The three-dimensional flash memory according to claim 1, wherein the first source / drain column and the second source / drain column each include a central portion and a peripheral portion surrounding the central portion, and a doping concentration of the central portion is greater than a doping concentration of the peripheral portion. 3 . The three-dimensional flash memory according to claim 1 , wherein the first source / drain pillar and the second source / drain pillar each include a central portion and a peripheral portion surrounding the central portion, and the central portion includes a metal silicide layer.

4. The three-dimensional flash memory according to claim 1, further comprising a first buried pillar and a second buried pillar, which are disposed in the dielectric substrate, wherein the first buried pillar is connected to the first source / drain pillar, and the second buried pillar is connected to the second source / drain pillar. 5 . The three-dimensional flash memory according to claim 1 , wherein the charge storage structure covers an upper surface and a lower surface of each of the plurality of gate layers. 6 . The three-dimensional flash memory of claim 1 , wherein the charge storage structure covers an outer surface of the channel pillar. The three-dimensional flash memory according to claim 1 , wherein the channel pillar is continuous in its extension direction. 8 . The three-dimensional flash memory according to claim 1 , wherein the channel column is discontinuous in its extension direction, and the channel column only corresponds to the position of each of the plurality of gate layers.

9. The three-dimensional flash memory according to claim 8, wherein the channel column comprises a plurality of channel column segments, the plurality of channel column segments are arranged in sequence in the extension direction of the channel column and do not contact each other, and each of the plurality of channel column segments corresponds to a position of one of the plurality of gate layers. 10 . The three-dimensional flash memory according to claim 1 , further comprising a first transistor and a second transistor, wherein the first transistor is electrically connected to the first source / drain column, and the second transistor is electrically connected to the second source / drain column.

11. The three-dimensional flash memory according to claim 10, wherein the first transistor and the second transistor are composed of a transistor gate layer, a first transistor channel column, a second transistor channel column, a first gate insulating layer and a second gate insulating layer, wherein: The transistor gate layer is stacked on the gate stack structure and is electrically insulated from the gate stack structure. The first transistor channel column penetrates the transistor gate layer and is connected to the first source / drain column. The second transistor channel column penetrates the transistor gate layer and is connected to the second source / drain column. The first gate insulating layer is disposed between the first transistor channel column and the transistor gate layer. The second gate insulating layer is disposed between the second transistor channel column and the transistor gate layer. The first transistor channel column has a first doped region at one end thereof opposite to the first source / drain column, and An end of the second transistor channel column opposite to the second source / drain column has a second doped region. 12 . The three-dimensional flash memory of claim 1 , wherein charges are locally trapped in the charge storage structure adjacent to the first source / drain pillar and / or adjacent to the second source / drain pillar.

13. The three-dimensional flash memory according to claim 1, wherein a plurality of the three-dimensional flash memories are stacked on top of each other, and the first source / drain column of the three-dimensional flash memory in the upper layer is connected to the first source / drain column of the three-dimensional flash memory in the lower layer, and the second source / drain column of the three-dimensional flash memory in the upper layer is connected to the second source / drain column of the three-dimensional flash memory in the lower layer.

14. The three-dimensional flash memory according to claim 1, wherein parallel channels are provided at opposite sides of the gate stack structure, and from a top view, a connection line between the first source / drain column and the second source / drain column is parallel or perpendicular to an extension direction of the channel.

15. The three-dimensional flash memory according to claim 1, wherein parallel channels are provided at opposite sides of the gate stack structure, and when viewed from a top view, an acute angle is formed between a connection line between the first source / drain column and the second source / drain column and an extension direction of the channel.

16. The three-dimensional flash memory according to claim 1 further includes a conductive layer, which is arranged on the dielectric substrate and adjacent to at least one side wall of the gate stack structure, wherein the conductive layer extends along the at least one side wall of the gate stack structure, and the two opposite end portions of the conductive layer in its extension direction each have an electrical connection point.

17. A three-dimensional flash memory array layout structure, comprising: A plurality of three-dimensional flash memories according to claim 1 are arranged in an array on the dielectric substrate; A plurality of circuit patterns, each of which is electrically connected to one of the first source / drain columns and the second source / drain columns of the plurality of three-dimensional flash memories; as well as A plurality of conductive lines are electrically connected to corresponding ones of the plurality of circuit patterns through contact windows, respectively, wherein the plurality of conductive lines are arranged in parallel with each other.

18. The three-dimensional flash memory array layout structure according to claim 17, wherein each of the plurality of line patterns comprises: a first portion extending along a column direction of the array, and the first portion is connected to one of the first source / drain column and the second source / drain column; as well as a second portion extending along a row direction of the array, The contact window is disposed on the second portion, and the plurality of conductive lines extend along the row direction.

19. The three-dimensional flash memory array layout structure according to claim 17, wherein the plurality of conductive lines comprise source lines or bit lines.

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