A control switch of a driving circuit, an array substrate and a display panel

Abstract

The present application discloses a control switch, an array substrate and a display panel of a driving circuit, wherein the control switch includes a thin film transistor, the driving circuit also includes a source lead connected to the thin film transistor, the thin film transistor includes a source, a drain and a gate, the source includes at least two source branches arranged in parallel, and a source trunk connecting the source branches; the drain is arranged in the same layer as the source, including at least one drain branch, the drain branch is arranged between adjacent source branches, and the gate is arranged corresponding to the source and the drain; the source lead is connected to the source, and the extension line of the source lead does not overlap with the drain branch. The driving circuit in this case will not cause a short circuit between the source and the drain even when etching is uneven, which is beneficial to improving the production yield of the product.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a control switch of a driving circuit, an array substrate and a display panel. Background Art

[0002] At present, display technology is widely used in the display of televisions, mobile phones and public information. The display panels used to display pictures are also diverse and can display colorful pictures. More and more display panels, such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Organic Light Emitting Diode (OLED), need to use the Gate Driver on Array (GOA) technology to integrate the gate driver circuit on the array substrate in the display panel to form a scanning drive for the display panel, thereby reducing the product cost in terms of material cost and manufacturing process.

[0003] Usually, when making a GOA circuit, the source, drain and source lead in the thin film transistor are arranged in the same layer and etched at the same time, but the problem of uneven etching is prone to occur during the etching process; and as the integration of the GOA circuit becomes higher and higher, the channel spacing between the source and the drain becomes smaller and smaller. Therefore, when the etching is uneven, it is easy to cause the source lead to be connected to the source and the drain at the same time, causing a short circuit between the source and the drain. Summary of the invention

[0004] The purpose of the present application is to provide a control switch of a driving circuit, an array substrate and a display panel to prevent the driving circuit from causing a short circuit between the source and the drain when etching is uneven.

[0005] The present application discloses a control switch of a driving circuit, the control switch includes a thin film transistor, the driving circuit also includes a source lead connected to the thin film transistor, the thin film transistor includes a source, a drain and a gate, the source includes at least two source branches arranged in parallel, and a source trunk connecting the source branches; the drain is arranged in the same layer as the source, includes at least one drain branch, and a drain trunk connecting the drain branches, the drain branches are arranged in parallel with the source branches and alternately to form a channel; the gate is arranged corresponding to the source and the drain, the source lead is connected to the source, and the extension line of the source lead does not overlap with the drain branch.

[0006] Optionally, the source lead is arranged on a side of the source trunk away from the source branch, connected to the source trunk, and an extension line of the source lead is parallel to the drain branch.

[0007] Optionally, the source branches connected to the two ends of the source trunk are a first source branch and a second source branch, and at least one source lead is provided, and is provided corresponding to at least one of the first source branch and the second source branch.

[0008] Optionally, the source branches connected to the two ends of the source trunk are the first source branch and the second source branch, and the source branches connected to the area between the two ends of the source trunk are the third source branch, and the third source branch is arranged in parallel between the first source branch and the second source branch; at least one source lead is provided, and is arranged corresponding to at least one of the first source branch, the second source branch and the third source branch.

[0009] Optionally, the width of the source lead is smaller than the distance between two adjacent drain branches.

[0010] Optionally, among the source branches, a first source branch and a second source branch are connected to both ends of the source trunk; the thin film transistor also includes an extension portion, the extension portion is connected to the source lead, and the extension portion is connected to the end of the first source branch and / or the second source branch away from the source trunk; in a first direction, the first source branch and / or the second source branch connected to the extension portion protrudes from other source branches, and the end of the source lead connected to the extension portion protrudes from one side of the drain trunk away from the source; wherein the first direction is the extension direction of the source branch.

[0011] Optionally, among the source branches, the one connected to the region between the two ends of the source trunk is a third source branch, and the third source branch is arranged in parallel between the first source branch and the second source branch; among the drain branches, the one connected to the two ends of the drain trunk is a first drain branch and a second drain branch, and the one connected to the region between the two ends of the drain trunk is a third drain branch, and the third drain branch is arranged in parallel between the first drain branch and the second drain branch;

[0012] The first drain branch is arranged in parallel between two adjacent first source branches and the third source branch, the second drain branch is arranged in parallel between two adjacent second source branches and the third source branch, and the third drain branch is arranged in parallel between two adjacent third source branches; the number of the third drain branches is one less than the number of the third source branches.

[0013] Optionally, the driving circuit includes a frame start signal line, a gate voltage control line, a clock signal line and a plurality of GOA units, the input end of each of the GOA units is connected to the frame start signal line, the gate voltage control line and the clock signal line, and the output end of the GOA unit is connected to the scan line to drive the scan line;

[0014] The GOA unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, the source of the first thin film transistor is connected to the gate voltage control line and the source of the second thin film transistor through the two source leads, the drain of the first thin film transistor is connected to the source of the third thin film transistor and the gate of the fourth thin film transistor, and the gate of the first thin film transistor is connected to the gate of the second thin film transistor;

[0015] The drain of the second thin film transistor is connected to the source of the fourth thin film transistor, and the gate of the second thin film transistor is connected to the gate of the fourth thin film transistor; the drain of the third thin film transistor is connected to the frame start signal line, and the drain of the fourth thin film transistor is connected to the clock signal line.

[0016] The present application also discloses an array substrate, comprising the driving circuit as described above, and a scanning line driven by the driving circuit.

[0017] The present application also discloses a display panel, comprising the array substrate as described above, a color filter substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color filter substrate.

[0018] Compared with the current solution of directly connecting the source lead vertically to the source branch in the thin film transistor, the present application changes the connection position of the source lead and the source so that when the metal layer where the source, drain and source leads are located is unevenly etched, even if the end of the source lead is not etched cleanly, so that the end of the source lead protrudes from the source branch or the source trunk, the extension line of the source lead does not overlap with the drain branch, so the end of the source lead will not intersect with the drain branch; therefore, the use of the driving circuit in this case will not cause a short circuit between the source and the drain even when the etching is uneven, which is beneficial to improving the production yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0020] Figure 1 is a planar schematic diagram of an array substrate;

[0021] Figure 2 yes Figure 1 A partial enlarged view of the middle M position;

[0022] Figure 3 is an exemplary partial schematic diagram of GOA;

[0023] Figure 4 is another exemplary partial schematic diagram of GOA;

[0024] Figure 5 is based on Figure 3 Schematic diagram under ideal conditions;

[0025] Figure 6 is based on Figure 4 Schematic diagram under ideal conditions;

[0026] Figure 7 is a partial schematic diagram of a driving circuit provided in the first embodiment of the present application;

[0027] Figure 8 is a partial schematic diagram of another driving circuit provided in the first embodiment of the present application;

[0028] Fig. 9 is a partial schematic diagram of a driving circuit including another type of thin film transistor provided in the first embodiment of the present application;

[0029] Fig.10 is a partial schematic diagram of a driving circuit including another type of thin film transistor provided in the first embodiment of the present application;

[0030] Fig.11 is a partial schematic diagram of a driving circuit provided in the second embodiment of the present application;

[0031] Fig.12 is a partial schematic diagram of another driving circuit provided in the second embodiment of the present application;

[0032] Fig.13 is a partial schematic diagram of a driving circuit provided in the third embodiment of the present application;

[0033] Fig.14 is a schematic diagram of a display panel provided in one embodiment of the present application.

[0034] Among them, 100, array substrate; 200, driving circuit; 201, first thin film transistor; 202, second thin film transistor; 203, third thin film transistor; 204, fourth thin film transistor; 210, source lead; 220, thin film transistor; 230, source; 231, source branch; 232, first source branch; 233, second source branch; 234, third source branch; 235, source trunk; 240, drain; 241, drain branch; 242, first drain branch; 243, second drain branch; 244, third drain branch; 245, drain trunk; 250, extension; 260, gate; 300, scan line; 400, display panel; 500, color film substrate; 600, liquid crystal layer. DETAILED DESCRIPTION

[0035] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0036] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, features defined as "first" and "second" may explicitly or implicitly include one or more of the features; "plurality" means two or more. The term "including" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may exist or be added.

[0037] In addition, terms indicating orientation or positional relationships, such as “center,” “lateral,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are described based on the orientation or relative positional relationships shown in the accompanying drawings and are merely simplified descriptions for the convenience of describing the present application. They do not indicate that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limitations on the present application.

[0038] In addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internally connected between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0039] The present application is described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, under the premise of no conflict, the embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0040] like Figure 1 and Figure 2 As shown, it is a planar schematic diagram of an array substrate, wherein a scan line 300 is provided in the display area of ​​the array substrate 100, and a drive circuit 200 is provided in the non-display area of ​​the array substrate 100, which can be specifically an array substrate row drive circuit, wherein the drive circuit 200 contains a frame start signal line (STV), a gate voltage control line (VGL), a clock signal line (CKV) and a plurality of GOA units, wherein the input end of the GOA unit is connected to STV, VGL and CKV, and the output end is connected to the scan line 300 to drive the scan line 300; wherein the gate voltage control line is connected to a thin film transistor 220 in the GOA unit through a source lead 210 to charge the thin film transistor 220.

[0041] Specifically, the GOA unit includes a first thin film transistor 201, a second thin film transistor 202, a third thin film transistor 203 and a fourth thin film transistor 204, the source 230 of the first thin film transistor 201 is connected to the gate voltage control line and the source 230 of the second thin film transistor 202 through the two source leads 210, the drain 240 of the first thin film transistor 201 is connected to the source 230 of the third thin film transistor 203 and the gate 260 of the fourth thin film transistor 204, respectively, the gate 260 of the first thin film transistor 201 is connected to the gate 260 of the second thin film transistor 202; the drain 240 of the second thin film transistor 202 is connected to the source 230 of the fourth thin film transistor 204, the gate 260 of the second thin film transistor 202 is connected to the gate 260 of the fourth thin film transistor 204; the drain 240 of the third thin film transistor 203 is connected to the frame start signal line, and the drain 240 of the fourth thin film transistor 204 is connected to the clock signal line.

[0042] exist Figure 2The GOA unit shown in the figure contains four interconnected thin film transistors and other wirings. It can be seen from the figure that there are three blank areas, namely area A, area B and area C; between area B and area C, two thin film transistors 220 are connected through the source lead 210. Before etching the metal layer into the source 230, the drain 240 and other metal line patterns, it is necessary to form an etching barrier layer on the source 230, the drain 240 and other metal line patterns, and then use a developer to form a barrier layer pattern. Since the area of ​​area B and area C is large, more developer is consumed, so that the development energy consumed by area D and area E becomes less, and then the barrier layer corresponding to area D and area E is not easy to etch completely. Finally, the problem of uneven etching occurs when etching the metal layer pattern, resulting in a short circuit between the source 230 and the drain 240 corresponding to area D and area E.

[0043] like Figure 3 and Figure 4 As shown, two exemplary partial schematic diagrams of GOA are shown. When the metal patterns corresponding to regions D and E are not etched uniformly, Figure 3 and Figure 4 The middle source lead 210 may extend into the channel of the source 230 of the thin film transistor 220 , or even be connected to the drain 240 , resulting in a short circuit between the source and drain 240 .

[0044] Figure 5 and Figure 6 Under ideal conditions, based on Figure 3 and Figure 4 However, this requires more developer to ensure that the barrier layers corresponding to regions D and E are completely etched, so that when the metal pattern is subsequently etched, the source lead 210 will not protrude from the source 230 and extend into the source 230 channel.

[0045] In view of this, the present application provides a control switch of a driving circuit 200 that does not cause a short circuit between a source 230 and a drain 240 when etching is uneven. The control switch includes a thin film transistor 220, Figure 1 , Figure 2 ,as well as Figure 7-Figure 13As shown, the thin film transistor 220 in the driving circuit 200 includes a source 230, a drain 240 and a gate 260, wherein the source 230 includes at least two source branches 231 arranged in parallel, and a source trunk 235 connecting the source branches 231; the drain 240 is arranged in the same layer as the source 230, including at least one drain branch 241, and a drain trunk 245 connecting the drain branches 241, wherein the drain branches 241 are arranged in parallel with the source branches 231 and are arranged alternately to form a channel; the gate 260 is arranged corresponding to the source 230 and the drain 240; wherein the source lead 210 is connected to the source 230, and the extension line of the source lead 210 does not overlap with the drain branch 231.

[0046] It should be noted that the source lead 210 may be connected only to the source branch 231, only to the source trunk 235, or simultaneously to the source branch 231 and the source trunk 235. When there is only one drain branch 241, the drain trunk 245 is a part of the drain branch 241 and is connected to other structures in the driving circuit 200. The extension line of the source lead 210 does not overlap with the drain branch 241, and further, the source lead 210 does not overlap with the drain trunk 245 or even the entire drain 240.

[0047] The present application changes the connection position between the source lead 210 and the source branch 231 so that the extension line of the source lead 210 does not overlap with the drain 240. At this time, the source lead 210 is located in the area B or the area C, thereby reducing the space of the area B or the area C, so that the developer consumed in the area B or the area C is reduced, resulting in more development energy for the area D and the area E, ensuring that the barrier layer corresponding to the area D and the area E is completely etched, thereby improving the problem of uneven etching of the metal layer pattern, so that the source lead 210 does not protrude from the source 230 and extends to the source 23 0 channel; and even if the problem of uneven etching occurs, the end of the source lead 210 is not etched cleanly when etching the source lead 210, so that the end of the source lead 210 protrudes from the source branch 231, but because the extension line of the source lead 210 does not overlap with the drain branch 241, the end of the source lead 210 still does not intersect with the drain branch 241; in summary, the use of the driving circuit 200 in this case will not cause the source 230 and the drain 240 to short-circuit even when etching is uneven, which is conducive to improving the production yield of the product.

[0048] Specifically, the present application provides the following multiple embodiments to achieve that the extension line of the source lead 210 does not overlap with the drain 240, so as to prevent the source 230 and the drain 240 from short-circuiting when the engraving is uneven. Figure 7-10As shown, the source lead is arranged on the side of the source trunk away from the source branch, connected to the source trunk, and the extension line of the source lead is parallel to the drain branch; the source lead overlaps or even coincides with at least one source branch. Figure 11-13 As shown, the source lead is perpendicular to the extension line of the source branch, and the extension line of the source line does not overlap with the drain.

[0049] like Figure 7 As shown, it is a partial schematic diagram of a driving circuit 200. As an embodiment of the present application, a control switch of the driving circuit 200 is disclosed. The control switch includes a thin film transistor 220. The driving circuit also includes a source lead 210 connected to the thin film transistor 220. The thin film transistor 220 includes a source 230 and a drain 240. The source 230 includes a first source branch 232 and a second source branch 233 arranged in parallel, and a first source branch 232 and a second source branch 233 are connected. The source trunk 235, at this time, the first source branch 232, the source trunk 235 and the second source branch 233 form a U-shaped pattern; the drain 240 includes a first drain branch 242, and the first drain branch 242 is arranged between the first source branch 232 and the second source branch 233; the source lead 210 is connected to the end of the first source branch 232, and the source lead 210 and the source branch 231 are located on the same straight line, so that the source lead 210 is also connected to the source trunk 235. In this embodiment, there is no need to change the structure of the existing thin film transistor 220, only the connection position of the source lead 210 to the first source branch 232 needs to be changed; moreover, when the first source branch 232 or the second source branch 233 is vertically connected to the source trunk 235, the source lead 210 is vertically connected to the source trunk, and then connected to the first source branch 232, thereby increasing the contact area between the source branch 231 and the thin film transistor 220, and improving the charging effect of the source lead 210 on the thin film transistor 220.

[0050] Of course, if Figure 8 As shown, the source lead 210 can also be connected to the second source branch 233, or two source leads 210 are provided in the driving circuit 200, one source lead 210 connects the VGL line to the thin film transistor 220, and the other source lead 210 connects the two thin film transistors 220, that is, one thin film transistor is connected to two source leads 210, which is specifically designed according to the usage, and Figure 2 At this time, the design of the source lead 210 is also as described above, and a portion of the source lead 210 is in the same straight line as the source branch 231.

[0051] like Fig. 9 and Fig.10 , there are two schematic diagrams of driving circuits 200 containing thin film transistors 220 of different types. Fig. 9 In the source branch 231, the first source branch 232 and the second source branch 233 are connected to the two ends of the source trunk 235, and the third source branch 234 is connected to the area between the two ends of the source trunk 235. The third source branch 234 is arranged between the first source branch 232 and the second source branch 233, and is connected to the middle end of the source trunk 235. The source 230 is shaped as two parallel U-shaped structures; the drain 240 includes a first drain branch 242, a second drain branch 243 and a drain trunk 245. The first drain branch 242 and the second drain branch 243 are respectively connected to the two ends of the drain trunk 245, and the drain 240 is shaped as a U-shaped structure. The first drain branch 242 is located between the first source branch 232 and the third source branch 234, and the second drain branch 243 is located between the second source branch 233 and the third source branch 234; on the side away from the drain 240, the source lead 210 is connected to the third source branch 234 and is located on the same straight line as the third source branch 234. Of course, the source lead 210 can overlap with the extension direction of the first source branch 232, can overlap with the extension direction of the second source branch 233, or the two source leads 210 can be connected to two of the first source branch 232, the second source branch 233 and the third source branch 234 respectively.

[0052] Fig.10 In the source branch 231, the first source branch 232 and the second source branch 233 are connected to the two ends of the source trunk 235, and the third source branch 234 is connected to the area between the two ends of the source trunk 235. The third source branch 234 is arranged in parallel between the first source branch 232 and the second source branch 233. The source 230 is shaped as a plurality of U-shaped structures connected in parallel; the drain 240 includes a first drain branch 242, a second drain branch 243, a drain trunk 245 and at least one third drain branch 244. The first drain branch 242 and the second drain branch 243 are respectively connected to the two ends of the drain trunk 245. The third drain branch 244 is arranged in parallel between the first drain branch 242 and the second drain branch 243, and is connected to the drain trunk 245. The drain 240 is also shaped as a plurality of U-shaped structures connected in parallel.

[0053] The first drain branch 242 is located between the first source branch 232 and the third source branch 234, the second drain branch 243 is located between the second source branch 233 and the third source branch 234, and the third drain branch 244 is located between two adjacent third source branches 234. On the side away from the drain 240, the source lead 210 overlaps with the extension direction of the first source branch 232; of course, it can also overlap with the extension direction of the second source branch 233, can overlap with the extension direction of the third source branch 234, or the two source leads 210 can be connected to two of the first source branch 232, the second source branch 233 and the third source branch 234 respectively.

[0054] In this embodiment, all source branches 231 and drain branches 241 are strip structures, which may be rectangular, elliptical or other shapes. The extension direction of the source branch 231 is perpendicular to the extension direction of the source trunk 235, and the extension direction of the drain branch 241 is perpendicular to the extension direction of the drain trunk 245; of course, the angle between the extension direction of the source branch 231 and the extension direction of the source trunk 235 may form an acute angle, and the angle between the extension direction of the drain branch 241 and the extension direction of the drain trunk 245 is also an acute angle.

[0055] exist Figure 7-10 In the embodiment, the widths of the source branch 231 , the source trunk 235 , the drain branch 241 and the drain trunk 245 are all equal, and the channel widths between adjacent source branches 231 and drain branches 241 are also equal, thereby improving the conductive performance of the thin film transistor 220 .

[0056] In addition, in order to further prevent the source 230 and the drain 240 from short-circuiting, the width of the source lead 210 is also narrowed in the present embodiment, so that the width of the source lead 210 is smaller than the width of the source branch 231, so that when etching the blocking layer pattern, more developing energy can be gathered between the source branch 231 and the drain branch 241, so that the pattern can be completely etched in the subsequent metal pattern etching process; at the same time, since the width of the source lead 210 is narrow, the corresponding blocking layer pattern required when etching the source lead 210 is narrow, even when the developing energy is insufficient, the blocking layer pattern is not completely etched, resulting in the side of the source lead 210 becoming wider, and since there is a large gap between the source lead 210 and the drain branch 241, it is difficult for the source lead 210 to be connected to the drain 240, resulting in a short circuit between the source 230 and the drain 240.

[0057] Of course, the width of the source lead 210 can be equal to the width of the source branch 231, so that the source lead 210 and the extension line of the source branch 231 overlap, so that the conductive effect of the thin film transistor 220 is more uniform. At the same time, the width of the source lead 210 can also be made smaller than the spacing between the source branch 231 and the drain branch 241, so that when the source lead 210 is not overlapped with the source branch 231 due to uneven etching, when the source lead 210 and the extension line of the source branch 231 partially overlap, the source lead 210 will not be connected to the drain 240, so that the source 230 and the drain 240 are short-circuited.

[0058] like Fig.11 As shown, it is a partial schematic diagram of another driving circuit 200. As another embodiment of the present application, a control switch of another driving circuit 200 is also disclosed, the control switch includes a thin film transistor 220, the driving circuit also includes a source lead 210 connected to the thin film transistor 220, the thin film transistor 220 includes a source 230 and a drain 240, the source 230 includes a first source branch 232 and a second source branch 233 arranged in parallel, and a source trunk 235 connected to the first source branch 232 and the second source branch 233, the first source branch 232 and the second source branch 233 are respectively connected to the two ends of the source trunk 235; the drain 240 includes a first drain branch 242, and the first drain branch 242 is arranged in the channel between the first source branch 232 and the second source branch 233.

[0059] The thin film transistor 220 also includes an extension portion 250, which is connected to the end of the first source branch 232 away from the source trunk 235. In a first direction, the first source branch connected to the extension portion 250 protrudes from other source branches, and the end of the source lead connected to the extension portion protrudes from a side of the drain trunk away from the source; wherein the first direction is the extension direction of the source branch.

[0060] In this embodiment, after the first source branch 232 is extended toward the drain 240, the extended portion forms an extension portion 250, and the extension portion 250 protrudes from the drain 240, so that the source lead 210 is connected to the portion of the extension portion 250 protruding from the drain 240, and the extension line of the source 230 does not overlap with the drain 240. Therefore, it is not necessary to change the shape of the source lead 210, and only the position of the source lead 210 needs to be changed; in this embodiment, by also changing the source lead 210, when etching the source 230 and drain 240 patterns, more developing energy can be obtained near the first source branch 232, so that the corresponding barrier layer pattern is completely etched, so that the channel between the first source branch 232 and the first drain branch 242 is completely etched in the subsequent etching process. Moreover, even if the end of the source lead 210 is not etched cleanly when etching the source lead 210, so that the end of the source lead 210 protrudes from the first source branch 232, since the extension line of the source lead 210 does not overlap with the drain 240, the end of the source lead 210 will not intersect with the drain 240; therefore, when the etching is uneven in this embodiment, it will not cause a short circuit between the source 230 and the drain 240, which is beneficial to improving the production yield of the product.

[0061] Of course, if Fig.12 As shown, an extension portion 250 can be provided on one end of the second source branch 233 facing the drain 240, and the source lead 210 is vertically connected to the extension portion 250. The specific design of the extension portion 250 refers to the extension portion 250 connected to the first source branch 232 mentioned above, and no further details are given here; or two source leads 210 are provided in the driving circuit 200. In this case, the first source branch 232 and the second source branch 233 are both provided with an extension portion 250, and the two source leads 210 are respectively connected to the first source branch 232 or the second source branch 233, and the specific design is carried out according to the usage.

[0062] Moreover, this embodiment is also applicable to other types of thin film transistors 220, including Fig. 9 A thin film transistor 220 having three source branches 231, and Fig.10 The thin film transistor 220 has more than three source branches 231, but the extension portion 250 is only connected to the first source branch 232 and / or the second source branch 233 at both ends of the source 230. The specific details are as follows Fig.11 It has been shown in the figure, and no further elaboration is given here.

[0063] like Fig.13As shown, another driving circuit 200 is disclosed, which is different from the previous embodiment in that the extension portion 250 is connected to the other end of the first source branch 232 and / or the second source branch 233, that is, the extension portion 250 is an extension of the drain branch 241 toward the comb handle of the drain 240; one end of the extension portion 250 is connected to the first source branch 232, and the other end is vertically connected to the extension line of the source trunk 235, and the source lead 210 coincides with the extension line of the source trunk 235. Specifically, since the shape of the source 230 is U-shaped, the connection between the first source branch 232 and the source trunk 235 is not a right angle. In this embodiment, the first source branch 232 and the source trunk 235 are extended together until they intersect. The portion between the intersection and the first source branch 232 is the extension portion 250, and the portion between the intersection and the source trunk 235 is a portion of the source lead 210. The source lead 210 is perpendicular to the extension portion 250 and passes through the extension portion 250 to overlap with the source trunk 235.

[0064] In this embodiment, the source lead 210 is arranged in the direction of the extension line of the source trunk 235, and the source lead 210 is connected to the first source branch 232 and the source trunk 235 at the same time, so as to improve the charging effect of the source lead 210 on the thin film transistor 220; in addition, even if the end of the source lead 210 is not etched cleanly when etching the source lead 210, so that the end of the source lead 210 protrudes from the extension portion 250, it will only protrude into the source trunk 235 and will not be connected to the drain 240, so the source 230 and the drain 240 will not be short-circuited.

[0065] As for the type of the thin film transistor 220 in this embodiment, the connection method of the source lead 210 and the extension portion 250 in other source branches 231 can also be combined with the above embodiments, which will not be described in detail here.

[0066] like Fig.14 FIG. 4 is a schematic diagram of a display panel. As another embodiment of the present application, a display panel 400 is also disclosed. The display panel 400 includes Figure 1 The array substrate 100 shown, the color filter substrate 500 disposed opposite to the array substrate 100, and the liquid crystal layer 600 disposed between the array substrate 100 and the color filter substrate 500, the non-display area of ​​the array substrate 100 contains the above-mentioned driving circuit 200. In addition, the thin film transistor 220 in the present application is not only applicable to the array substrate row driving circuit in the non-display area, but also applicable to the active switch in the display area of ​​the array substrate 100.

[0067] The technical solution of the present application can be widely used in various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels can also be applied to the above solution.

[0068] It should be noted that the inventive concept of the present application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effects will be enhanced.

[0069] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A control switch of a driving circuit, the control switch comprising a thin film transistor, the driving circuit further comprising a source lead connected to the thin film transistor, characterized in that: The thin film transistor comprises: A source electrode, comprising at least two source electrode branches arranged in parallel, and a source electrode trunk connecting the source electrode branches; and A drain electrode, arranged in the same layer as the source electrode, comprising at least one drain electrode branch and a drain electrode trunk connecting the drain electrode branches, wherein the drain electrode branches are arranged in parallel and alternately with the source electrode branches to form a channel; and A gate electrode, arranged corresponding to the source electrode and the drain electrode; Wherein, the source lead is connected to the source, and the extension line of the source lead does not overlap with the drain branch; Among the source branches, the first source branch and the second source branch are connected to both ends of the source trunk; The thin film transistor further comprises an extension portion, the extension portion is connected to the source lead, and the extension portion is connected to an end of the first source branch and / or the second source branch away from the source trunk; In the first direction, the first source branch and / or the second source branch connected to the extension portion protrudes beyond other source branches, and the end of the source lead connected to the extension portion protrudes from a side edge of the drain trunk away from the source; The first direction is an extending direction of the source branch.

2. The control switch of the drive circuit according to claim 1, characterized in that: Among the source branches, the third source branch is connected to the region between the two ends of the source trunk, and the third source branch is arranged in parallel between the first source branch and the second source branch; Among the drain branches, the first drain branch and the second drain branch are connected to the two ends of the drain trunk, and the third drain branch is connected to the area between the two ends of the drain trunk. The third drain branch is arranged in parallel between the first drain branch and the second drain branch; The first drain branch is arranged in parallel between two adjacent first source branches and the third source branch, the second drain branch is arranged in parallel between two adjacent second source branches and the third source branch, and the third drain branch is arranged in parallel between two adjacent third source branches; The number of the third drain branches is one less than the number of the third source branches.

3. The control switch of the driving circuit according to claim 1, characterized in that: The driving circuit includes a frame start signal line, a gate voltage control line, a clock signal line and a plurality of GOA units, the input end of each of the GOA units is connected to the frame start signal line, the gate voltage control line and the clock signal line, and the output end of the GOA unit is connected to the scan line to drive the scan line; The GOA unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, the source of the first thin film transistor is connected to the gate voltage control line and the source of the second thin film transistor through the two source leads, the drain of the first thin film transistor is connected to the source of the third thin film transistor and the gate of the fourth thin film transistor, and the gate of the first thin film transistor is connected to the gate of the second thin film transistor; The drain of the second thin film transistor is connected to the source of the fourth thin film transistor, and the gate of the second thin film transistor is connected to the gate of the fourth thin film transistor; The drain of the third thin film transistor is connected to the frame start signal line, and the drain of the fourth thin film transistor is connected to the clock signal line.

4. An array substrate, characterized in that: The invention comprises a control switch of the driving circuit as claimed in any one of claims 1 to 3, and a scanning line controlled by the control switch.

5. A display panel, characterized in that: It comprises the array substrate as claimed in claim 4, a color filter substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color filter substrate.

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