Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, wherein a bottom metal layer is formed in the substrate; forming a first interlayer dielectric layer and a second interlayer dielectric layer on the substrate in sequence; forming a first through hole in the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the bottom of the first through hole exposes the surface of the bottom metal layer; forming a first groove in the second interlayer dielectric layer, wherein the bottom of the first groove is connected to the top of the first through hole; forming a first conductive layer in the first through hole; forming a first metal interconnection layer in the first groove, wherein the first metal interconnection layer is also located on the first conductive layer. The method provided by the embodiment of the present invention is conducive to reducing the resistance of the formed interconnection structure and improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the key dimensions of components are constantly decreasing, and the circuit density inside the integrated circuit is increasing. This development makes it impossible for the wafer surface to provide enough area to make the required interconnection lines.

[0003] In order to meet the needs of interconnection lines after the key dimensions are reduced, the conduction between different metal layers or metal layers and substrates is currently achieved through interconnection structures. A via is an electrical connection between wiring structures. As the key dimensions of components continue to decrease, the pitch of vias has also been shrinking, and the resistance of vias has increased dramatically, which has a great impact on the performance of the back end of line (BEOL) circuit, and in severe cases, it will affect the normal operation of semiconductor devices.

[0004] The current process for forming interconnect structures easily leads to a degradation in the electrical performance of semiconductor structures. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce the resistance of the interconnection structure and help improve the electrical performance of the semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, a bottom metal layer is formed in the substrate; a first interlayer dielectric layer is located on the substrate; a second interlayer dielectric layer is located on the first interlayer dielectric layer; a first through hole is located in the first interlayer dielectric layer and in the second interlayer dielectric layer; a first groove is located in the second interlayer dielectric layer, and the bottom of the first groove is connected to the top of the first through hole; a first conductive layer is located in the first through hole; a first metal interconnection layer is located in the first groove, and the first metal interconnection layer is also located on the first conductive layer.

[0007] Optionally, a top surface of the first conductive layer is flush with or lower than a top of the first through hole.

[0008] Optionally, when the top surface of the first conductive layer is lower than the top of the first through hole, a portion of the first metal interconnection layer is located in the first through hole.

[0009] Optionally, the method further includes: a barrier layer, wherein the barrier layer is located on the bottom and side wall surfaces of the first through hole and the bottom and side wall surfaces of the first groove.

[0010] Optionally, the material of the barrier layer includes TiN, Ti, TaN, Ta, WC, Co or Ru.

[0011] Optionally, the material of the first conductive layer includes Co or Ru.

[0012] Optionally, the material of the first metal interconnection layer includes Cu or Ag or Au or Al.

[0013] Correspondingly, an embodiment of the present invention also provides a method for forming the above-mentioned semiconductor structure, including: providing a substrate, wherein a bottom metal layer is formed in the substrate; forming a first interlayer dielectric layer on the substrate; forming a second interlayer dielectric layer on the first interlayer dielectric layer; forming a first through hole in the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the bottom of the first through hole exposes the surface of the bottom metal layer; forming a first groove in the second interlayer dielectric layer, wherein the bottom of the first groove is connected to the top of the first through hole; forming a first conductive layer in the first through hole; forming a first metal interconnection layer in the first groove, wherein the first metal interconnection layer is also located on the first conductive layer.

[0014] Optionally, a top surface of the first conductive layer is flush with or lower than a top of the first through hole.

[0015] Optionally, when the top surface of the first conductive layer is lower than the top of the first through hole, the method further includes: forming a first metal interconnection layer in a portion of the first through hole.

[0016] Optionally, the step of forming a first conductive layer includes: filling a first conductive material layer in the first through hole and the first groove, wherein the first conductive material layer also covers the top surface of the second interlayer dielectric layer; planarizing the first conductive material layer so that the top surface of the first conductive material layer is flush with the top surface of the second interlayer dielectric layer; and etching back the first conductive material layer until the top surface of the first conductive material layer is flush with or lower than the top of the first through hole, thereby forming a first conductive layer.

[0017] Optionally, the step of forming the first metal interconnection layer includes: filling a first metal material layer in the first groove, the first metal material layer being located on the first conductive layer, and the first metal material layer also covering the top surface of the second interlayer dielectric layer; planarizing the first metal material layer until the top surface of the first metal material layer is flush with the top surface of the second interlayer dielectric layer to form a first metal interconnection layer.

[0018] Optionally, the steps of forming the first through hole and the first groove include: forming a first mask layer having a first groove pattern on the second interlayer dielectric layer; forming a second mask layer having a first through hole pattern on the first mask layer; using the second mask layer as a mask, etching the second interlayer dielectric layer and a portion of the first interlayer dielectric layer to form a portion of the first through hole; removing the second mask layer; using the first mask layer as a mask, etching the second interlayer dielectric layer and the first interlayer dielectric layer to form a first groove and a first through hole.

[0019] Optionally, before filling the first conductive material layer, the method further includes: forming a barrier layer on the bottom and side wall surfaces of the first through hole and the bottom and side wall surfaces of the first trench.

[0020] Optionally, the material of the barrier layer includes TiN, Ti, TaN, Ta, WC, Co or Ru.

[0021] Optionally, before filling the first metal material layer in the first trench, the method further includes: forming a seed layer on the bottom and sidewall surface of the first trench and the surface of the first conductive layer.

[0022] Optionally, the material of the first conductive layer includes Co or Ru.

[0023] Optionally, the material of the first metal interconnection layer includes Cu or Ag or Au or Al.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] Firstly, a first through hole is formed through the first interlayer dielectric layer and the second interlayer dielectric layer to directly connect the first metal interconnection layer and the bottom metal layer, thereby reducing the resistance of the interconnection structure; secondly, a first conductive layer is first formed in the first through hole, and the first through hole with a high aspect ratio is filled with a conductive material with good filling performance to avoid the generation of voids; then, on the basis of the first conductive layer, a first metal interconnection layer is formed in the first trench with a material with low resistivity and good anti-mobility, thereby further reducing the resistance of the interconnection structure and facilitating improving the electrical performance of the semiconductor structure.

[0026] The present invention provides a semiconductor structure, wherein a first through hole passes through a first interlayer dielectric layer and a second interlayer dielectric layer, and a first conductive layer located in the first through hole directly connects a bottom metal layer located in a bottom dielectric layer and a first metal interconnection layer located in the second interlayer dielectric layer, thereby reducing the resistance of an interconnection structure and improving the electrical performance of the semiconductor structure; and the first conductive layer is located in the first through hole, and the first metal interconnection layer is located in a first groove, and the first conductive layer with good filling performance is used to fill the first through hole with a high aspect ratio, and the first metal interconnection layer with lower resistance is used to fill the first groove, thereby reducing the resistance of the interconnection structure and avoiding defects such as filling voids, thereby being beneficial to the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram of a semiconductor structure in one embodiment;

[0028] Figures 2 to 12 It is a schematic structural diagram corresponding to each step of a semiconductor structure forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] As can be seen from the background art, the formation process of the interconnection structure in the prior art easily leads to the degradation of the performance of the semiconductor structure. The reasons for the degradation of the performance are now analyzed in combination with a semiconductor structure.

[0030] refer to Figure 1 , showing a schematic structural diagram of a semiconductor structure, the semiconductor structure comprising:

[0031] A first interconnect level (Mx) 11, the first interconnect level (Mx) 11 comprising: a substrate (not shown), a first dielectric layer 21 on the substrate, a first metal layer 31 in the first dielectric layer 21, and a first cover layer 41 on the first dielectric layer 21;

[0032] a second interconnect level (Mx+1) 12 located on the first interconnect level (Mx) 11, the second interconnect level comprising a second dielectric layer 22, a second interconnect structure 32 located in the second dielectric layer 22, and a second cover layer 42 located on the second dielectric layer 22;

[0033] The third interconnection level (Mx+2) 13 is located on the second interconnection level (Mx+1) 12 , and the third interconnection level includes a third dielectric layer 23 and a third interconnection structure 33 located in the third dielectric layer 23 .

[0034] In the above semiconductor structure, the second interconnect structure 32 includes a second metal layer 51 and a first conductive plug 61 connecting the second metal layer 51 and the first metal layer 31 , and the third interconnect structure 33 includes a third metal layer 52 and a second conductive plug 62 connecting the third metal layer 52 and the second metal layer 51 .

[0035] As the critical dimensions of components continue to decrease, the pitch of through holes has also been shrinking, and the resistance of through holes has increased, which has an adverse effect on the electrical properties of semiconductor devices. Therefore, in the through hole process, super vias that can pass through multiple dielectric layers have appeared. For example, the super via passes through the second dielectric layer 22 and the third dielectric layer 23, directly connecting the third metal layer 52 in the third interconnect level (Mx+2) 13 and the first metal layer 31 in the first interconnect level (Mx) 11, which can reduce the resistance of the interconnect structure.

[0036] Copper is usually used to form interconnect structures due to its low resistivity and good anti-mobility. However, super vias pass through multiple dielectric layers and have a high aspect ratio. When copper is deposited in the vias to form conductive plugs, voids are easily generated in the vias due to the filling performance of copper, which has an adverse effect on the resistance of the formed interconnect structure and further affects the performance of the semiconductor structure.

[0037] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a first through hole in a first interlayer dielectric layer and a second interlayer dielectric layer; forming a first groove connected to the first through hole in the second interlayer dielectric; forming a first conductive layer in the first through hole, wherein the top surface of the first conductive layer is flush with or lower than the top of the first through hole; and forming a first metal interconnection layer in the first groove, wherein the first metal interconnection layer is also located on the first conductive layer. Firstly, the first through hole passes through the first interlayer dielectric layer and the second interlayer dielectric layer, directly connecting the first metal interconnection layer and the bottom metal layer, which can reduce the resistance of the interconnection structure; secondly, the first conductive layer is first formed in the first through hole, and the first conductive layer adopts materials such as cobalt and ruthenium with good filling performance, and no voids are formed in the process of forming the first conductive layer, so as to avoid adverse effects on the performance of the semiconductor structure; then, on the basis of the first conductive layer, the first metal interconnection layer is filled in the first trench. Since the first through hole with a high aspect ratio has been filled, the first metal interconnection layer selects materials with low resistance and good anti-mobility such as copper, which further reduces the resistance of the interconnection structure and avoids the problem of voids when copper is selected to fill the first through hole with a high aspect ratio.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 2 to 12It is a schematic structural diagram corresponding to each step of a semiconductor structure forming process in one embodiment of the present invention.

[0040] refer to Figure 2 , providing a substrate 100, wherein a bottom metal layer 101 is formed in the substrate 100.

[0041] The substrate 100 provides a process operation basis for subsequent processes.

[0042] According to actual process conditions, a functional structure may be formed in the substrate 100 , for example, a semiconductor device such as a MOS field effect transistor may be formed in the substrate 100 , and an underlying interconnection mechanism or a resistance structure may also be formed.

[0043] In this embodiment, a bottom dielectric layer 110 is formed in the substrate 100 , and the bottom metal layer 101 is located in the bottom dielectric layer 110 .

[0044] The bottom dielectric layer 110 is used to insulate the bottom metal layers 101 from each other. In this embodiment, the bottom dielectric layer 110 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), thereby effectively reducing the parasitic capacitance between the bottom metal layers 101, thereby reducing the RC delay of the back end. In other embodiments, the material of the bottom dielectric layer can also be silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, aluminum nitride or aluminum oxide.

[0045] The material of the bottom dielectric layer 110 may be SiOH, SiOCH, or SiOC. In this embodiment, the material of the bottom dielectric layer 110 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing holes.

[0046] The bottom metal layer 101 is used to realize electrical connection with the interconnection structure to be formed, and can also be used to realize electrical connection with an external circuit. The material of the bottom metal layer 101 is a conductive material such as Cu, Al or W.

[0047] In this embodiment, the top surface of the bottom metal layer 101 is flush with the top surface of the substrate 100 ; in other embodiments, the top surface of the bottom metal layer 101 may also be higher than the top surface of the substrate 100 .

[0048] In one implementation, one bottom metal layer 101 is formed in the substrate 100. In another embodiment, a plurality of bottom metal layers 101 are formed in the substrate 100. In this embodiment, two bottom metal layers 101 are formed as an example for description, but the number is not limited to two.

[0049] In this embodiment, a first covering layer 120 is also formed on the surface of the bottom dielectric layer 110 and the bottom metal layer 101, and the through hole formed subsequently also penetrates the first covering layer 120. The first covering layer 120 subsequently acts as an etching barrier, and the etching rate of the first covering layer 120 in the subsequent etching process of etching the dielectric layer is relatively low, thereby acting as an etching stopper to prevent over-etching of the substrate 100 or the bottom metal layer 101. In addition, the etching rate of the bottom metal layer 101 in the subsequent etching process of etching the first covering layer 120 is relatively low, thereby further avoiding etching damage to the bottom metal layer 101.

[0050] The material of the first cover layer 120 is different from that of the underlying dielectric layer 110. The material of the first cover layer 120 includes silicon nitride, silicon oxynitride or silicon carbonitride. In this embodiment, the material of the first cover layer 120 is silicon carbonitride.

[0051] In this embodiment, the first covering layer 120 is formed by atomic layer deposition. In other embodiments, the first covering layer 120 may be formed by chemical vapor deposition or physical vapor deposition.

[0052] Continue to refer Figure 2 , a first interlayer dielectric layer 200 is formed on the substrate 100 , specifically, the first interlayer dielectric layer 200 is formed on the bottom dielectric layer 110 .

[0053] The first interlayer dielectric layer 200 is used to insulate the interconnect structures formed subsequently from each other.

[0054] In this embodiment, the material of the first interlayer dielectric layer 200 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing holes. The description of the material of the first interlayer dielectric layer 200 can refer to the corresponding description of the bottom dielectric layer 110 above, and this embodiment will not be repeated here.

[0055] In this embodiment, a second metal interconnection layer 210 is formed in the first interlayer dielectric layer 200 , and a second conductive layer 220 connecting the second metal interconnection layer 210 and the bottom metal layer 101 is formed.

[0056] In other embodiments, the second metal interconnection layer may not be formed in the first interlayer dielectric layer 200 , which may be determined according to actual design requirements and is not limited in the present invention.

[0057] In this embodiment, the steps of forming the second metal interconnect layer 210 and the second conductive layer 220 include:

[0058] The first interlayer dielectric layer 200 and the first cover layer 120 are etched by a dual damascene process to form a second opening (not labeled), wherein the second opening includes a second trench (not labeled) and a second through hole (not labeled) intersecting each other, the bottom of the second trench is connected to the top of the second through hole, and the width of the bottom of the second trench is greater than the width of the top of the second through hole;

[0059] Forming a barrier layer 201 on the bottom and sidewall surface of the second opening;

[0060] Filling the second opening with a conductive material, wherein the conductive material also covers the top surface of the first interlayer dielectric layer 200;

[0061] The conductive material is subjected to chemical mechanical polishing to make the top surface of the conductive material flush with the top surface of the first interlayer dielectric layer 200, a second conductive layer 220 is formed in the second through hole, and a second metal interconnection layer 210 is formed in the second trench.

[0062] In this embodiment, the second metal interconnection layer 210 and the second conductive layer 220 are formed simultaneously and are made of the same material.

[0063] In this embodiment, after the second metal interconnection layer 210 and the second conductive layer 220 are formed, a second capping layer 230 is further formed on the first interlayer dielectric layer 200 and the second metal interconnection layer 210 .

[0064] In this embodiment, the material of the second covering layer 230 is silicon carbonitride. The material, function and formation method of the second covering layer 230 can refer to the first covering layer 120 formed on the bottom dielectric layer 110, and will not be repeated here.

[0065] refer to Figure 3 , a second interlayer dielectric layer 300 is formed on the first interlayer dielectric layer 200 .

[0066] In this embodiment, the second interlayer dielectric layer 300 is formed on the surface of the second cover layer 230 .

[0067] In this embodiment, the material of the second interlayer dielectric layer 300 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing holes. The description of the material of the second interlayer dielectric layer 300 can refer to the corresponding description of the bottom dielectric layer 110 above, and this embodiment will not be repeated here.

[0068] refer to Figure 8 A first through hole 410 and a first trench 420 are formed in the first interlayer dielectric layer 200 and the second interlayer dielectric layer 300 , and the first through hole 410 exposes the surface of the underlying metal layer 101 .

[0069] In this embodiment, the first through hole 410 passes through the second interlayer dielectric layer 300 and the first interlayer dielectric layer 200, exposing the top surface of the underlying metal layer 101, the first groove is located in the second interlayer dielectric layer 300, the bottom of the first groove 420 is connected to the top of the first through hole 410, and the width of the bottom of the first groove 420 is greater than the width of the top of the first through hole 410.

[0070] In this embodiment, a first through hole 410 is formed passing through two dielectric layers; in other embodiments, a through hole passing through more than two dielectric layers may be formed, which is not limited in the present invention.

[0071] In this embodiment, the first through hole 410 passes through the first interlayer dielectric layer 200 and the second interlayer dielectric layer 300. After the conductive layer is subsequently formed, the metal layer located in the second interlayer dielectric layer and the bottom metal layer located in the bottom dielectric layer can be directly connected, which is beneficial to reducing the resistance of the interconnection structure and improving the performance of the semiconductor structure.

[0072] In this embodiment, a third opening 310 is further formed in the second interlayer dielectric layer 300 , and the third opening 310 exposes the surface of the second metal interconnection layer 210 .

[0073] In this embodiment, the third opening 310 includes a third trench 311 and a third through hole 312 . The third trench 311 is used for subsequently forming a third metal interconnection layer, and the third through hole 312 is used for subsequently forming a third conductive layer.

[0074] In this embodiment, the method for forming the first through hole 410, the first groove 420 and the third opening 310 is to form part of the first through hole by a first etching, deepen the depth of part of the first through hole by a second etching and form part of the second through hole by a third etching, and form the first groove, the first through hole, the third groove and the third through hole by a third etching. The specific steps include:

[0075] refer to Figure 4 , forming a first mask layer having a first trench pattern on the second interlayer dielectric layer 300 .

[0076] In this embodiment, the first mask layer also has a third groove pattern. Specifically, a first hard mask layer 301, a metal hard mask layer 302, a first anti-reflection layer (not shown), and a patterned first photoresist layer (not shown) are sequentially formed on the second interlayer dielectric layer 300; the first anti-reflection layer and the metal hard mask layer 302 are etched using the patterned first photoresist layer as a mask to form an opening, wherein the opening defines the shape and position of the first groove and the third groove to be formed; and the patterned first photoresist layer and the first anti-reflection layer are removed.

[0077] In this embodiment, the material of the first hard mask layer 301 is silicon carbide; in other embodiments, the material of the first hard mask layer 301 may also be silicon nitride or other materials.

[0078] In this embodiment, the first hard mask layer 301 is formed by chemical vapor deposition. In other embodiments, the first hard mask layer may be formed by physical vapor deposition or atomic layer deposition.

[0079] In this embodiment, the material of the metal hard mask layer 302 is titanium nitride; in other embodiments, the material of the metal hard mask layer may also be one or more combinations of tantalum nitride, titanium and tantalum.

[0080] In this embodiment, the metal hard mask layer 302 is formed by chemical vapor deposition. In other embodiments, the metal hard mask layer may be formed by physical vapor deposition or atomic layer deposition.

[0081] refer to Figure 5 , forming a second mask layer having a first through hole pattern on the first mask layer.

[0082] Specifically, a second anti-reflective layer 303, a second hard mask layer 304, and a second photoresist layer (not shown) are sequentially deposited on the exposed first hard mask layer 301 and the metal hard mask layer 302; the second photoresist layer is patterned to form a patterned second photoresist layer 305, defining a pattern of a first through hole, and the pattern of the first through hole is located in the pattern of the first groove.

[0083] refer to Figure 6 Using the patterned second photoresist layer 305 as a mask, the second hard mask layer 304, the second anti-reflection layer 303, the first hard mask layer 301, the second interlayer dielectric layer 300 and the second covering layer 230 are etched to form a partial first through hole of a certain depth in the second interlayer dielectric layer 300.

[0084] It should be noted that, since the first through hole finally formed penetrates the first interlayer dielectric layer 200 and the second interlayer dielectric layer 300, when the first through hole is partially formed by the first etching, the thickness of the remaining dielectric layer to be etched is equal to the depth of the third through hole to be formed. Since the thickness of the second interlayer dielectric layer 300 is equal to the thickness of the first interlayer dielectric layer 200 in this embodiment, the bottom of the part of the first through hole formed by the first etching just exposes the surface of the first interlayer dielectric layer 200.

[0085] refer to Figure 7After forming part of the first through hole, an opening (not shown) is formed on the patterned second photoresist layer 305, and the opening defines the pattern of the third through hole to be formed, and the pattern of the third through hole is located in the pattern of the third groove.

[0086] Continue to refer Figure 7 , a second etching is performed using the patterned second photoresist layer 305 as a mask to deepen the depth of part of the first through hole and form part of the third through hole in the second interlayer dielectric layer 300, and the thickness of the remaining dielectric layer to be etched is equal to the depth of the first trench and the third trench to be formed.

[0087] In this embodiment, the first interlayer dielectric layer 200 is further etched along part of the first through hole to deepen the depth of part of the first through hole, and the second hard mask layer 304, the second anti-reflection layer 303, the first hard mask layer 301 and the second interlayer dielectric layer 300 are etched along the opening to form part of the third through hole in the second interlayer dielectric layer 300. The thickness of the remaining first interlayer dielectric layer 200 to be etched is equal to the thickness of the remaining second interlayer dielectric layer 300 to be etched, and is equal to the depth of the first groove and the third groove to be formed.

[0088] refer to Figure 8 , removing the second mask layer. In this embodiment, specifically, removing the patterned second photoresist layer 305, the second hard mask layer 304 and the second anti-reflection layer 303.

[0089] Continue to refer Figure 8 , the second interlayer dielectric layer 300 and the first interlayer dielectric layer 200 are etched using the first mask layer as a mask to form a first trench 420 and a first through hole 410 .

[0090] In this embodiment, the metal hard mask layer 302 is used as a mask to etch the first hard mask layer 301, the second interlayer dielectric layer 300 and the first interlayer dielectric layer 200, and the first cover layer 120 and the second cover layer 230 are etched using a plasma etching process until the top surface of the underlying metal layer 101 is exposed at a position where the first through hole is to be formed and the surface of the second metal interconnection layer 210 is exposed at a position where the third through hole is to be formed, a first through hole 410 is formed in the second interlayer dielectric layer 300 and the first interlayer dielectric layer 200, a first trench 420 is formed in the second interlayer dielectric layer 300, and a third through hole 312 and a third trench 311 are formed in the second interlayer dielectric layer 300.

[0091] refer to Fig. 9 , removing the metal hard mask layer 302 and the first hard mask layer 301.

[0092] After forming the first through hole 410 and the first trench 420 , a first conductive layer is formed in the first through hole 410 , and a top surface of the first conductive layer is flush with or lower than the top of the first through hole 410 .

[0093] The specific steps of forming the first conductive layer include:

[0094] Continue to refer Fig. 9 , a first conductive material layer 500 is filled in the first through hole 410 and the first trench 420 , and the first conductive material layer 500 also covers the surface of the second interlayer dielectric layer 300 .

[0095] In this embodiment, the first conductive material layer 500 also fills the third trench 311 and the third through hole 312 .

[0096] In this embodiment, the material of the first conductive material layer 500 is cobalt. Since cobalt has good filling properties, it can be filled in through holes with high aspect ratios to avoid the formation of voids, thereby ensuring the quality of the formed first conductive layer and facilitating the performance of the semiconductor structure.

[0097] In other embodiments, the material of the first conductive layer 500 may also be ruthenium.

[0098] In this embodiment, the method for forming the first conductive material layer 500 is physical vapor deposition; in other embodiments, the first conductive material layer may also be formed by electrochemical plating or chemical vapor deposition.

[0099] In this embodiment, before filling the first conductive layer 500, it also includes: forming a blocking layer 201 on the bottom and side wall surfaces of the first through hole 410, the bottom and side wall surfaces of the first groove 420, the bottom and side wall surfaces of the third through hole 312, and the bottom and side wall surfaces of the third groove 311.

[0100] The barrier layer 201 can prevent the conductive material from diffusing into the adjacent dielectric layer. The material of the barrier layer 201 includes TiN, Ti, TaN, Ta, WC, Co or Ru. In this embodiment, the material of the barrier layer 201 is titanium nitride.

[0101] The method for forming the barrier layer 201 includes chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this embodiment, the method for forming the barrier layer 201 is atomic layer deposition.

[0102] refer to Fig.10 , the first conductive material layer 500 is planarized so that the top surface of the first conductive material layer is flush with the top surface of the second interlayer dielectric layer 300 .

[0103] In this embodiment, a chemical mechanical polishing process is used to planarize the first conductive material layer 500 .

[0104] refer to Fig.11 , the first conductive material layer 500 is etched back until the top surface of the first conductive material layer 500 is flush with or lower than the top of the first through hole 410 , to form a first conductive layer 510 .

[0105] In this embodiment, the first conductive material layer 500 is etched back to form a first conductive layer 510 in the first through hole 410, and a third conductive layer 520 is formed in the third through hole 312. The first conductive layer 510 connects the underlying metal layer 101 and a first metal interconnection layer subsequently formed in the first groove 420, and the third conductive layer 520 connects the second metal interconnection layer 210 and a third metal interconnection layer subsequently formed in the third groove 311.

[0106] In this embodiment, the top surface of the first conductive layer 510 is flush with the top surface of the first through hole 410 , and the top surface of the third conductive layer 520 is flush with the top surface of the third through hole 312 .

[0107] In this embodiment, due to the presence of the barrier layer 201 , the depths of the first through hole and the third through hole include the thickness of the barrier layer 201 .

[0108] After the first conductive layer 510 is formed, a first metal interconnection layer is formed in the first trench 420 , and the first metal interconnection layer is also located on the first conductive layer 510 .

[0109] In this embodiment, when forming the first metal interconnection layer, the process further includes: forming a third metal interconnection layer in the third trench 311 , and the third metal interconnection layer is also located on the third conductive layer 520 .

[0110] For details, please refer to Fig.11 , a first metal material layer 600 is filled in the first trench 420 and the third trench 311 , and the first metal material layer 600 also covers the top surface of the second interlayer dielectric layer 300 .

[0111] In this embodiment, the material of the second metal material layer 600 is copper. Since copper has the advantages of low resistivity and good anti-mobility, it is used to form a wiring structure, which can reduce the resistance of the semiconductor structure and improve the performance of the semiconductor structure. In addition, before copper filling, cobalt is first filled in the first through hole 410 to avoid the phenomenon of voids when copper fills the first through hole 410 with a high aspect ratio. The good filling performance of cobalt is used to fill the first through hole with a high aspect ratio, and the low resistance characteristics of copper are used to form a metal interconnection layer. While reducing the resistance of the semiconductor structure, it also avoids the void problem that occurs during the filling process, which is beneficial to improving the performance of the semiconductor structure.

[0112] In this embodiment, the method for forming the first metal material layer 600 is physical vapor deposition; in other embodiments, the first metal material layer may also be formed by electrochemical plating or chemical vapor deposition.

[0113] In this embodiment, before forming the first metal material layer 600 , a seed layer 601 is formed on the bottom and sidewall surfaces of the first trench 420 and the bottom and sidewall surfaces of the third trench 311 .

[0114] The material of the seed layer 601 is the same as that of the first metal material layer 600 . In this embodiment, the material of the seed layer 601 is copper.

[0115] In this embodiment, the seed layer 601 is formed by physical vapor deposition.

[0116] refer to Fig.12 , the first metal material layer 600 is planarized until the top surface of the first metal material layer 600 is flush with the top surface of the second interlayer dielectric layer 300, a first metal interconnection layer 610 is formed in the first groove 420, and the first metal interconnection layer 610 is also located on the first conductive layer 510, and a third metal interconnection layer 620 is formed in the third groove 311, and the third metal interconnection layer 620 is also located on the third conductive layer 520.

[0117] In another embodiment, when the top of the first conductive layer 510 is lower than the top of the first through hole 410 , part of the first metal interconnection layer 610 is still located in the first through hole 410 .

[0118] Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above-mentioned formation method.

[0119] refer to Fig.12The semiconductor structure includes: a substrate 100, in which a bottom metal layer 101 is formed; a first interlayer dielectric layer 200, located on the substrate 100; a second interlayer dielectric layer 300, located on the first interlayer dielectric layer 200; a first through hole 410, located in the first interlayer dielectric layer 200 and the second interlayer dielectric layer 300; a first trench 420, located in the second interlayer dielectric layer 300, and the bottom of the first trench 420 is connected to the top of the first through hole 410; a first conductive layer 510, located in the first through hole 410, and the top surface of the first conductive layer 510 is flush with the top of the first through hole 410 or lower than the top of the first through hole 410; a first metal interconnection layer 610, located in the first trench 420, and the first metal interconnection layer 610 is also located on the first conductive layer 510.

[0120] In this embodiment, a bottom dielectric layer 110 is formed in the substrate 100 , and the bottom metal layer 101 is located in the bottom dielectric layer 110 .

[0121] In this embodiment, the material of the bottom dielectric layer 110 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing holes. In other embodiments, the material of the bottom dielectric layer 110 can also be SiOH, SiOC, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, aluminum nitride or aluminum oxide.

[0122] The material of the bottom metal layer 101 is a conductive material such as Cu, Al or W.

[0123] In this embodiment, the top surface of the bottom metal layer 101 is flush with the top surface of the substrate 100 ; in other embodiments, the top surface of the bottom metal layer 101 may also be higher than the top surface of the substrate 100 .

[0124] In this embodiment, the material of the first interlayer dielectric layer 200 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing holes.

[0125] In this embodiment, the material of the second interlayer dielectric layer 300 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing holes.

[0126] In this embodiment, the first interlayer dielectric layer 200 further includes: a second metal interconnection layer 210 and a second conductive layer 220 , and the second conductive layer 220 connects the second metal interconnection layer 220 and the bottom metal layer 101 .

[0127] In this embodiment, the second metal interconnection layer 210 and the second conductive layer 220 are made of the same material, copper.

[0128] In this embodiment, the top surface of the first conductive layer 510 is flush with the top of the first through hole 410 .

[0129] In other embodiments, the top surface of the first conductive layer 510 may be lower than the top of the first through hole 410 . In this state, a portion of the first metal interconnection layer 610 is still located in the through hole 410 .

[0130] In this embodiment, the material of the first conductive layer 510 is cobalt; in other embodiments, the material of the first conductive layer 510 may also be ruthenium.

[0131] In this embodiment, the material of the first metal interconnection layer 610 is copper.

[0132] In this embodiment, the second interlayer dielectric layer 300 further includes a third conductive layer 520 and a third metal interconnect layer 620 , and the third conductive layer 520 connects the third metal interconnect layer 620 and the second metal interconnect layer 210 .

[0133] The material of the third conductive layer 520 is the same as that of the first conductive layer 510. In this embodiment, the material of the third conductive layer 520 is cobalt; in other embodiments, the material of the third conductive layer 520 may also be ruthenium.

[0134] The third metal interconnection layer 620 is made of the same material as the first metal interconnection layer 610. In this embodiment, the third metal interconnection layer 620 is made of copper.

[0135] refer to Fig.12 The semiconductor structure further includes: a first covering layer 120 located between the bottom dielectric layer 110 and the first interlayer dielectric layer 200 , and a second covering layer 230 located between the first interlayer dielectric layer 200 and the second interlayer dielectric layer 300 .

[0136] The material of the first cover layer 120 is different from that of the underlying dielectric layer 110. The material of the first cover layer 120 includes silicon nitride, silicon oxynitride or silicon carbonitride. In this embodiment, the material of the first cover layer 120 is silicon carbonitride.

[0137] The material of the second cover layer 230 is different from that of the first interlayer dielectric layer 200. The material of the second cover layer 230 includes silicon nitride, silicon oxynitride or silicon carbonitride. In this embodiment, the material of the second cover layer 230 is silicon carbonitride.

[0138] refer to Fig.12The semiconductor structure further includes: a barrier layer 201 located at the bottom and sidewall surfaces of the first through hole 410 , the first trench 420 , the second through hole, the second trench, the third through hole 312 , and the third trench 311 .

[0139] The barrier layer 201 can prevent the conductive material from diffusing into the adjacent dielectric layer. The material of the barrier layer 201 includes TiN, Ti, TaN, Ta, WC, Co or Ru. In this embodiment, the material of the barrier layer 201 is titanium nitride.

[0140] In this embodiment, the semiconductor structure further includes: a seed layer 601 located at the bottom and sidewall surfaces of the first trench 420 and the third trench 311 .

[0141] The material of the seed layer 601 is the same as that of the first metal interconnection layer 610. In this embodiment, the material of the seed layer 601 is copper.

[0142] In the semiconductor structure provided by the embodiment of the present invention, the first through hole 410 passes through the first interlayer dielectric layer 200 and the second interlayer dielectric layer 300, and the first conductive layer 410 located in the first through hole 410 is directly connected to the bottom metal layer 101 located in the bottom dielectric layer 110 and the first metal interconnection layer 610 located in the second interlayer dielectric layer 300, thereby reducing the resistance of the interconnection structure and improving the electrical performance of the semiconductor structure; and the first conductive layer 510 is located in the first through hole 410, and the first metal interconnection layer 610 is located in the first trench 420, the first conductive layer 510 with good filling performance is used to fill the first through hole 410 with a high aspect ratio, and the first metal interconnection layer 610 with lower resistance is used to fill the first trench 420, while reducing the resistance of the interconnection structure, it also avoids defects such as filling voids, which is beneficial to the performance of the semiconductor structure.

[0143] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate having an underlying metal layer formed therein; forming a first interlayer dielectric layer on the substrate, wherein a second conductive layer and a second metal interconnect layer are formed in the first interlayer dielectric layer, and the second metal interconnect layer is located on the second conductive layer; forming a second interlayer dielectric layer on the first interlayer dielectric layer; Etching the second interlayer dielectric layer to form a portion of the first through hole in the second interlayer dielectric layer, wherein the thickness of the remaining first interlayer dielectric layer and the second interlayer dielectric layer to be etched is equal to the thickness of the second interlayer dielectric layer; Etching the second interlayer dielectric layer and the first interlayer dielectric layer to deepen the depth of the portion of the first through hole, forming a portion of the first through hole in the second interlayer dielectric layer and the first interlayer dielectric layer, forming a portion of the third through hole in the second interlayer dielectric layer, and the thickness of the first interlayer dielectric layer at the bottom of the portion of the first through hole is equal to the thickness of the second interlayer dielectric layer at the bottom of the portion of the third through hole; Continue etching the second interlayer dielectric layer and the first interlayer dielectric layer to form a first through hole in the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the bottom of the first through hole exposes the surface of the bottom metal layer, and a third through hole is formed in the second interlayer dielectric layer, wherein the bottom of the third through hole exposes the surface of the second metal interconnection layer, and a first trench and a third trench are formed in the second interlayer dielectric layer, wherein the bottom of the first trench is connected to the top of the first through hole, and the bottom of the third trench is connected to the top of the third through hole; forming a first conductive layer in the first through hole; forming a third conductive layer in the third through hole; forming a first metal interconnection layer in the first trench, wherein the first metal interconnection layer is also located on the first conductive layer; A third metal interconnection layer is formed in the third trench, and the third metal interconnection layer is also located on the third conductive layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: A top surface of the first conductive layer is flush with or lower than a top of the first through-hole.

3. The method for forming a semiconductor structure according to claim 2, wherein: When the top surface of the first conductive layer is lower than the top of the first through hole, the method further includes: forming a first metal interconnection layer in a portion of the first through hole.

4. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming the first conductive layer comprises: Filling a first conductive material layer in the first through hole and the first trench, wherein the first conductive material layer also covers a top surface of the second interlayer dielectric layer; performing a planarization process on the first conductive material layer so that a top surface of the first conductive material layer is flush with a top surface of the second interlayer dielectric layer; The first conductive material layer is etched back until the top surface of the first conductive material layer is flush with or lower than the top of the first through hole, so as to form a first conductive layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the first metal interconnection layer comprises: A first metal material layer is filled in the first groove, the first metal material layer is located on the first conductive layer, and the first metal material layer also covers the top surface of the second interlayer dielectric layer; the first metal material layer is planarized until the top surface of the first metal material layer is flush with the top surface of the second interlayer dielectric layer, so as to form a first metal interconnection layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the first through hole and the first trench include: forming a first mask layer having a first trench pattern on the second interlayer dielectric layer; forming a second mask layer having a first through hole pattern on the first mask layer; Using the second mask layer as a mask, etching the second interlayer dielectric layer and a portion of the first interlayer dielectric layer to form a portion of the first through hole; removing the second mask layer; Using the first mask layer as a mask, the second interlayer dielectric layer and the first interlayer dielectric layer are etched to form a first trench and a first through hole.

7. The method for forming a semiconductor structure according to claim 4, wherein: Before filling the first conductive material layer, the method further includes: forming a barrier layer on the bottom and side wall surfaces of the first through hole and the bottom and side wall surfaces of the first trench.

8. The method for forming a semiconductor structure according to claim 7, wherein: The material of the barrier layer includes TiN, Ti, TaN, Ta, WC, Co or Ru.

9. The method for forming a semiconductor structure according to claim 5, wherein: Before filling the first metal material layer in the first trench, the method further includes: forming a seed layer on the bottom and sidewall surface of the first trench and the surface of the first conductive layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first conductive layer includes Co or Ru.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first metal interconnection layer includes Cu, Ag, Au or Al.

12. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 11, characterized in that: include: a substrate having an underlying metal layer formed therein; A first interlayer dielectric layer, located on the substrate, a second conductive layer and a second metal interconnect layer are formed in the first interlayer dielectric layer, and the second metal interconnect layer is located on the second conductive layer; A second interlayer dielectric layer, located on the first interlayer dielectric layer; A first through hole is located in the first interlayer dielectric layer and the second interlayer dielectric layer; A first trench is located in the second interlayer dielectric layer, and the bottom of the first trench is connected to the top of the first through hole; a third through hole, located in the second interlayer dielectric layer, wherein the bottom of the third through hole exposes the surface of the second metal interconnection layer; A third trench is located in the second interlayer dielectric layer, and the bottom of the third trench is connected to the top of the third through hole; A first conductive layer, located in the first through hole; A third conductive layer is located in the third through hole; A first metal interconnection layer is located in the first trench, and the first metal interconnection layer is also located on the first conductive layer; The third metal interconnection layer is located in the third trench, and the third metal interconnection layer is also located on the third conductive layer.

13. The semiconductor structure according to claim 12, wherein: A top surface of the first conductive layer is flush with or lower than a top of the first through hole.

14. The semiconductor structure according to claim 13, wherein: When the top surface of the first conductive layer is lower than the top of the first through hole, a portion of the first metal interconnection layer is located in the first through hole.

15. The semiconductor structure according to claim 12, wherein: Also includes: A barrier layer is located on the bottom and sidewall surfaces of the first through hole and the bottom and sidewall surfaces of the first trench.

16. The semiconductor structure according to claim 15, wherein: The material of the barrier layer includes TiN, Ti, TaN, Ta, WC, Co or Ru.

17. The semiconductor structure according to claim 12, wherein: The material of the first conductive layer includes Co or Ru. 18 . The semiconductor structure according to claim 12 , wherein a material of the first metal interconnection layer comprises Cu, Ag, Au or Al.

Images