Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, characterized by comprising: providing an initial substrate, the initial substrate comprising a plurality of invalid regions and an effective region surrounding the invalid regions; forming a cutting layer in the initial substrate in the invalid regions; forming a plurality of first mask structures on the surface of the initial substrate, at least one first mask structure spanning the cutting layer; using the first mask structure as a mask, etching the cutting layer and the initial substrate until a substrate, a plurality of first fin structures located on the substrate, and a plurality of first dummy fin structures located on the substrate are formed; after forming the first fin structures and the first dummy fin structures, removing the plurality of first dummy fin structures. Thus, the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the high integration of semiconductor devices, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is constantly shortening, and a series of effects that can be ignored in the MOSFET long channel model have become more and more significant, and even become the dominant factor affecting device performance. This phenomenon is collectively referred to as the short channel effect. The short channel effect will deteriorate the electrical performance of the device, such as causing a decrease in gate threshold voltage, increased power consumption, and a decrease in signal-to-noise ratio.

[0003] In order to overcome the short channel effect, a three-dimensional device structure of a fin field effect transistor is proposed. The fin field effect transistor is a transistor with a fin-shaped channel structure. The fin field effect transistor uses several surfaces of a thin fin as a channel, thereby preventing the short channel effect in traditional transistors and increasing the operating current. In the manufacturing process of the fin field effect transistor, the manufacturing of the fin is a very important part.

[0004] However, the performance of existing semiconductor structures is still poor. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which improves the graphic accuracy of the cutting layer and the first fin structure and reduces the defects of the semiconductor structure to improve the performance of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing an initial substrate, the initial substrate including a plurality of invalid areas and an effective area surrounding the invalid areas; forming a cutting layer in the initial substrate in the invalid areas, the surface of the initial substrate exposing the surface of the cutting layer; forming a plurality of first mask structures on the surfaces of the invalid areas and the effective areas, at least one first mask structure spanning the cutting layer; using the first mask structure as a mask, etching the cutting layer and the initial substrate until a substrate, a plurality of first fin structures located on the substrate, and a plurality of first dummy fin structures located on the substrate are formed, the first fin structures being separate from each other and located in the effective areas, and the first dummy fin structures being located in the invalid areas; after forming the first fin structures and the first dummy fin structures, removing the plurality of first dummy fin structures.

[0007] Optionally, the method for forming the cutting layer includes: forming a second mask structure on the initial substrate surface, wherein the second mask structure exposes the initial substrate surface of the invalid area.

[0008] Optionally, the second mask structure includes a second mask layer; the method for forming the second mask layer includes: forming a second mask material layer on the surface of the effective area and the invalid area; forming a second photoresist layer on the surface of the second mask material layer, the second photoresist layer exposing the surface of the second mask material layer on the invalid area; using the second photoresist layer as a mask, etching the second mask material layer until the initial substrate surface is exposed.

[0009] Optionally, the material of the second mask layer includes spin-on carbon.

[0010] Optionally, the second mask structure also includes a second hard mask layer, and the second mask layer is located on the surface of the second hard mask layer; the method for forming the second hard mask layer includes: before forming the second mask material layer, forming a second hard mask material layer on the surface of the effective area and the invalid area; after etching the second mask material layer, continuing to etch the second hard mask material layer until the initial substrate surface is exposed.

[0011] Optionally, a material of the second hard mask layer includes one or more combinations of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon or silicon nitride.

[0012] Optionally, the method further includes: before forming the second photoresist layer, forming an anti-reflection layer on the surface of the second mask material layer.

[0013] Optionally, the method for forming the cutting layer further includes: etching the initial substrate using the second mask structure as a mask to form a first opening in the ineffective area; and forming the cutting layer in the first opening.

[0014] Optionally, in the etching process for forming the first opening, an etching selectivity ratio between the material of the initial substrate and the material of the second mask layer is greater than 5:1.

[0015] Optionally, the method for forming the cutting layer in the first opening includes: forming a cutting material layer on the initial substrate surface and in the first opening, the process of forming the cutting material layer including one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or an epitaxial growth process; flattening the cutting material layer until the initial substrate surface is exposed.

[0016] Optionally, the method for forming the cutting layer further includes: using the second mask structure as a mask to perform an ion doping process on the initial substrate of the ineffective area.

[0017] Optionally, the ion doping process includes an ion implantation process.

[0018] Optionally, the process parameters of the ion implantation process include: the implantation dose range is 1.0e16atom / cm 3 ~1.0e20atom / cm 3 ; The injection energy range is 10KeV~200KeV.

[0019] Optionally, the material of the cutting layer includes one or more combinations of silicon nitride, silicon oxide, silicon germanium and silicon phosphide.

[0020] Optionally, the material of the first mask structure includes one or more combinations of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon nitride.

[0021] Optionally, in the etching process for etching the cutting layer and the initial substrate, an etching selectivity ratio between the material of the cutting layer and the material of the first mask structure is greater than 3:1.

[0022] Optionally, the process of forming the plurality of first mask structures comprises a multiple self-alignment patterning process.

[0023] Optionally, the method for forming several first mask structures includes: forming a first mask material layer on the surface of the initial substrate in the effective area and the cutting layer in the invalid area; forming several mutually discrete first core mold structures on the surface of the first mask material layer; forming a first side wall on the side wall surface of each of the first core mold structures; using the first side wall as a mask, etching the first mask material layer until the surface of the cutting layer and the surface of the initial substrate are exposed.

[0024] Optionally, the method for forming the first side wall includes: forming a first side wall material layer on the surface of the first mask material layer and the surface of the first core mold structure; and etching back the first side wall material layer until the surface of the first mask material layer and the top surface of the first core mold structure are exposed.

[0025] Optionally, the method for forming the first core mold structure includes: forming a first core mold material layer on the surface of the first mask material layer; forming a first photoresist layer on the surface of the first core mold material layer, the first photoresist layer exposing a portion of the surface of the first core mold material layer; using the first photoresist layer as a mask, etching the first core mold material layer until the surface of the first mask material layer is exposed.

[0026] Optionally, the method for forming the first core mold structure includes: forming a first core mold material layer on the surface of the first mask material layer; forming a plurality of mutually discrete second core mold structures on the surface of the first core mold material layer; forming a second side wall on the side wall surface of the second core mold structure; and etching the first core mold material layer using the second side wall as a mask until the surface of the first mask material layer is exposed.

[0027] Optionally, the material of the first core mold structure includes one or more combinations of amorphous silicon, silicon nitride, silicon oxide, amorphous carbon and photoresist.

[0028] Optionally, the material of the first spacer includes: a combination of one or more of silicon oxide, silicon nitride, silicon and titanium oxide.

[0029] Optionally, it also includes: before forming the first mask material layer, forming a first protective material layer on the initial substrate of the effective area and the cutting layer surface of the invalid area; after etching the first mask material layer, continuing to etch the first protective material layer until the cutting layer surface and the initial substrate surface are exposed to form a first protective layer.

[0030] Optionally, the material of the first protective layer includes silicon oxide.

[0031] Optionally, the etching process includes a wet etching process or a plasma etching process.

[0032] Optionally, the process of removing the first dummy fin structure includes an etching process, in which an etching selectivity ratio between a material of the first dummy fin structure and a material of the substrate is greater than 5:1.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0034] In the method for forming a semiconductor structure provided by the technical solution of the present invention, since the initial substrate includes a plurality of invalid areas and an effective area surrounding the invalid areas, and a first fin structure that is separate from each other and located in the effective area, and a first dummy fin structure located in the invalid area are formed, that is, in the extension direction of the first fin structure, the first dummy fin structure is connected to the first fin structure, and after the first fin structure and the first dummy fin structure are formed, a plurality of the first dummy fin structures are removed. Therefore, in the extension direction of the first fin structure, the first fin structures on both sides of the invalid area can be separated by the first dummy fin structure, thereby forming a first fin structure with a shorter length to improve the integration of the semiconductor structure. On this basis, since a cutting layer is formed in the initial substrate of the invalid area before forming the first mask structure, on the first hand, the influence of subsequent etching and cleaning processes on the cutting layer is reduced to improve the graphic accuracy of the cutting layer, and the influence of the accuracy of subsequent other graphic layers and subsequent etching and cleaning processes on the overlay accuracy of the photoresist layer graphic used to form the cutting layer graphic is reduced, thereby increasing the process window size of the process for forming the cutting layer, thereby improving the performance of the semiconductor structure; on the second hand, the first mask structure can be formed directly through a graphic layer to form the first fin structure through the first mask structure, thereby reducing the number of graphic layers for forming the first mask structure and simplifying the graphic process for forming the first mask structure, thereby improving the graphic accuracy of the first mask structure, so that the graphic accuracy of the first fin structure is improved, and further, the performance of the semiconductor structure is improved; on the third hand, the graphic process for forming the first mask structure is simplified. The process can also reduce the number of etching and cleaning times of the patterned layer forming the first mask structure during the patterning process, thereby reducing the residue contamination generated during the etching and cleaning processes, so that the defects of the semiconductor structure can be reduced, and the over-etching caused by the etching is reduced, thereby reducing the downward transmission of the over-etching, thereby improving the graphic accuracy of the first fin structure and improving the performance of the semiconductor structure; in the fourth aspect, when removing a number of the first pseudo-fin structures, the material of the cutting layer, that is, the material of the first pseudo-fin structure, can be selected to increase the etching process for removing the first pseudo-fin structure, the etching selectivity of the first fin structure material and the first pseudo-fin structure material, reduce the damage of the etching process to the surface of the first fin structure, so as to improve the graphic accuracy of the first fin structure, and reduce the residue contamination of the first pseudo-fin structure during the etching process, so as to reduce the defects of the semiconductor structure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0036] Figures 4 to 22It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, the performance of the semiconductor structure is still relatively poor. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0038] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0039] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0040] Please refer to Figure 1 , providing a substrate 10, wherein the substrate 10 includes a plurality of invalid areas I; forming a first mask material layer 20 on the surface of the substrate 10; forming an initial second mask layer 30 on the surface of the first mask material layer 20; forming a cutting material layer 50 on the surface of the initial second mask layer 30 and the surface of the first mask material layer 20; forming a photoresist layer 51 on the surface of the cutting material layer 50, wherein the photoresist layer 51 exposes the surface of the cutting material layer 50 of the invalid area I.

[0041] The process of forming the initial second mask layer 30 includes a self-aligned multiple patterning process.

[0042] Please refer to Figure 2 , using the photoresist layer 51 as a mask, etching the cutting material layer 50 and the initial second mask layer 30 until the surface of the first mask material layer 20 is exposed to form a second mask layer 40 and a cutting layer (not shown); after forming the second mask layer 40, removing the cutting layer and the photoresist layer 51.

[0043] Please refer to Figure 3 After removing the cutting layer and the photoresist layer 51, the first mask material layer 20 is etched using the second mask layer 40 as a mask until the surface of the substrate 10 is exposed to form a first mask layer 21; after forming the first mask layer 21, the substrate 10 is etched using the first mask layer 21 as a mask to form a plurality of discrete fin structures 11 on the substrate 10.

[0044] However, in the above method, the deviation of the etching process for forming the initial second mask layer 30 not only causes the pattern of the initial second mask layer 30 to be easily deviated, but also, affected by the deviation, the pattern accuracy of the photoresist layer 51 is also affected. Moreover, the pattern accuracy of the photoresist layer 51 is also affected by the deviation of the pattern accuracy of the photoresist layer used to form the initial second mask layer 30. Therefore, on the one hand, the pattern accuracy (including overlay accuracy) of the photoresist layer 51 is poor. On the other hand, the formation of the photoresist layer 51 is subject to more constraints, resulting in a smaller process window for forming the photoresist layer 51. As a result, the pattern accuracy of the fin structure 11 finally formed is low, and the performance of the semiconductor structure is poor.

[0045] In addition, in the process of etching the cutting material layer 50 and the initial second mask layer 30 using the photoresist layer 51 as a mask, the etching process is prone to over-etching the surface of the first mask material layer 20, which not only causes damage to the surface of the first mask material layer 20 and reduces the graphic accuracy of the first mask layer 21, but the over-etching is also easily transmitted downward, resulting in the graphic accuracy of the fin structure 11 being affected, thereby causing the performance of the semiconductor structure to be poor. Moreover, in the process of removing the cutting layer and the photoresist layer 51, in order to reduce the damage to the second mask layer 40 caused by the cleaning process, the intensity of the cleaning process is relatively low. Therefore, after removing the cutting layer and the photoresist layer 51, the surface of the first mask material layer 20 is prone to be contaminated by the residues of the cutting layer and the photoresist layer 51, thereby increasing the defects of the semiconductor structure and causing the performance of the semiconductor structure to be poor. In summary, the performance of the semiconductor structure is still poor.

[0046] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, by forming a cutting layer in an invalid area before forming a first fin structure, and removing several first dummy fin structures after forming the first fin structure and the first dummy fin structure, thereby improving the performance of the semiconductor structure.

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figures 4 to 22 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0049] Please refer to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of a top view of a semiconductor structure in an embodiment of the present invention, Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure in the X-X1 direction provides an initial substrate 100, wherein the initial substrate 100 includes a plurality of invalid regions B and an effective region A surrounding the invalid regions B.

[0050] The initial substrate 100 is made of semiconductor material.

[0051] In this embodiment, the material of the initial substrate 100 is silicon.

[0052] In other embodiments, the material of the initial substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0053] Subsequently, a cutting layer is formed in the initial substrate 100 in the ineffective area B, and the surface of the cutting layer is exposed on the surface of the initial substrate 100. For details on the process of forming the cutting layer, please refer to Figures 6 to 12 .

[0054] Please refer to 6 and Figure 7 , Figure 6 is Figure 4 Schematic diagram of the top view of the structure on the foundation. Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure in the X-X1 direction shows that a second hard mask material layer 111 is formed on the surfaces of the effective area A and the invalid area B; a second mask material layer 112 is formed on the surface of the second hard mask material layer 111; a second photoresist layer 120 is formed on the surface of the second mask material layer 112, and the second photoresist layer 120 exposes the surface of the second mask material layer 112 on the invalid area B.

[0055] The second hard mask material layer 111 is used to provide material for subsequently forming a second hard mask layer.

[0056] The material of the second hard mask material layer 111 includes one or more combinations of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon or silicon nitride. Accordingly, the material of the second hard mask layer includes one or more combinations of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon or silicon nitride.

[0057] Since the material of the second hard mask layer has a high hardness, the material of the second hard mask layer is less lost during the pattern transfer process, thereby facilitating the improvement of the pattern accuracy during the pattern transfer process. In summary, the second hard mask layer can improve the pattern accuracy of the subsequently formed cutting layer.

[0058] The second mask material layer 112 is used, on the one hand, to provide material for the subsequent formation of the second mask layer, and on the other hand, is also used to increase the anti-reflection effect during the photolithography process of forming the second photoresist layer 120 , thereby improving the graphic accuracy of the second photoresist layer 120 .

[0059] In this embodiment, the material of the second mask material layer 112 includes spin-coated carbon. Accordingly, the material of the second mask layer includes spin-coated carbon. Since the spin-coated carbon has good filling property and fluidity, the flatness of the second mask material layer 112 can be improved, which is conducive to forming the second photoresist layer 120 with high pattern accuracy, so as to improve the performance of the semiconductor structure.

[0060] In this embodiment, an anti-reflection layer 121 may be formed on the surface of the second mask material layer 112 before forming the second photoresist layer 120. Thus, the anti-reflection layer 121 can increase the anti-reflection effect during the photolithography process of forming the second photoresist layer 120, thereby improving the pattern accuracy of the second photoresist layer 120.

[0061] The anti-reflection layer 121 includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0062] It should be noted that, in this embodiment, since the anti-reflection layer 121 is formed on the surface of the second mask material layer 112 before the second photoresist layer 120 is formed, the second photoresist layer 120 exposes the surface of the second mask material layer 112 on the invalid area B means that the second photoresist layer 120 exposes the surface of the anti-reflection layer 121 on the invalid area B.

[0063] In other embodiments, the anti-reflection layer is not formed.

[0064] Please refer to Figure 8 and Fig. 9 , Figure 8 is Figure 6 Schematic diagram of the top view of the structure on the foundation. Fig. 9 yes Figure 8 The schematic diagram of the cross-sectional structure in the X-X1 direction shows that the second mask material layer 112 is etched with the second photoresist layer 120 as a mask to form a second mask layer 114; after etching the second mask material layer 112, the second hard mask material layer 111 is continuously etched until the surface of the initial substrate 100 is exposed to form a second hard mask layer 113, and the second mask layer 114 is located on the surface of the second hard mask layer 113.

[0065] In this embodiment, the second hard mask layer 113 and the second mask layer 114 form a second mask structure 110 . The second mask structure 110 is located on the surface of the initial substrate 100 and exposes the inactive region B of the initial substrate 100 .

[0066] In this embodiment, the process of etching the second hard mask material layer 111 and the second mask material layer 112 includes a dry etching process or a wet etching process.

[0067] In this embodiment, after the second mask structure 110 is formed, the anti-reflection layer 121 and the second photoresist layer 120 are removed.

[0068] Please refer to Fig.10 and Fig.11 , Fig.10 is Figure 8 Schematic diagram of the top view of the structure on the foundation. Fig.11 yes Fig.10 The schematic diagram of the cross-sectional structure in the X-X1 direction shows that the initial substrate 100 is etched using the second mask structure 110 as a mask to form a first opening 103 in the invalid area B.

[0069] In this embodiment, in the etching process for forming the first opening 103 , the etching selectivity ratio between the material of the initial substrate 100 and the material of the second mask layer 114 is greater than 5:1.

[0070] The etching process for forming the first opening 103 includes a dry etching process or a wet etching process.

[0071] In this embodiment, the etching process for forming the first opening 103 is a dry etching process, and the gas used in the dry etching process includes C x F y , C x H y F z , C x H y , H2, O2, SO2, COS, He, Ar and N 2 One or a combination of the following.

[0072] In this embodiment, after the first opening 103 is formed, the second mask structure 110 is removed.

[0073] Please refer to Fig.12 , Fig.12 is with Fig.10 In the schematic diagram of the top view of the structure along the same direction, a cutting layer 130 is formed in the first opening 103 .

[0074] The cutting layer 130 is used to provide material for subsequently forming a first dummy fin structure.

[0075] In this embodiment, the method for forming the cutting layer 130 in the first opening 103 includes: forming a cutting material layer (not shown) on the surface of the initial substrate 100 and in the first opening 103; and planarizing the cutting material layer until the surface of the initial substrate 100 is exposed.

[0076] In this embodiment, the process of forming the cutting material layer includes: a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or an epitaxial growth process.

[0077] In this embodiment, the material of the cutting layer 130 includes one or more combinations of silicon nitride, silicon oxide, silicon germanium and silicon phosphide.

[0078] In this embodiment, the method for planarizing the cutting material layer includes: a chemical mechanical polishing process, a wet etching process or a dry etching process.

[0079] In other embodiments, the method for forming the cutting layer further includes: after forming the second mask structure, using the second mask structure as a mask, performing an ion doping process on the initial substrate of the invalid area, wherein the ion doping process includes an ion implantation process, and the process parameters of the ion implantation process include: an implantation dose range of 1.0e16atom / cm 3 ~1.0e20atom / cm 3 ; The injection energy range is 10KeV~200KeV.

[0080] On the one hand, in the subsequent etching process of removing the cutting layer, the ion doping process can increase the etching selectivity of the etching process for the cutting layer and the initial substrate; on the other hand, since the cutting layer is directly formed in the initial substrate by the ion doping process, the steps of forming the cutting layer are reduced, that is, it is not necessary to form an opening in the initial substrate before forming the cutting layer, and to flatten the cutting material layer after forming the cutting material layer in the opening and on the surface of the initial substrate. Thus, the time and complexity of the semiconductor process are reduced.

[0081] Subsequently, a plurality of first mask structures are formed on the surfaces of the ineffective area B and the effective area A, and at least one first mask structure crosses the cutting layer 130. In this embodiment, the process of forming the plurality of first mask structures includes a multiple self-aligned patterning process. For the specific process of forming the first mask structure, please refer to Figures 13 to 18 .

[0082] Please refer to Fig.13 and Fig.14 , Fig.13 is Fig.12 Schematic diagram of the top view of the structure on the foundation. Fig.14 yes Fig.13 Schematic diagram of the cross-sectional structure in the X-X1 direction, a first mask material layer 140 is formed on the surface of the initial substrate 100 in the effective area A and the cutting layer 130 in the invalid area B; a first core mold material layer 150 is formed on the surface of the first mask material layer 140; after the first core mold material layer 150 is formed, a plurality of mutually discrete second core mold structures 160 are formed on the surface of the first core mold material layer 150; and second side walls 161 are formed on the side walls of the plurality of mutually discrete second core mold structures 160.

[0083] The first mask material layer 140 provides material for subsequently forming a first mask structure.

[0084] In this embodiment, the process of forming the first mask material layer 140 includes a chemical vapor deposition process, an epitaxial growth process or an atomic layer deposition process.

[0085] In this embodiment, the material of the first mask material layer 140 includes one or more combinations of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon nitride. Accordingly, the material of the first mask structure includes one or more combinations of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon nitride.

[0086] The first core mold material layer 150 provides material for subsequently forming a first core mold structure.

[0087] In this embodiment, the process of forming the first core mold material layer 150 includes a chemical vapor deposition process, an epitaxial growth process or an atomic layer deposition process.

[0088] In this embodiment, the material of the first core mold material layer 150 includes one or more combinations of amorphous silicon, silicon nitride, silicon oxide, amorphous carbon and photoresist. Correspondingly, the material of the first core mold structure includes one or more combinations of amorphous silicon, silicon nitride, silicon oxide, amorphous carbon and photoresist.

[0089] In this embodiment, the method for forming the second core mold structure 160 includes: forming a second core mold material layer (not shown) on the surface of the first core mold material layer 150; forming a second core mold photoresist layer on the surface of the second core mold material layer, the second core mold photoresist layer exposing a portion of the surface of the second core mold material layer; using the second core mold photoresist layer as a mask, etching the second core mold material layer until the surface of the first core mold material layer 150 is exposed.

[0090] In this embodiment, the process of forming the second core mold material layer includes a chemical vapor deposition process, an epitaxial growth process or an atomic layer deposition process.

[0091] In this embodiment, the process of etching the second core mold material layer includes a wet etching process or a dry etching process.

[0092] In this embodiment, after the second core mold structure 160 is formed, the second core mold photoresist layer is removed.

[0093] In this embodiment, the method for forming the second side wall 161 includes: after forming the second core mold structure 160, forming a second side wall material layer (not shown) on the exposed surface of the first core mold material layer 150 and the surface of the second core mold structure 160; and etching back the second side wall material layer until the top surface of the second core mold structure 160 and the surface of the first core mold material layer 150 are exposed.

[0094] In this embodiment, the process of forming the second spacer material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0095] In this embodiment, the process of etching back the second spacer material layer includes an anisotropic plasma etching process.

[0096] In other embodiments, the process of forming the second mandrel structure includes a multiple self-aligned patterning process.

[0097] In this embodiment, after the second sidewall 161 is formed, the second core mold structure 160 is removed.

[0098] In this embodiment, before forming the first mask material layer 140 , a first protection material layer 105 is formed on the surface of the initial substrate 100 in the active area A and the cutting layer 130 in the inactive area B.

[0099] Since the first protective material layer 105 is formed before forming the first mask material layer 140 , the first protective material layer 105 can protect the initial substrate 100 and the cutting layer 130 , thereby reducing damage to the initial substrate 100 and the cutting layer 130 caused by subsequent processes.

[0100] The first protective material layer 105 is used to provide material for subsequently forming a first protective layer.

[0101] In this embodiment, the material of the first protective material layer 105 includes silicon oxide. Accordingly, the material of the first protective layer includes silicon oxide.

[0102] Since the material of the first protective layer is silicon oxide, which has good filling and adhesion properties, on the one hand, the first protective layer can increase the adhesion between the initial substrate 100 and the cutting layer 130 and the first mask material layer 140; on the other hand, the first protective layer can also improve the interface state between the initial substrate 100 and the cutting layer 130. Thus, the performance of the semiconductor structure is improved.

[0103] The process of forming the first protective material layer 105 includes a thermal oxidation process or a deposition process.

[0104] In this embodiment, the process of forming the first protective material layer 105 is a thermal oxidation process.

[0105] Please refer to Fig.15 , Fig.15 Yes and Fig.14 The schematic diagram of the cross-sectional structure along the same direction shows that the first core mold material layer 150 is etched using the second sidewall 161 as a mask until the surface of the first mask material layer 140 is exposed, so as to form a plurality of mutually discrete first core mold structures 151 on the surface of the first mask material layer 140 .

[0106] In other embodiments, the second core mold structure and the second sidewall are not formed. The method for forming the first core mold structure includes: after forming the first core mold material layer, forming a first photoresist layer on the surface of the first core mold material layer, the first photoresist layer exposing a portion of the surface of the first core mold material layer; using the first photoresist layer as a mask, etching the first core mold material layer until the surface of the first mask material layer is exposed. Thus, a plurality of mutually separate first core mold structures are formed on the surface of the first mask material layer.

[0107] In this embodiment, the process of etching the first core mold material layer 150 includes a dry etching process or a wet etching process.

[0108] Please refer to Fig.16 , Fig.16 Yes and Fig.15 According to the schematic cross-sectional structure diagram along the same direction, a first sidewall 152 is formed on the sidewall surface of each of the first core mold structures 151 , and at least one of the first sidewalls 152 spans across the inactive area B.

[0109] In this embodiment, the method for forming the first side wall 152 includes: forming a first side wall material layer (not shown) on the surface of the first mask material layer 140 and the surface of the first core mold structure 151; and etching back the first side wall material layer until the surface of the first mask material layer 140 and the top surface of the first core mold structure 151 are exposed.

[0110] In this embodiment, the process of forming the first spacer material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0111] In this embodiment, the process of etching back the first spacer material layer includes an anisotropic plasma etching process.

[0112] In this embodiment, the material of the first spacer material layer includes one or more combinations of silicon oxide, silicon nitride, silicon and titanium oxide. Accordingly, the material of the first spacer 152 includes one or more combinations of silicon oxide, silicon nitride, silicon and titanium oxide.

[0113] In this embodiment, after the first sidewall 152 is formed, the first core mold structure 151 is removed.

[0114] Please refer to Fig.17 and Fig.18 , Fig.17 is with Fig.13 Schematic diagram of the structure viewed from above in the same direction. Fig.18 is along Fig.17 The schematic diagram of the cross-sectional structure along the X-X1 direction shows that the first side wall 152 is used as a mask to etch the first mask material layer 140 until the surface of the cutting layer 130 and the surface of the initial substrate 100 are exposed, so as to form a plurality of first mask structures 141 on the surfaces of the invalid area B and the valid area A, and at least one first mask structure 141 spans across the cutting layer 130.

[0115] The first mask structure 141 is used as a mask for subsequently forming a first fin structure.

[0116] Therefore, by subsequently removing the first dummy fin structure, the pattern transferred downward by the first mask structure 141 across the inactive region B can be disconnected.

[0117] Since the cutting layer 130 is formed in the initial substrate 100 of the invalid area B before the first mask structure 141 is formed, on the one hand, the influence of the subsequent etching and cleaning processes on the cutting layer 130 is reduced to improve the pattern accuracy of the cutting layer 130, and the influence of the accuracy of the subsequent other patterned layers and the subsequent etching and cleaning processes on the overlay accuracy of the second photoresist layer 120 pattern used to form the cutting layer 130 pattern is reduced, and the process window size of the process of forming the cutting layer 130 is increased, thereby improving the performance of the semiconductor structure. On the other hand, the first mask structure 141 can be directly formed through a patterned layer (first core mold structure 151) to form the first fin structure, which reduces the number of patterned layers for forming the first mask structure 141 and simplifies the patterning process for forming the first mask structure 141, thereby improving the pattern accuracy of the first mask structure 141, so that the pattern accuracy of the first fin structure is improved, and then the performance of the semiconductor structure is improved. At the same time, simplifying the patterning process of forming the first mask structure 141 can also reduce the number of etching and cleaning times of the patterning layer forming the first mask structure 141 during the patterning process, thereby reducing the residue contamination generated during the etching and cleaning processes, thereby reducing the defects of the semiconductor structure, and also reducing the over-etching caused by the etching, thereby reducing the downward transfer of the over-etching, thereby improving the graphic accuracy of the first fin structure and improving the performance of the semiconductor structure.

[0118] In this embodiment, since the first protective material layer 105 is formed on the surface of the initial substrate 100 in the effective area A and the surface of the cutting layer 130 in the invalid area B before the first mask material layer 140 is formed, etching the first mask material layer 140 until the surface of the cutting layer 130 and the surface of the initial substrate 100 are exposed means that the first mask material layer 140 is etched until the surface of the first protective material layer 105 on the surface of the cutting layer 130 and the initial substrate 100 is exposed.

[0119] In this embodiment, the process of etching the first mask material layer 140 includes a wet etching process or a dry etching process.

[0120] In this embodiment, after etching the first mask material layer 140 , the first protection material layer 105 is continuously etched until the surface of the cutting layer 130 and the surface of the initial substrate 100 are exposed, so as to form a first protection layer 106 .

[0121] In this embodiment, the process of etching the first protective material layer 105 includes a wet etching process or a dry etching process.

[0122] In this embodiment, after the first mask structure 141 is formed, the first sidewall spacer 152 is removed.

[0123] Please refer to Fig.19 and Fig. 20 , Fig.19 is Fig.17 The top view structural diagram of the basis, Fig. 20 is along Fig.19 The schematic diagram of the cross-sectional structure along the X-X1 direction shows that the cutting layer 130 and the initial substrate 100 are etched with the first mask structure 141 as a mask until a substrate 101, a plurality of first fin structures 102 located on the substrate 101, and a plurality of first pseudo-fin structures 131 located on the substrate 101 are formed, wherein the first fin structures 102 are separated from each other and located in the effective area A, and the first pseudo-fin structures 131 are located in the invalid area B.

[0124] The process of etching the cutting layer 130 and the initial substrate 100 includes a dry etching process or a wet etching process.

[0125] In this embodiment, the process of etching the cutting layer 130 and the initial substrate 100 is a plasma etching process, and the gas used in the plasma etching process includes: C x F y , C x H y F z , C x H y , H 2 , Cl 2 , HBr, Ar and He, or a combination of one or more thereof.

[0126] In this embodiment, in the etching process for etching the cutting layer 130 and the initial substrate 100 , the etching selectivity ratio between the material of the cutting layer 130 and the material of the first mask structure 141 is greater than 3:1.

[0127] In this embodiment, after the first fin structure 102 and the first dummy fin structure 131 are formed, the first mask structure 141 is removed.

[0128] Please refer to Fig.21 and Fig. 22 , Fig.21 is Fig.19 The top view structural diagram of the basis, Fig. 22 is along Fig.21 The schematic diagram of the cross-sectional structure along the X-X1 direction shows that after the first fin structure 102 and the first dummy fin structure 131 are formed, some of the first dummy fin structures 131 are removed.

[0129] Since the initial substrate 100 includes a plurality of invalid regions B and an effective region A surrounding the invalid regions B, and a first fin structure 102 that is separate from each other and located in the effective region A and a first dummy fin structure 131 located in the invalid region B are formed, that is, since the first dummy fin structure 131 is connected to the first fin structure 102 in the extension direction of the first fin structure 102, and after the first fin structure 102 and the first dummy fin structure 131 are formed, a plurality of the first dummy fin structures 131 are removed, therefore, in the extension direction of the first fin structure 102, the first fin structures 102 on both sides of the invalid region B can be separated by the first dummy fin structure 131, thereby forming a first fin structure 102 with a shorter length to improve the integration of the semiconductor structure.

[0130] Moreover, when removing several of the first pseudo-fin structures 131, the material of the cutting layer 130 can be selected, that is, the material of the first pseudo-fin structure 131 can be selected to increase the etching process for removing the first pseudo-fin structure 131, and the etching selectivity ratio of the first fin structure 102 material and the first pseudo-fin structure 131 material can be reduced, thereby reducing the damage to the surface of the first fin structure 102 caused by the etching process, so as to improve the graphic accuracy of the first fin structure 102, and reduce the residual contamination of the first pseudo-fin structure 102 during the etching process, so as to reduce the defects of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0131] In this embodiment, the process of removing the first dummy fin structure 131 includes an etching process, and the etching process includes a wet etching process or a plasma etching process.

[0132] In this embodiment, in the etching process for removing the first dummy fin structure 131 , the etching selectivity ratio between the material of the first dummy fin structure 131 and the material of the substrate 101 is greater than 5:1.

[0133] In this embodiment, after removing the first dummy fin structure 131 , a dielectric layer 170 is formed on the surface of the substrate 101 .

[0134] The dielectric layer 170 is used to electrically insulate the semiconductor devices from each other.

[0135] In this embodiment, the method of forming the dielectric layer 170 includes: forming a dielectric material layer (not shown) on the surface of the substrate 101 and the surface of the first fin structure 102; and etching back the dielectric material layer until a portion of the sidewall surface of the first fin structure 102 is exposed.

[0136] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing an initial substrate, wherein the initial substrate comprises a plurality of ineffective regions and an effective region surrounding the ineffective regions; forming a cutting layer in the initial substrate of the ineffective region, wherein the surface of the cutting layer is exposed on the surface of the initial substrate; forming a plurality of first mask structures on the surfaces of the ineffective area and the effective area, wherein at least one first mask structure spans across the cutting layer; Using the first mask structure as a mask, etching the cutting layer and the initial substrate until a substrate, a plurality of first fin structures located on the substrate, and a plurality of first dummy fin structures located on the substrate are formed, wherein the first fin structures are separated from each other and located in the effective area, and the first dummy fin structures are located in the ineffective area; After forming the first fin structure and the first dummy fin structure, some of the first dummy fin structures are removed.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the cutting layer includes: forming a second mask structure on the initial substrate surface, wherein the second mask structure exposes the initial substrate surface of the ineffective area.

3. The method for forming a semiconductor structure according to claim 2, wherein: The second mask structure includes a second mask layer; The method for forming the second mask layer includes: forming a second mask material layer on the surface of the effective area and the ineffective area; forming a second photoresist layer on the surface of the second mask material layer, the second photoresist layer exposing the surface of the second mask material layer on the ineffective area; using the second photoresist layer as a mask, etching the second mask material layer until the initial substrate surface is exposed.

4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the second mask layer includes spin-on carbon.

5. The method for forming a semiconductor structure according to claim 3, wherein: The second mask structure further includes a second hard mask layer, and the second mask layer is located on the surface of the second hard mask layer; The method for forming the second hard mask layer comprises: before forming the second mask material layer, forming a second hard mask material layer on the surfaces of the effective area and the ineffective area; After etching the second mask material layer, the second hard mask material layer is continuously etched until the initial substrate surface is exposed.

6. The method for forming a semiconductor structure according to claim 5, wherein: The material of the second hard mask layer includes one or more combinations of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon or silicon nitride.

7. The method for forming a semiconductor structure according to claim 3, wherein: Also includes: Before forming the second photoresist layer, an anti-reflection layer is formed on the surface of the second mask material layer.

8. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the cutting layer further includes: etching the initial substrate using the second mask structure as a mask to form a first opening in the ineffective area; and forming the cutting layer in the first opening.

9. The method for forming a semiconductor structure according to claim 8, wherein: In the etching process for forming the first opening, the etching selectivity ratio of the material of the initial substrate and the material of the second mask layer is greater than 5:

1.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the cutting layer in the first opening includes: forming a cutting material layer on the surface of the initial substrate and in the first opening, the process of forming the cutting material layer including one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or an epitaxial growth process; and flattening the cutting material layer until the initial substrate surface is exposed.

11. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the cutting layer further includes: using the second mask structure as a mask to perform an ion doping process on the initial substrate of the ineffective area.

12. The method for forming a semiconductor structure according to claim 11, wherein: The ion doping process includes an ion implantation process.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process parameters of the ion implantation process include: the implantation dose range is 1.0e16atom / cm 3 ~1.0e20atom / cm 3 ; The injection energy range is 10KeV~200KeV.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the cutting layer includes one or more combinations of silicon nitride, silicon oxide, silicon germanium and silicon phosphide.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first mask structure includes one or more of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon nitride.

16. The method for forming a semiconductor structure according to claim 1, wherein: In the etching process for etching the cutting layer and the initial substrate, the etching selectivity ratio of the material of the cutting layer to the material of the first mask structure is greater than 3:

1.

17. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the first mask structures includes a multiple self-aligned patterning process.

18. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming a plurality of the first mask structures comprises: forming a first mask material layer on the surface of the initial substrate in the effective area and the cutting layer in the invalid area; forming a plurality of mutually discrete first core mold structures on the surface of the first mask material layer; forming a first side wall on the side wall surface of each of the first core mold structures; and etching the first mask material layer using the first side wall as a mask until the cutting layer surface and the initial substrate surface are exposed.

19. The method for forming a semiconductor structure according to claim 18, wherein: The method for forming the first sidewall includes: forming a first sidewall material layer on the surface of the first mask material layer and the surface of the first core mold structure; etching back the first sidewall material layer until the surface of the first mask material layer and the top surface of the first core mold structure are exposed.

20. The method for forming a semiconductor structure according to claim 18, wherein: The method for forming the first core mold structure includes: forming a first core mold material layer on the surface of the first mask material layer; forming a first photoresist layer on the surface of the first core mold material layer, the first photoresist layer exposing a portion of the surface of the first core mold material layer; using the first photoresist layer as a mask, etching the first core mold material layer until the surface of the first mask material layer is exposed.

21. The method for forming a semiconductor structure according to claim 18, wherein: The method for forming the first core mold structure includes: forming a first core mold material layer on the surface of the first mask material layer; forming a plurality of mutually discrete second core mold structures on the surface of the first core mold material layer; forming a second side wall on the side wall surface of the second core mold structure; and etching the first core mold material layer using the second side wall as a mask until the surface of the first mask material layer is exposed.

22. The method for forming a semiconductor structure according to claim 18, wherein: The material of the first core mold structure includes one or more combinations of amorphous silicon, silicon nitride, silicon oxide, amorphous carbon and photoresist.

23. The method for forming a semiconductor structure according to claim 18, wherein: The material of the first spacer includes: one or more combinations of silicon oxide, silicon nitride, silicon and titanium oxide.

24. The method for forming a semiconductor structure according to claim 18, wherein: Also includes: Before forming the first mask material layer, forming a first protective material layer on the surface of the initial substrate in the effective area and the cutting layer in the ineffective area; After etching the first mask material layer, the first protection material layer is continuously etched until the surface of the cutting layer and the surface of the initial substrate are exposed to form a first protection layer.

25. The method for forming a semiconductor structure according to claim 24, wherein: The material of the first protection layer includes silicon oxide.

26. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first dummy fin structure includes an etching process, in which an etching selectivity ratio between a material of the first dummy fin structure and a material of the substrate is greater than 5:1.

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