A capacitor array structure, a manufacturing method thereof and a semiconductor memory device

Abstract

The present application discloses a method for manufacturing a capacitor array structure, including: providing a substrate, and forming an alternately stacked sacrificial layer and a supporting layer on the substrate; forming a capacitor hole on the structure covering the substrate; forming a capacitor unit structure in the capacitor hole; introducing a silicon source gas after forming the capacitor unit structure in the capacitor hole to form a seed particle size on the surface of the capacitor unit structure; introducing a silicon source gas, a boron source gas, and a germanium source gas by doubling or multiple times the special gas to react to form a multi-seed particle size, and the multi-seed particle size diffuses into a film in the capacitor hole to form a conductive filling structure. By doubling or multiple times the special gas to keep the concentration of the multi-seed particle size diffused into the film in the capacitor hole unchanged, the gas flow rate introduced can be doubled, so that the formed conductive filling structure fills the capacitor hole more densely and evenly, thereby achieving the effect of reducing leakage and strengthening the capacitor array structure.

Description

Technical Field

[0001] The present application relates to but is not limited to the technical field of semiconductors, and in particular to a capacitor array structure, a manufacturing method thereof, and a semiconductor memory device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeated storage cells. Each storage cell usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage. At present, in the DRAM process below 20nm, DRAM uses a stacked capacitor structure, and its capacitor is a vertical cylindrical shape with a high aspect ratio to increase the surface area.

[0003] When the traditional method is used to fill the capacitor structure, due to the high aspect ratio structure of the capacitor (height: 1000-2000nm, CD: 30-60nm), when the traditional method is used to fill the capacitor structure, premature sealing will occur, resulting in gaps in the capacitor structure and causing an increase in leakage current. Summary of the invention

[0004] The purpose of the present application is to provide a capacitor array structure, a manufacturing method thereof and a semiconductor memory device, in order to solve the problem in the prior art that when the capacitor holes are filled using the traditional method, due to the high aspect ratio structure of the capacitor (height: 1000-2000nm, CD: 30-60nm), premature sealing will occur during filling, resulting in gaps in the capacitor structure, thereby causing an increase in leakage current.

[0005] To solve the above technical problems, according to some embodiments, the present application provides a method for manufacturing a capacitor array structure, including: providing a substrate, and forming alternatingly stacked sacrificial layers and supporting layers on the substrate; forming a capacitor hole on the structure covering the substrate; forming a capacitor unit structure in the capacitor hole; after the capacitor unit structure is formed in the capacitor hole, introducing a silicon source gas to form a seed particle size on the surface of the capacitor unit structure; introducing a silicon source gas, a boron source gas, and a germanium source gas in a double or multiple manner to react to form a multi-seed particle size, and the multi-seed particle size diffuses into a film in the capacitor hole to form a conductive filling structure.

[0006] Preferably, forming a capacitor unit structure on the inner wall of the capacitor hole includes: forming a first electrode layer on the inner wall of the capacitor hole; forming at least one opening on the supporting layer on the alternatingly stacked sacrificial layer and supporting layer to open the supporting layer, and removing the sacrificial layer based on the opening; forming a dielectric layer on the surface of the structure obtained by removing the sacrificial layer, and forming a second electrode layer on the surface of the dielectric layer.

[0007] Preferably, one of the openings is formed to overlap with only one of the capacitor holes, or one opening is formed to overlap with a plurality of the capacitor holes at the same time.

[0008] Preferably, an etch stop layer is formed on the surface of the substrate, and the alternately stacked sacrificial layers and supporting layers are formed on the surface of the etch stop layer.

[0009] Preferably, the germanium source gas comprises GeH 4 Or Ge 2 H 6 At least one of the above, wherein the silicon source gas comprises SiH 4 、Si 2 H 6 or SiH 6 Cl, the boron source gas comprises BCl 3 or B 2 H 6 At least one of .

[0010] Preferably, after forming the capacitor unit structure in the capacitor hole, introducing the silicon source gas to form the seed crystal particle size on the surface of the capacitor unit structure comprises: the introduced silicon source gas reacts for 10 to 30 minutes under the first reaction condition, wherein SiH 4 The gas flow rate is: 200 standard milliliters per minute to 300 standard milliliters per minute.

[0011] Preferably, the introduced silicon source gas reacts for 10 to 30 minutes under the first reaction conditions including: a reaction temperature of 360° C. to 410° C. and a reaction pressure of less than 1 Torr.

[0012] Preferably, the method of introducing silicon source gas, boron source gas and germanium source gas in a double or multiple manner to react to form multiple seed crystals comprises: the introduced silicon source gas, boron source gas and germanium source gas react for 10 to 40 minutes under the second reaction condition, wherein SiH 4 Gas flow rate: 300 standard ml / min-700 standard ml / min, GeH 4 Gas flow rate: 850 standard ml / min-1300 standard ml / min, BCL 3 The gas flow rate is: 50 standard ml / min-200 standard ml / min.

[0013] Preferably, the introduced silicon source gas, boron source gas, and germanium source gas react for 10 to 40 minutes under the second reaction conditions including: a reaction temperature of 360° C. to 410° C. and a reaction pressure of 1 to 3 Torr.

[0014] Preferably, a protective layer is formed on the surface of the conductive filling structure, wherein the material of the protective layer comprises polysilicon doped with boron or germanium.

[0015] Preferably, the conductive filling structure and the protective layer are prepared in the same reaction chamber, and the germanium source gas for forming the protective layer includes GeH 4 Or Ge 2 H 6 At least one of the above, wherein the silicon source gas comprises SiH 4 、Si 2 H 6 or SiH 6 Cl, the boron source gas comprises BCl 3 or B 2 H 6 At least one of .

[0016] Preferably, forming a protective layer on the surface of the conductive filling structure comprises: reacting at a temperature of 410°C to 460°C for 3 to 4 hours, wherein SiH 4 Gas flow rate: 300 standard ml / min-700 standard ml / min, GeH 4 Gas flow rate: 1250 standard ml / min - 1800 standard ml / min, BCL 3 The gas flow rate is 50 standard ml / min-200 standard ml / min, and the reaction pressure is less than 1 Torr.

[0017] According to some other embodiments, the present application also provides a capacitor array structure, including: a substrate, on which alternatingly stacked sacrificial layers and supporting layers are arranged; a capacitor hole, which is opened on a structure covering the substrate; a capacitor unit structure, which is formed on the inner wall of the capacitor hole; and a conductive filling structure, which is filled on the surface of the capacitor unit structure, and which uses a special gas to double or multiple times introduce silicon source gas, boron source gas, and germanium source gas to form multiple seed particles in the capacitor hole, and the multiple seed particles are diffused into a film in the capacitor hole.

[0018] Preferably, the method further comprises: an etch stop layer, wherein the etch stop layer covers the substrate, and the alternately stacked sacrificial layers and supporting layers are formed on the surface of the etch stop layer.

[0019] Preferably, it further comprises: a protective layer covering the surface of the conductive filling structure.

[0020] According to some other embodiments, the present application further provides a semiconductor memory device, which includes the capacitor array structure.

[0021] The embodiments of the present disclosure have at least the following advantages: the seed crystal particle size formed by the silicon source gas on the surface of the capacitor unit structure is suppressed from growing under low temperature conditions, and in the process of filling the capacitor hole, uniformity and density can be achieved, and the problem of premature sealing will not occur, so that the subsequent germanium-doped polysilicon can be smoothly filled into the capacitor hole in an environment that is not easy to seal; then, the silicon source gas, boron source gas and germanium source gas are introduced in a double or multiple manner to react to form a multi-seed crystal particle size, so that the germanium-doped polysilicon reactant can be better diffused into the extremely small holes in the capacitor hole, thereby achieving perfect filling of the inside of the capacitor hole, thereby achieving the effect of reducing leakage and strengthening the capacitor array structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A flow chart of a method for manufacturing a capacitor array structure provided in one embodiment of the present application;

[0024] Figure 2A-2L A schematic cross-sectional structure diagram corresponding to each step in a method for manufacturing a capacitor array structure provided in an embodiment of the present application;

[0025] Figure 3A This is a flow chart of a method for manufacturing a conductive filling structure in one embodiment of the present application;

[0026] Figure 3B-Figure 3D Schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a conductive filling structure in one embodiment of the present application. DETAILED DESCRIPTION

[0027] When the traditional method is used to fill the capacitor structure, due to the high aspect ratio structure of the capacitor (height: 1000-2000nm, CD: 30-60nm), the capacitor structure will be sealed prematurely, resulting in gaps in the capacitor structure and an increase in leakage current.

[0028] To solve the above problems, an embodiment of the present application provides a method for manufacturing a capacitor array structure, including: providing a substrate, and forming alternatingly stacked sacrificial layers and supporting layers on the substrate; forming a capacitor hole on the structure covering the substrate; forming a capacitor unit structure in the capacitor hole; after the capacitor unit structure is formed in the capacitor hole, introducing a silicon source gas to form a seed particle size on the surface of the capacitor unit structure; introducing a silicon source gas, a boron source gas, and a germanium source gas in a double or multiple manner to react to form a multi-seed particle size, and the multi-seed particle size diffuses into a film in the capacitor hole to form a conductive filling structure.

[0029] Silicon source gas, boron source gas and germanium source gas are introduced in a double or multiple manner to react and form multiple seed particles, so that the germanium-doped polysilicon reactant can be better diffused into the tiny holes in the capacitor hole, thereby achieving perfect filling of the capacitor hole.

[0030] The capacitor unit structure formed therein is a ring-shaped capacitor or a columnar capacitor. The ring-shaped capacitor (Cylinder, also called a double-sided capacitor, has two capacitors: inner and outer). The technical solutions of the present application are all carried out after the capacitor structure of the ring-shaped capacitor or the columnar capacitor is formed. This embodiment is described in detail using the ring-shaped capacitor as an example.

[0031] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined with each other and quoted from each other without contradiction.

[0032] Figure 1 A flow chart of a method for manufacturing a capacitor array structure provided in one embodiment of the present application; Figure 2A-2L A schematic diagram of a cross-sectional structure corresponding to each step in a method for manufacturing a capacitor array structure provided in an embodiment of the present application. The following is a further detailed description of a method for manufacturing a capacitor array structure provided in this embodiment in conjunction with the accompanying drawings, and the specific steps are as follows:

[0033] Step S11, providing a substrate, and forming alternately stacked sacrificial layers and supporting layers on the substrate.

[0034] Please refer to Figure 1 and Figure 2AAs shown, the details may include, forming an etch stop layer 102 covering the substrate 101, a first sacrificial layer 103, a first supporting layer 104, a second sacrificial layer 105 and a second supporting layer 106 in sequence on the substrate 101, wherein the thickness of the first sacrificial layer 103 is greater than the thickness of the second sacrificial layer 105, and the thickness of the second supporting layer 106 is greater than the thickness of the first supporting layer 104.

[0035] In one example, the materials of the sacrificial layer and the supporting layer may be the same or different. In the embodiment of the present application, the material of the sacrificial layer and the material of the supporting layer are different as an example. In the same etching process, the etching rate of the sacrificial layer is much greater than the etching rate of the supporting layer, so that when the sacrificial layer is completely removed, the supporting layer is almost completely retained, thereby playing a supporting role.

[0036] In another example, the material of the sacrificial layer includes silicon oxide or silicon oxynitride or a polysilicon layer, and the material of the supporting layer includes any one or a combination of any two or more of silicon nitride, silicon oxynitride or aluminum oxide. In the embodiment of the present application, the material of the sacrificial layer is SiO 2 , the material of the supporting layer is SiN.

[0037] In some embodiments, various methods for forming the support layer and the sacrificial layer may be formed by, for example, an atomic layer deposition process (Atomic Layer Deposition) or a plasma enhanced chemical vapor deposition process (Plasma Enhanced Chemical Vapor Deposition) as is well known in the art.

[0038] In this embodiment, it should be noted that the etch stop layer 102 can be used as an insulating layer to protect and isolate other circuits. Preferably, the etch stop layer 102 is formed by an atomic layer deposition process (Atomic Layer Deposition) or a low pressure chemical vapor deposition process (Low Pressure Chemical Vapor Deposition), and the thickness is preferably between 15nm and 35nm.

[0039] In some embodiments, the material of the substrate 101 may include a semiconductor substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a single crystal metal oxide substrate, etc. In this embodiment, the substrate 101 is made of silicon material. This embodiment uses silicon material as the substrate 101 to facilitate the understanding of subsequent formation methods by those skilled in the art, and does not constitute a limitation. In actual application, a suitable substrate material can be selected according to requirements.

[0040] Step S12: forming a patterned mask layer on the structure obtained in step S11, and etching the sacrificial layer and the supporting layer based on the patterned mask layer to form capacitor holes.

[0041] Please refer to Figure 1 and Figure 2B As shown, the details may include coating a photoresist layer on the surface area of ​​the formed second support layer 106. In other embodiments, other mask layers (such as silicon nitride hard mask layers, etc.) may also be formed, and the mask layer is patterned by a photolithography process to sequentially form a patterned first mask layer 107 and a patterned second mask layer 108 on the surface area of ​​the second support layer 106. In this embodiment, it should be noted that the structure covering the substrate 101 is etched by an etching process using the formed first mask layer 107 and the second mask layer 108 as masks until the etching stop layer 102 is exposed, and the first mask layer 107 and the second mask layer 108 are removed to form a capacitor hole 109, as shown in FIG. Figure 2C shown. Figure 2D is a top view of a capacitor after etching in the related art, and the arrangement of the capacitor holes 109 is as follows Figure 2D shown.

[0042] Step S13, after forming the capacitor hole, depositing titanium nitride on the inner wall of the capacitor hole to form a first electrode layer.

[0043] Please refer to Figure 1 , Figure 2C and Figure 2E As shown, the details may include, using an atomic layer deposition process (Atomic Layer Deposition) or a plasma chemical vapor deposition process (Chemical Vapor Deposition) to deposit a lower electrode material layer on the sidewall and bottom of the capacitor hole 109 and the upper surface of the second support layer 106, the lower electrode material layer includes a compound formed by one or two of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide) and titanium silicon nitride (TiSixNy), preferably, in this embodiment, the material of the lower electrode material layer is titanium nitride for example. After the lower electrode material layer is formed, a chemical mechanical grinding or etching process is used to remove the lower electrode material layer located on the upper surface of the second support layer 106, and the lower electrode material layer located on the sidewall and bottom of the capacitor hole 109 is retained as the first electrode layer 110 (refer to 2E).

[0044] Step S14, forming a patterned third mask layer having openings on the surface area of ​​the second supporting layer, and etching the second supporting layer based on the third mask layer to form a first opening on the second supporting layer.

[0045] Please refer to the detailed information. Figure 1 and Figure 2F A patterned third mask layer 111 having an opening is formed in the surface area of ​​the second supporting layer 106, wherein the opening defines the position and shape of the first opening on the second supporting layer 106, and the second supporting layer 106 is etched based on the third mask layer 111 to form a first opening 112 on the second supporting layer 106 (refer to 2G), and the bottom of the first opening 112 exposes the top area of ​​the second sacrificial layer 105.

[0046] Optionally, as an example, the first openings 112 formed in step S14 are arranged at even intervals, and one first opening 112 overlaps only one capacitor hole 109, or one first opening 112 overlaps multiple capacitor holes 109 at the same time, such as Figure 2H As shown, one first opening 112 overlaps three capacitor holes 109 as an example. Figure 2H is a top view of the second support layer 106 having the first opening 112. The positional relationship between the first opening 112 and the capacitor hole 109 is shown in FIG. Figure 2H Please continue to refer to Figure 1 and Fig.2I According to the first opening 112, the second sacrificial layer 105 between the first supporting layer 104 and the second supporting layer 106 is removed by a wet etching process. The second supporting layer 106 with the first opening 112 formed by this method has a suitable opening position, which is conducive to the wet etching of the sacrificial layer and can ensure sufficient supporting strength.

[0047] Step S15 , forming a second opening on the first supporting layer based on the first opening, and removing the first sacrificial layer.

[0048] Please refer to Figure 1 and Fig.2I As shown, the details may include forming a second opening 113 on the first support layer 104 based on the first opening 112, such as Fig.2I As shown in the dashed box, Figure 2J is a cross-sectional view of the first support layer having the second opening, and the positional relationship between the second opening 113 and the capacitor hole 109 is shown in FIG. Figure 2J According to the second opening 113 , the first sacrificial layer 103 between the etch stop layer 102 and the first support layer 104 is removed by a wet etching process.

[0049] Step S16, forming a dielectric layer on the surface of the structure obtained in step S15, and forming a second electrode layer on the surface of the dielectric layer.

[0050] Details may include, please continue to refer to Figure 1 and Figure 2KAs shown, a dielectric layer 114 is formed on the inner and outer surfaces of the first electrode layer 110 on the inner wall of the capacitor hole 109 and on the surfaces of the first support layer 104 and the second support layer 106, wherein the dielectric layer 114 is selected from strontium titanate (SrTiO 3 ) and titanium oxide (TiO 2 ) composed of a laminated structure, aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO) and a composite perovskite-type ferroelectric material (BST material, a composite perovskite-structured iron electrode material, is composed of BaTiO 3 and SrTiO 3 One of the solid solutions composed in a certain proportion.

[0051] A second electrode layer 115 is formed on the surface of the dielectric layer 114. In some embodiments, the dielectric layer 114 and the second electrode layer 115 are formed by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. The material of the second electrode layer 115 includes a compound formed by one or both of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy). The metal electrode material may also be a conductive material such as Ru (ruthenium), Pt (platinum), Ir (iridium), Pd (palladium), or even a metal oxide such as RuO 2 (Ruthenium oxide), IrO 2 (iridium oxide), etc.

[0052] Step S17 , forming a conductive filling structure on the surface of the second electrode layer, wherein the conductive filling structure fills the gap between adjacent second electrode layers and is electrically connected to the second electrode layer.

[0053] like Figure 2L As shown, the details may include forming a conductive filling structure in the gap between adjacent second electrode layers 115 and on the second electrode layer 115 .

[0054] Figure 3A This is a flow chart of a method for manufacturing a conductive filling structure in one embodiment of the present application; Figure 3B-Figure 3D This is a schematic diagram of the cross-sectional structure corresponding to each step in the manufacturing method of the conductive filling structure in one embodiment of the present application. The manufacturing of the conductive filling structure specifically includes the following steps:

[0055] Step S171, forming seed particles in the capacitor hole under a first reaction condition.

[0056] like Figure 3A , Figure 3B As shown: In detail, the conductive filling structure obtained in step S17 is placed in a chemical vapor deposition furnace tube, and a silicon source gas is introduced into the chemical vapor deposition furnace tube, and the silicon source gas reacts for 10 to 30 minutes under the first reaction condition to form a seed particle size 117 on the outer surface of the second electrode layer 115 in the capacitor hole 109. The silicon source gas introduced includes SiH 4 、Si 2 H 6 or SiH 6 At least one of Cl, in the embodiment of the present application, the silicon source gas is SiH 4 For example, in one example, the first reaction condition specifically includes: the temperature is set to 360°C to 410°C, the reaction pressure is controlled to be less than 1 torr, wherein SiH 4 The gas flow rate is: 200 standard milliliters per minute to 300 standard milliliters per minute.

[0057] In the embodiment of the present application, silicon source gas is introduced during the process of filling the capacitor hole 109. The silicon source gas forms seed particles 117 on the outer surface of the second electrode layer 115 under the first reaction condition. By lowering the temperature in the first reaction condition to between 360°C and 410°C, the formed seed particles 117 are suppressed from growing in the capacitor hole 109 at a relatively low temperature. Thus, in the process of filling the capacitor hole 109, uniformity and density can be achieved without the problem of premature sealing, so that the subsequent germanium-doped polysilicon can be smoothly filled into the capacitor hole 109 in an environment where sealing is not easy.

[0058] In other embodiments, the formed seed crystal grains 117 are also located on the upper surface of the second supporting layer 106 around the capacitor hole 109 .

[0059] Step S172 , the multi-crystal seed particles diffuse into a film in the capacitor hole under a second reaction condition to form a conductive filling structure.

[0060] like Figure 3A and 3C As shown, in detail, the conductive filling structure includes a filling conductive layer 116 , and the filling conductive layer 116 fills the hole of the capacitor hole 109 and also extends to cover the upper surface of the second supporting layer 106 around the capacitor hole 109 .

[0061] In some embodiments, silicon source gas, boron source gas and germanium source gas are introduced into the chemical vapor deposition furnace tube by doubling or multiple times of special gas to react for 10 to 40 minutes under the second reaction condition to form multiple seed particles in the capacitor hole 109 and diffuse into a film to form the filled conductive layer 116. By doubling or multiple times of special gas while keeping the concentration of the multiple seed particles diffused into the film in the capacitor hole 109 unchanged, the gas flow rate introduced can be doubled, thereby achieving high pressure conditions for the chemical vapor deposition furnace tube machine.

[0062] The silicon source gas introduced includes SiH 4 、Si 2 H 6 or SiH 6 At least one of Cl, the germanium source gas includes GeH 4 ,Ge 2 H 6 At least one of the boron source gas comprises BCl 3 , B 2 H 6 In this embodiment, the silicon source gas is SiH 4 , Germanium source gas is GeH 4 , boron source gas is BCl 3 In this application, a boron-doped germanium silicon layer is used as the filling conductive layer 116 , and germanium is contained in the filling conductive layer 116 . Germanium can increase the carrier mobility, thereby reducing the resistance value of the filling conductive layer 116 .

[0063] The silicon source gas, the boron source gas and the germanium source gas are introduced into the reaction chamber in a double or multiple manner to react for 10 to 40 minutes under the second reaction conditions, wherein the second reaction conditions specifically include: a temperature of 360° C. to 410° C., a reaction pressure of 1 to 3 torr, wherein SiH 4 Gas flow rate: 300 standard ml / min-700 standard ml / min, GeH 4 Gas flow rate: 850 standard ml / min-1300 standard ml / min, BCl 3 The gas flow rate is 50 standard ml / min-200 standard ml / min. 4 The gas flow rate is: 850 standard ml / min-1300 standard ml / min, low concentration GeH 4 The film can be formed with a smaller crystal grain size in the capacitor hole 109, and the film can be denser when filling the capacitor hole 109.

[0064] In the embodiment of the present application, silicon source gas, boron source gas and germanium source gas are introduced simultaneously to react under the second reaction condition, and the reaction temperature of 360°C to 410°C in the second reaction condition is controlled to remain unchanged with the reaction temperature of 360°C to 410°C in the first reaction condition, and the reaction pressure is increased to between 1 and 3 torr, so that the germanium-doped polysilicon reactant can be better diffused into the extremely small holes in the capacitor hole 109, thereby achieving perfect filling of the inside of the capacitor hole 109, thereby achieving the effect of reducing leakage and strengthening the capacitor array structure.

[0065] Step S173, forming a protective layer on the surface of the filled conductive layer under a third reaction condition.

[0066] like Figure 3A and Figure 3D As shown, the details may include that the formed protective layer 118 is used to prevent the germanium in the filling conductive layer 116 from affecting the subsequent process, and the material of the protective layer 118 includes polysilicon doped with boron and germanium, wherein the protective layer 118 and the filling conductive layer 116 are prepared in the same reaction chamber, and the germanium source gas for forming the protective layer 118 includes GeH 4 Or Ge 2 H 6 At least one of the silicon source gas comprises SiH 4 、Si 2 H 6 or SiH 6 At least one of Cl, the boron source gas includes BCl 3 or B 2 H 6 In the present embodiment, the germanium source gas is GeH 4 、Silicon source gas is SiH 4 and the boron source gas is BCl 3 As an example, the third reaction condition includes reacting at a temperature of 410°C to 460°C for 3 to 4 hours and a reaction pressure of less than 1 Torr, wherein SiH 4 Gas flow rate: 300 standard ml / min-700 standard ml / min, GeH 4 Gas flow rate: 1250 standard ml / min - 1800 standard ml / min, BCl 3 The gas flow rate is 50 standard ml / min-200 standard ml / min. In this step, the GeH 4 The gas flow rate becomes: 1250 standard ml / min-1800 standard ml / min, GeH 4 The germanium in the conductive layer 116 can increase the carrier mobility, thereby reducing the resistance of the conductive layer 116, thereby increasing the amount of GeH 4 The flow rate of the gas can reduce the resistance of the formed capacitor.

[0067] Embodiment 2

[0068] Please continue to refer to Example 1. Figure 2L , the embodiment of the present application also provides a capacitor array structure, the capacitor array structure is manufactured by the manufacturing method described in the first embodiment, the capacitor array structure is arranged on a substrate 101, and alternately stacked sacrificial layers and supporting layers are arranged on the substrate 101; wherein the sacrificial layer includes a first sacrificial layer 103 and a second sacrificial layer 105, and the supporting layer includes a first supporting layer 104 and a second supporting layer 106; the first sacrificial layer 103, the first supporting layer 104, the second sacrificial layer 105 and the second supporting layer 106 are sequentially stacked on the substrate 101. An etch stop layer 102 is also formed between the first sacrificial layer 103 and the substrate 101, and the etch stop layer 102 can be used as an insulating layer to protect and isolate other circuits.

[0069] The capacitor hole 109 is opened in the first sacrificial layer 103, the first supporting layer 104, the second sacrificial layer 105 and the second supporting layer 106 and exposes the etching stop layer 102;

[0070] The capacitor array structure includes a first electrode layer 110 , which is deposited on the inner wall of the capacitor hole 109 ; a dielectric layer 114 , which covers the surface of the first electrode layer 110 ; and a second electrode layer 115 , which covers the surface of the dielectric layer 114 .

[0071] The conductive filling structure includes a filling conductive layer 116, which covers the outer surface of the second electrode layer 115 and fills the gap between adjacent second electrode layers 115, and is electrically connected to the second electrode layer 115. The material of the filling conductive layer 116 includes a boron-doped silicon germanium layer (B-doped SiGe). The filling conductive layer 116 is formed by forming a multi-seed particle size in the capacitor hole 109 by doubling or multiplying the special gas, and then diffused into a film to fill the surface of the capacitor unit structure.

[0072] As an example, the capacitor array structure further includes a protective layer 118, and the protective layer 118 covers the surface of the filling conductive layer 116. Optionally, the material of the protective layer 118 includes polysilicon doped with boron or germanium. As an example, the dielectric layer 114 is a high-K dielectric layer to increase the capacitance value of the capacitor per unit area, which includes strontium titanate (SrTiO 3 ) and titanium oxide (TiO 2 ) and a stacked structure composed of aluminum oxide (AlO) and hafnium oxide (HfO).

[0073] Embodiment 3

[0074] Accordingly, the embodiment of the present application further provides a semiconductor memory device structure, which includes the capacitor array structure as described in Embodiment 2. As an example, the semiconductor memory device structure may be, but is not limited to, a dynamic random access memory (DRAM).

[0075] To sum up, in the embodiments of the present disclosure, under the condition of a reaction temperature of 360°C to 410°C, the seed particle size formed on the surface of the conductive layer by the silicon source gas introduced is suppressed from growing. In the process of filling the capacitor holes, uniformity and density can be achieved, and the problem of premature sealing will not occur, so that the subsequent germanium-doped polycrystalline silicon can be smoothly filled into the capacitor holes in an environment where sealing is not easy; then, under a reaction pressure of 1 to 3 torr, silicon source gas, boron source gas and germanium source gas are introduced simultaneously in a doubling or multiple manner of special gas to react under high pressure conditions, and the parameters in the second reaction condition are controlled so that the germanium-doped polycrystalline silicon reactant can be better diffused into the extremely small holes in the capacitor holes, thereby achieving perfect filling of the inside of the capacitor holes, thereby achieving the effect of reducing leakage and strengthening the capacitor array structure.

[0076] It should be understood that the above specific embodiments of the present application are only used to illustrate or explain the principles of the present application, and do not constitute a limitation to the present application. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present application should be included in the protection scope of the present application. In addition, the claims attached to the present application are intended to cover all changes and modifications that fall within the scope and boundaries of the attached claims, or the equivalent forms of such scope and boundaries.

Claims

1. A method for manufacturing a capacitor array structure, characterized in that: include: Providing a substrate, and forming alternately stacked sacrificial layers and supporting layers on the substrate; forming a capacitor hole on a structure covering the substrate; forming a capacitor unit structure in the capacitor hole; After forming a capacitor unit structure in the capacitor hole, a silicon source gas is introduced to form a seed particle size on the surface of the capacitor unit structure; Silicon source gas, boron source gas and germanium source gas are introduced in a double or multiple manner to react to form multiple seed particles, and the multiple seed particles diffuse into a film in the capacitor hole to form a conductive filling structure.

2. The manufacturing method according to claim 1, characterized in that Forming a capacitor unit structure in the capacitor hole includes: forming a first electrode layer on the inner wall of the capacitor hole; forming at least one opening on the supporting layer on the alternately stacked sacrificial layer and the supporting layer to open the supporting layer, and removing the sacrificial layer based on the opening; A dielectric layer is formed on the surface of the structure obtained by removing the sacrificial layer, and a second electrode layer is formed on the surface of the dielectric layer.

3. The manufacturing method according to claim 2, characterized in that: One of the openings is formed to overlap with only one of the capacitor holes, or one of the openings overlaps with a plurality of the capacitor holes at the same time.

4. The manufacturing method according to claim 2, characterized in that: An etch stop layer is formed on the surface of the substrate, and the alternately stacked sacrificial layers and supporting layers are formed on the surface of the etch stop layer.

5. The manufacturing method according to claim 1, characterized in that: The germanium source gas includes at least one of GeH4 or Ge2H6, the silicon source gas includes at least one of SiH4, Si2H6 or SiH6Cl, and the boron source gas includes at least one of BCl3 or B2H6.

6. The manufacturing method according to claim 5, characterized in that: After forming the capacitor unit structure in the capacitor hole, introducing the silicon source gas to form seed crystal particles on the surface of the capacitor unit structure includes: The introduced silicon source gas reacts for 10 to 30 minutes under the first reaction condition, wherein the flow rate of SiH4 gas is 200 to 300 standard ml / min.

7. The manufacturing method according to claim 6, characterized in that: The silicon source gas introduced is reacted for 10 to 30 minutes under the first reaction condition including: The reaction temperature is 360°C to 410°C, and the reaction pressure is less than 1 Torr.

8. The manufacturing method according to claim 7, characterized in that: The method of doubling or multiplying the special gas to introduce silicon source gas, boron source gas, and germanium source gas to react to form multiple seed crystal particle sizes includes: The introduced silicon source gas, boron source gas and germanium source gas react under the second reaction conditions for 10 to 40 minutes, wherein the flow rate of SiH4 gas is 300-700 standard ml / min, the flow rate of GeH4 gas is 850-1300 standard ml / min, and the flow rate of BCL3 gas is 50-200 standard ml / min.

9. The manufacturing method according to claim 8, characterized in that: The silicon source gas, boron source gas, and germanium source gas are reacted for 10 to 40 minutes under the second reaction conditions, including: The reaction temperature is 360°C to 410°C, and the reaction pressure is 1 to 3 Torr.

10. The manufacturing method according to claim 9, characterized in that: A protection layer is formed on the surface of the conductive filling structure, wherein the material of the protection layer includes polysilicon doped with boron or germanium.

11. The manufacturing method according to claim 10, characterized in that: The conductive filling structure and the protective layer are prepared in the same reaction chamber, the germanium source gas for forming the protective layer includes at least one of GeH4 or Ge2H6, the silicon source gas includes at least one of SiH4, Si2H6 or SiH6Cl, and the boron source gas includes at least one of BCl3 or B2H6.

12. The manufacturing method according to claim 11, characterized in that: Forming a protective layer on the surface of the conductive filling structure comprises: The reaction time is 3 to 4 hours at a reaction temperature of 410°C to 460°C, wherein the flow rate of SiH4 gas is 300 to 700 standard ml / min, the flow rate of GeH4 gas is 1250 to 1800 standard ml / min, and the flow rate of BCL3 gas is 50 to 200 standard ml / min, and the reaction pressure is less than 1 Torr.

13. A capacitor array structure manufactured by the method for manufacturing a capacitor array structure according to any one of claims 1 to 12, characterized in that: include: A substrate, on which sacrificial layers and supporting layers are alternately stacked; A capacitor hole is provided on the structure covering the substrate; A capacitor unit structure is formed in the capacitor hole; The conductive filling structure is filled on the surface of the capacitor unit structure. Silicon source gas, boron source gas and germanium source gas are introduced by doubling or multiple times the special gas to form multiple seed particles in the capacitor hole. The multiple seed particles diffuse into a film in the capacitor hole.

14. The array structure according to claim 13, characterized in that: Also includes: The etch stop layer covers the substrate, and the alternately stacked sacrificial layers and supporting layers are formed on the surface of the etch stop layer.

15. The array structure according to claim 14, characterized in that: Also includes: A protective layer covers the surface of the conductive filling structure.

16. A semiconductor memory device, characterized in that: The semiconductor memory device includes the capacitor array structure as claimed in claim 13.

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