A GaN HEMT device for improving linearity and a method for preparing the same

Abstract

The present invention discloses a GaN HEMT device for improving linearity and a preparation method thereof, the device comprising: a substrate layer; a GaN buffer layer, arranged on the substrate layer; a back-to-back barrier layer, arranged on the GaN buffer layer, the Al component in the back-to-back barrier layer increasing from x to y from top to bottom and then decreasing from y to 0; a source electrode and a drain electrode, the partial depths of the source electrode and the drain electrode being respectively located inside the two ends of the GaN buffer layer; a passivation layer, the passivation layer being arranged on the back-to-back barrier layer; and a gate electrode, the gate electrode being arranged on the back-to-back barrier layer in the gate electrode region. The new type of gradually changing barrier GaN HEMT device provided by the present invention has significantly improved transconductance flatness compared with conventional structures, and the linearity is improved. In addition, compared with a single gradually changing Al component barrier structure, the distribution of the electric field under the gate of the new structure is flatter. Therefore, this structure takes into account good frequency characteristics, breakdown characteristics and excellent linearity.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and the present invention relates to a GaN HEMT device for improving linearity and a preparation method thereof. Background Art

[0002] Since gallium nitride (GaN) materials have the characteristics of high mobility, high electron saturation velocity and high breakdown field strength, GaN-based devices represented by AlGaN / GaN HEMT (High Electron Mobility Transistor) have shown good development prospects in the field of high frequency and high power in recent years. However, as the operating frequency of the device continues to increase and the gate length continues to decrease, the inherent nonlinearity of the device becomes more and more serious, and the interference between signals caused by it will be detrimental to the application of GaN-based HEMTs in the millimeter wave frequency band.

[0003] At present, linearization technology for power amplifiers includes two methods: circuit level and device level. Circuit level linearization technology connects transistors under different biases in parallel so that the high-order derivatives of their transconductance cancel each other out to improve the linearity of the amplifier. However, the cost of multiple power supply biases is high power consumption, low integration, and high complexity. In contrast, device level linearization technology improves the nonlinear problem from the bottom up, reduces power consumption, and improves integration.

[0004] Based on the above, people have been exploring new device structures to improve the linearity of conventional AlGaN / GaN HEMT. In 2006, T. Palacios et al. proposed the AlGaN / GaN / AlGaN / GaN dual-channel structure, which uses the multi-threshold modulation effect brought by the two channels being turned on at different gate voltages to flatten the transconductance. At the same time, the source resistance Rs of the dual-channel device is less affected by the drain current than that of the single-channel device, and the maximum oscillation frequency f of the device is reduced. max It reached 40GHz, and the IMD (intermodulation distortion) was improved by 2dBc at 10GHz. Later, the researchers proposed to use a nanochannel structure, taking advantage of the fact that the current driving capability of the source region is greater than that of the region under the gate, to effectively suppress the increase of the source resistance under high current, and the gate voltage swing and flatness of the device were significantly improved. At 8GHz, the IMD was improved by 5dBc at a large input power.

[0005] In summary, device-level linearization technology has developed rapidly in recent years. However, the introduction of new technologies will lead to problems such as increased parasitic capacitance and deterioration of the electric field distribution under the gate, which limits the application of high-linearity GaN-based HEMTs in the millimeter-wave high-power field and becomes a bottleneck hindering the development of device-level linearization technology. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a GaN HEMT device for improving linearity and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0007] A GaN HEMT device for improving linearity, the GaN HEMT device comprising:

[0008] substrate layer;

[0009] A GaN buffer layer, wherein the buffer layer is disposed on the substrate layer;

[0010] A back-to-back barrier layer, wherein the back-to-back barrier layer is disposed on the GaN buffer layer, wherein the Al component in the back-to-back barrier layer increases from x to y from top to bottom, and then decreases from y to 0;

[0011] A source electrode and a drain electrode, wherein a portion of the depth of the source electrode and the drain electrode is located inside the two ends of the GaN buffer layer, and the sidewall of the back-to-back barrier layer is in contact with the sidewall of the source electrode and the drain electrode;

[0012] A passivation layer, wherein the passivation layer is disposed on the back-to-back barrier layer, and a sidewall of the passivation layer contacts the sidewalls of the source electrode and the drain electrode, and the passivation layer has a gate electrode region exposing the back-to-back barrier layer;

[0013] A gate electrode is disposed on the back-to-back barrier layer in a gate electrode region.

[0014] In one embodiment of the present invention, the substrate layer includes one of sapphire, SiC, and Si.

[0015] In one embodiment of the present invention, the back-to-back barrier layer includes a bottom barrier layer and a top barrier layer, the bottom barrier layer is arranged on the GaN buffer layer, and the top barrier layer is arranged on the bottom barrier layer, wherein the Al component in the top barrier layer increases from x to y from top to bottom, and the Al component in the bottom barrier layer decreases from y to 0 from top to bottom.

[0016] In one embodiment of the present invention, the value range of x is 0.1-0.4, and the value range of y is 0.5-0.8.

[0017] In one embodiment of the present invention, the thickness of the back-to-back barrier layer is in the range of 5 nm to 40 nm.

[0018] In one embodiment of the present invention, the thickness of the top barrier layer is in the range of 2 nm to 20 nm, and the thickness of the bottom barrier layer is in the range of 3 nm to 20 nm.

[0019] In one embodiment of the present invention, the back-to-back barrier layer includes one of AlGaN and InAlN.

[0020] In one embodiment of the present invention, the passivation layer includes one of SiN, SiO2, and Al2O3.

[0021] In one embodiment of the present invention, the distance between the gate electrode and the source electrode is smaller than the distance between the gate electrode and the drain electrode.

[0022] An embodiment of the present invention further provides a method for preparing a GaN HEMT device for improving linearity. The method for preparing a GaN HEMT device is used to prepare any of the above-mentioned GaN HEMT devices. The method for preparing a GaN HEMT device comprises:

[0023] Step 1: Select the substrate layer;

[0024] Step 2: growing a GaN buffer layer on the substrate layer;

[0025] Step 3, growing a back-to-back barrier layer on the GaN buffer layer, wherein the Al component in the back-to-back barrier layer increases from x to y from top to bottom, and then decreases from y to 0;

[0026] Step 4, photolithography a source electrode region and a drain electrode region on the back-to-back barrier layer, fabricating a source electrode and a drain electrode in the source electrode region and the drain electrode region, respectively, and using an annealing process to sink the source electrode and the drain electrode into the GaN buffer layer, wherein the source electrode and the drain electrode are respectively located at two ends of the GaN buffer layer;

[0027] Step 5, growing a passivation layer on the source electrode, the drain electrode and the back-to-back barrier layer;

[0028] Step 6: photolithography and etching of a gate electrode region on the passivation layer, and manufacturing a gate electrode in the gate electrode region;

[0029] Step seven: photolithography a metal interconnection region on the source electrode and the drain electrode in the metal interconnection opening area and the passivation layer that has not been etched by the opening, so as to evaporate and form a metal interconnection layer in the metal interconnection region.

[0030] Beneficial effects of the present invention:

[0031] The novel structure of the new type of gradually changing barrier GaN HEMT device provided by the present invention has significantly improved transconductance flatness compared with the conventional structure, and the linearity is improved. In addition, compared with the single gradually changing Al component barrier structure, the distribution of the electric field under the gate of the novel structure is flatter. Therefore, this structure takes into account good frequency characteristics, breakdown characteristics and excellent linearity.

[0032] The novel slow-barrier GaN HEMT device provided by the present invention has a quasi-three-dimensional distribution of carriers, a certain distribution thickness, and is mainly located inside the barrier layer, the distance from the channel to the gate is reduced, the aspect ratio of the device is improved, and the frequency characteristics are improved. At the same time, it is expected to promote the application of GaN-based HEMT in the field of high frequency and high power.

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a GaN HEMT device for improving linearity provided by an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of the variation of the Al component in a barrier layer with the thickness of the barrier when an epitaxial barrier layer is grown according to an embodiment of the present invention;

[0036] Figure 3 Carrier distribution diagrams of a conventional GaN HEMT and a novel graded barrier GaN HEMT provided in an embodiment of the present invention;

[0037] Figure 4 Transfer characteristic curves of conventional GaN HEMTs provided in embodiments of the present invention and the novel graded barrier GaN HEMTs of the present invention;

[0038] Figure 5 (a) is a diagram showing the electric field distribution along the direction parallel to the channel of a conventional GaN HEMT, a graded barrier GaN HEMT and a novel graded barrier GaN HEMT of the present invention provided in an embodiment of the present invention;

[0039] Figure 5 (b) is a diagram showing the electric field distribution along the direction perpendicular to the channel of a conventional GaN HEMT, a graded barrier GaN HEMT and a novel graded barrier GaN HEMT of the present invention provided in an embodiment of the present invention;

[0040] Figure 6 A schematic flow chart of a method for preparing a GaN HEMT device for improving linearity provided by an embodiment of the present invention;

[0041] Figure 7a-7hA schematic diagram of a process of a method for preparing a GaN HEMT device for improving linearity provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0043] Embodiment 1

[0044] At present, there are three main methods to achieve high linearity devices: 1. Using MIS-HEMT structure to achieve high linearity devices, that is, inserting a passivation layer between the gate and the barrier layer can effectively reduce gate leakage. At the same time, the total thickness from the gate to the channel increases, resulting in a decrease in the electric field strength within the same gate bias range, and the decrease in carrier mobility under large gate voltage is suppressed, the transconductance flatness is improved, and the device linearity is improved. 2. Using Fin structure to achieve high linearity devices, that is, different fin widths (W fin ) devices are connected in parallel along the gate width direction to achieve multi-threshold voltage regulation and transconductance compensation. By designing the fin length and fin height, etching depth and etching ratio, the flatness of the transconductance curve can be significantly improved. 3. Use a dual-channel structure to achieve a high linearity device, that is, use a dual-channel device to improve the linearity of the device. On the one hand, it can be attributed to the multi-threshold modulation and transconductance compensation brought about by the two channels being turned on in sequence under different gate voltage biases. On the other hand, it also suppresses the source resistance (R S ) with the leakage current (I DS ) increases with the increase of the trend.

[0045] However, 1. The main problem of the MIS structure is that the introduction of the passivation layer leads to an increase in gate capacitance and a deterioration in the frequency characteristics of the device, which is not conducive to the application of AlGaN / GaN HEMT in the high-frequency field. 2. Fin HEMT needs to etch through the channel under the gate compared to planar HEMT. Additional dry etching will inevitably introduce etching damage, which will lead to serious interface state problems and cause gate leakage. In addition, the sidewall parasitic capacitance formed by the Fin structure also limits its application at high frequencies. At the same time, since part of the channel is etched along the gate width, the actual current conduction area of ​​the Fin HEMT only accounts for a part of the total channel area. The current converted under the same gate width is greatly reduced compared to the planar HEMT, and as the integration becomes higher and higher, this also causes a waste of layout area. 3. Dual-channel devices are limited by the gate's reduced control ability over the lower channel, the lower channel's limiting effect on carriers is weakened, and the coupling between the two channels is not strong. As the device size continues to decrease, dual-channel devices are also seriously affected by the short channel effect.

[0046] Based on the above reasons, the present invention provides a GaN HEMT device for improving linearity. Figure 1 , Figure 1A schematic diagram of a structure of a GaN HEMT device for improving linearity provided in an embodiment of the present invention. The GaN HEMT device for improving linearity provided in this embodiment includes:

[0047] substrate layer;

[0048] A GaN buffer layer, wherein the buffer layer is disposed on the substrate layer;

[0049] A back-to-back barrier layer, wherein the back-to-back barrier layer is disposed on the GaN buffer layer, wherein the Al component in the back-to-back barrier layer increases from x to y from top to bottom and then decreases from y to 0;

[0050] A source electrode and a drain electrode, wherein a portion of the depth of the source electrode and the drain electrode is located inside the two ends of the GaN buffer layer, and a side wall of the back-to-back barrier layer is in contact with a side wall of the source electrode and the drain electrode;

[0051] A passivation layer, wherein the passivation layer is disposed on the back-to-back barrier layer, and a sidewall of the passivation layer is in contact with a sidewall of the source electrode and a sidewall of the drain electrode, and the passivation layer has a gate electrode region exposing the back-to-back barrier layer;

[0052] The gate electrode is disposed on the back-to-back barrier layer in the gate electrode region.

[0053] In this embodiment, since a back-to-back barrier layer is provided between the GaN buffer layer and the passivation layer, and the Al component in the back-to-back barrier layer increases first from top to bottom and then decreases to zero, as shown in FIG. Figure 2 As shown, the carriers in the channel of the GaN HEMT device are distributed in a quasi-three-dimensional manner, and the carriers in the channel have a certain distribution thickness and are mainly located inside the barrier layer, so that the peak value of the carrier concentration in the channel is located inside the back-to-back barrier layer instead of at the bottom, thereby reducing the distance from the peak value of the carrier concentration to the gate electrode, and reducing the effective barrier thickness (the distance from the position where the peak value of the carrier concentration in the channel is located to the gate electrode is the effective channel thickness) of the GaN HEMT device of this embodiment. Therefore, when the length of the gate electrode is constant, the aspect ratio can be improved (the aspect ratio refers to the ratio of the length of the gate electrode to the effective barrier thickness). With the improvement of the aspect ratio, the gate control ability of the GaN HEMT device is also improved. Because when the length of the gate electrode is constant, the effective barrier thickness is reduced, the frequency characteristics of the GaN HEMT device are improved. Secondly, the conduction band bottom of the conventional structure is located at the heterojunction interface, which is farther from the Fermi level and has a steep distribution. In contrast, the back-to-back barrier layer structure of the present embodiment makes the conduction band bottom located inside the barrier, closer to the Fermi level, and the distribution of the conduction band bottom is relatively smooth, resulting in a lower carrier concentration and an increased distribution thickness of the GaN HEMT device of the present embodiment, presenting a quasi-three-dimensional distribution. Therefore, Figure 3As shown, compared with the 2DEG (two-dimensional electron gas) of the conventional barrier structure, the carrier concentration of the GaN HEMT device of this embodiment is lower, and the mobility is improved. Since the carrier mobility is improved, the velocity-field relationship is improved, so that the decrease of transconductance under large current is suppressed, that is, the flatness of transconductance is improved, and its high-order derivative is reduced, thereby reducing the cross-modulation distortion, and finally improving the linearity of the device. Finally, the part with the highest Al component in the back-to-back barrier structure of this embodiment is located inside the back-to-back barrier, thereby transferring the electric field peak under the gate from the gate foot to the position with the highest Al component inside the back-to-back barrier layer, as shown in FIG. Figure 4 As shown, the flatness of the electric field distribution of the GaN HEMT device is significantly improved, thereby reducing the electric field peak, and thus the breakdown voltage and output power of the device are improved.

[0054] Furthermore, the substrate layer includes one of sapphire, SiC, and Si.

[0055] Furthermore, the back-to-back barrier layer includes a bottom barrier layer and a top barrier layer, the bottom barrier layer is arranged on the GaN buffer layer, and the top barrier layer is arranged on the bottom barrier layer, wherein the Al component in the top barrier layer increases from x to y from top to bottom, and the Al component in the bottom barrier layer decreases from y to 0 from top to bottom, therefore, x is the starting Al component of the top barrier layer, y is the ending Al component of the top barrier layer, and is also the starting Al component of the bottom barrier layer, and the ending Al component of the bottom barrier layer is 0.

[0056] Preferably, the value range of x is 0.1 to 0.4, and the value range of y is 0.5 to 0.8, so as to ensure that the device has DC characteristics, AC small signal characteristics, power characteristics, etc.

[0057] Preferably, the thickness of the back-to-back barrier layer is in the range of 5nm-40nm. Since the thickness of the back-to-back barrier layer is too low and inconvenient to prepare, and too thick will lead to poor frequency characteristics of the device, 5nm-40nm is selected.

[0058] Preferably, the thickness range of the top barrier layer is 2nm-20nm, and the thickness range of the bottom barrier layer is 3nm-20nm. When the total thickness of the back-to-back barrier layers is constant, the thicker the top barrier layer, the flatter the electric field distribution under the gate, and the higher the breakdown voltage and output power of the device. However, since the Al component gradient range of the bottom barrier layer is greater than that of the bottom barrier layer, that is, if the thickness of the bottom barrier and the top barrier are set to be the same, the material growth difficulty of the bottom barrier is greater than that of the top barrier. Therefore, under the condition of meeting the process level limit, the thinner the bottom barrier layer, the better, thus, the thickness range of the top barrier layer is selected to be 2nm-20nm, and the thickness range of the bottom barrier layer is selected to be 3nm-20nm.

[0059] Preferably, the back-to-back barrier layer comprises one of AlGaN and InAlN.

[0060] Preferably, the passivation layer includes one of SiN, SiO2, and Al2O3.

[0061] In a specific embodiment, a distance between the gate electrode and the source electrode is smaller than a distance between the gate electrode and the drain electrode.

[0062] First, the carriers in the channel of the slow-barrier GaN HEMT of the present invention are quasi-three-dimensionally distributed, have a certain distribution thickness, and are mainly located inside the barrier layer, so that the effective barrier thickness is reduced, the aspect ratio is improved, and the gate control capability and frequency characteristics are improved. Secondly, compared with the 2DEG of the conventional barrier structure, the carrier concentration of the new structure is lower, the mobility is improved, the decrease of transconductance under large current is suppressed, and the linearity of the device is improved. Finally, the new back-to-back barrier structure inserts a barrier layer with a reverse gradient of Al composition above the barrier layer with a monotonically gradient Al composition, and transfers the electric field peak under the gate from the gate foot to the position with the highest Al composition inside the barrier layer, the flatness of the electric field distribution is significantly improved, and the breakdown voltage and output power of the device are improved.

[0063] Embodiment 2

[0064] See also Figure 6 , Figure 6 A schematic diagram of a process flow of a GaN HEMT device for improving linearity provided by an embodiment of the present invention. Based on the above embodiment, the present invention further provides a method for preparing a GaN HEMT device for improving linearity, and the method for preparing the GaN HEMT device includes:

[0065] Step 1: Select the base layer.

[0066] Preferably, the material of the substrate layer includes sapphire, SiC, and Si.

[0067] Step 2: growing a GaN buffer layer on the substrate layer.

[0068] Step 3: growing a back-to-back barrier layer on the GaN buffer layer, wherein the Al component in the back-to-back barrier layer increases from x to y and then decreases from y to 0 from top to bottom.

[0069] Preferably, the back-to-back barrier layer is made of one of the materials such as AlGaN and InAlN, and the Al component in the layer gradually increases from x (top of the barrier layer) to y (depth T inside the barrier layer). top ), and then gradually decreases from y to 0 (the bottom of the barrier layer).

[0070] Step 4: Photolithography source electrode region and drain electrode region on the back-to-back barrier layer, respectively fabricate source electrode and drain electrode in the source electrode region and drain electrode region, and use annealing process to sink the source electrode and drain electrode into the GaN buffer layer, wherein the source electrode and drain electrode are respectively located at two ends of the GaN buffer layer.

[0071] Preferably, the source electrode and the drain electrode are a bottom-up metal stack structure of Ti, Al, Ni, and Au.

[0072] Step 5: growing a passivation layer on the source electrode, the drain electrode and the back-to-back barrier layer.

[0073] Preferably, the material of the passivation layer includes one of SiN, SiO2, and Al2O3.

[0074] Step six: photolithography and etching of a gate electrode region on the passivation layer, and fabrication of a gate electrode in the gate electrode region.

[0075] Preferably, the gate electrode is a three-layer metal stack structure of Ni, Au, and Ni from bottom to top.

[0076] Step 7: Photolithography a metal interconnection region on the source electrode and the drain electrode in the metal interconnection opening region and the passivation layer that has not been etched by the opening, so as to evaporate a metal interconnection layer in the metal interconnection region.

[0077] Preferably, the metal interconnection layer is a two-layer metal stack structure of Ti and Au from bottom to top.

[0078] The novel gradually changing barrier GaN HEMT device for improving linearity prepared by the present invention has a quasi-three-dimensional distribution of carriers, a certain distribution thickness, and is mainly located inside the barrier layer. The distance from the channel to the gate is reduced, the aspect ratio of the device is improved, and the frequency characteristics are improved. At the same time, the transconductance flatness of the novel structure is significantly improved compared with the conventional structure, and the linearity is improved. In addition, compared with the single gradually changing Al component barrier structure, the distribution of the electric field under the gate of the novel structure is flatter. Therefore, this structure takes into account good frequency characteristics, breakdown characteristics and excellent linearity, and is expected to promote the application of GaN-based HEMT in the field of high frequency and high power.

[0079] Embodiment 3

[0080] See also Figure 7a-7h , Figure 7a-7hA process diagram of a method for preparing a GaN HEMT device for improving linearity provided in an embodiment of the present invention. This embodiment further provides a method for preparing a GaN HEMT device for improving linearity based on the above embodiment. In the above embodiment, the initial material for making a new type of gradual barrier GaN HEMT device is an epitaxial substrate, and the substrate is grown using an MOCVD system, with triethylgallium (TEGa) as the Ga source, trimethylaluminum (TMAl) as the Al source, ammonia (NH3) as the N source, and a carrier gas of high-purity hydrogen (H2). The substrate includes a SiC substrate layer, a GaN buffer layer, and an AlGaN back-to-back barrier layer from top to bottom. The AlGaN back-to-back barrier layer adopts a gradual growth method, first growing a bottom barrier layer with a decreasing Al component on the buffer layer, and then growing a top barrier layer with an inversely increasing Al component, such as Figure 7a-7c When epitaxially growing back-to-back barrier layers, the relationship between the Al composition in the layer and the thickness of the barrier layer is shown in Figure 2 The device structure made on the basis of the existing epitaxial wafer is shown in Figure 1 As shown, the preparation process steps are as follows:

[0081] Step 1: Figure 7d As shown, a source electrode and a drain electrode are fabricated on an epitaxial substrate.

[0082] Specifically, the source electrode region and the drain electrode region are photolithographically formed on the AlGaN back-to-back barrier layer:

[0083] (a) Place the epitaxial substrate on a hot plate at 200°C and bake for 5 min;

[0084] (b) Applying a stripping glue (PMGI SF6) on the AlGaN back-to-back barrier layer, the spin speed of the spinner is 2000 rad / min, the spin time is 40 sec, and the spin thickness is 0.35 μm. Then the sample is placed on a hot plate at 200°C and baked for 5 min.

[0085] (c) coating photoresist (EPI621) on the stripping glue, with a spinning speed of 5000 rad / min, a spinning time of 30 sec, and a spinning thickness of 0.77 μm. The sample was then baked on a hot plate at 90° C. for 1 min.

[0086] (d) placing the sample after the glue coating and the glue spinning into a photolithography machine to expose the glue coated surface for 230 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0087] (e) placing the film in a developer (EPD1000) to remove the photoresist and stripping adhesive for 45 seconds, then rinsing with ultrapure water and drying with nitrogen to obtain defined source electrode regions and drain electrode regions;

[0088] 2) Evaporating the source electrode and the drain electrode on the AlGaN back-to-back barrier layer in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region:

[0089] (a) Place the sample with active electrode and drain electrode photolithography patterns in a plasma stripper for bottom film treatment, with a power of 200 W, O2 = 100 sccm, and a treatment time of 5 min;

[0090] (b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After Torr, ohmic metal is evaporated on the AlGaN back-to-back barrier layer in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form the source electrode and the drain electrode. The ohmic metal is Ti / Al / Ni / Au from bottom to top, and its thickness is

[0091] (c) The sample after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist and stripping glue outside the source electrode and the drain electrode, and then the sample is rinsed with ultrapure water and blown dry with nitrogen.

[0092] 3) The sample after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing, so that the ohmic metal on the AlGaN back-to-back barrier layer in the source electrode and the drain electrode sinks to the GaN buffer layer, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere is N2, annealing temperature is 840°C, and annealing time is 60s.

[0093] Step 2: Figure 7e As shown, a SiN passivation layer is grown on the source electrode, the drain electrode and the AlGaN back-to-back barrier layer in the active region using a PECVD process.

[0094] 1) Surface cleaning of samples after source and drain electrodes are completed:

[0095] (a) The sample was placed in an acetone solution and ultrasonically cleaned for 5 min with an ultrasonic intensity of 2.2;

[0096] (b) Place the sample in a stripping solution at 60°C and heat it in a water bath for 15 min;

[0097] (c) The sample was placed in an acetone solution and an isopropanol solution for ultrasonic cleaning for 3 min, with an ultrasonic intensity of 2.2;

[0098] (d) Rinse the sample with ultrapure water and blow dry with nitrogen;

[0099] 2) A SiN passivation layer with a thickness of 120 nm was grown on the source electrode, drain electrode and AlGaN back-to-back barrier layer of the active area using a PECVD process. The growth process conditions were: SiN (2% SiH4 / N2) = 200 sccm, NH3 = 2 sccm, N2 = 0 sccm, He = 200 sccm, pressure = 600 mT, temperature = 250°C, power = 22 W, and deposition time = 25 min.

[0100] Step 3: Figure 7f As shown, a gate groove region is photolithographically formed on the SiN passivation layer, and the SiN passivation layer in the gate groove region is etched using an ICP process.

[0101] 1) Photolithography of the gate groove area on the SiN passivation layer:

[0102] (a) Place the sample on a hot plate at 200 °C and bake for 5 min;

[0103] (b) coating and spinning of electron beam photoresist, with a spinning speed of 3500 rad / min, a spinning time of 40 sec, a layer thickness of 450 nm, and baking the sample on a hot plate at 150° C. for 1 min;

[0104] (c) placing the sample in an electron beam lithography machine to expose the photoresist in the gate groove area;

[0105] (d) placing the exposed sample into a developer to remove the photoresist in the gate groove region, and drying the sample with nitrogen gas;

[0106] 2) The SiN passivation layer in the gate groove region is removed by ICP etching process, and the etching conditions are: CF4=60sccm, O2=2sccm, pressure=1Pa, upper electrode power=100W, lower electrode power=25W. The etching depth is equal to the thickness of the SiN layer.

[0107] Step 4: Figure 7g As shown, the gate electrode region is photolithographically processed, and the gate electrode is formed using an electron beam evaporation process.

[0108] 1) Photolithography gate electrode region on AlGaN back-to-back barrier layer:

[0109] (a) Place the sample on a hot plate at 200 °C and bake for 5 min;

[0110] (b) Applying a stripping glue (PMGI SF6) on the SiN passivation layer, the spinning speed of the glue table is 2000 rad / min, the spinning time is 40 seconds, and the thickness of the glue is 0.35 μm, and then the sample is placed on a hot plate at 200°C and baked for 5 minutes;

[0111] (c) coating photoresist (EPI621) on the stripping glue, with a spinning speed of 5000 rad / min, a spinning time of 30 sec, and a spinning thickness of 0.77 μm. The sample was then baked on a hot plate at 90° C. for 1 min.

[0112] (d) placing the sample after the glue coating and the glue spinning into a photolithography machine to expose the glue coated surface for 280 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0113] (e) The film is placed in a developer (EPD1000) to remove the photoresist and stripping adhesive for 60 seconds, and then rinsed with ultrapure water and dried with nitrogen.

[0114] 2) Evaporating the gate electrode on the AlGaN back-to-back barrier layer in the gate electrode area and on the photoresist outside the gate electrode area:

[0115] (a) Place the sample with the gate electrode photolithography pattern into a plasma stripper for bottom film treatment, with a power of 200 W, O2 = 100 sccm, and a treatment time of 5 min;

[0116] (b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After Torr, the gate metal is evaporated on the AlGaN back-to-back barrier layer in the gate electrode area and the photoresist outside the gate electrode area. The gate metal is sequentially formed from bottom to top.

[0117] (c) Stripping the sample after gate metal evaporation to remove the gate metal, photoresist and stripping glue outside the gate electrode area, rinse the sample with ultrapure water and blow dry with nitrogen to form a gate electrode.

[0118] Step 5: Photolithography a metal interconnect opening region on the SiN passivation layer, and sequentially etch away the SiN passivation layer in the interconnect opening region using an ICP process.

[0119] 3) Photolithography of metal interconnect opening area on SiN passivation layer:

[0120] (a) Place the sample on a hot plate at 200 °C and bake for 5 min;

[0121] (b) Apply photoresist (EPI621) on the sample at a spinning speed of 3000 rad / min for 30 seconds, and then bake the sample on a hot plate at 90°C for 1 minute;

[0122] (c) placing the sample after the glue coating and the glue spinning into a photolithography machine to expose the glue coated surface for 280 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0123] (d) placing the exposed sample in a developer (EPD1000) to remove the photoresist in the interconnect opening area for 75 seconds, and then rinsing with ultrapure water and drying with nitrogen gas;

[0124] (e) Before etching the metal interconnect opening area, the film was hardened and the sample was baked on a hot plate at 100°C for 1 min;

[0125] 3) Using the ICP etching process, the reaction gases are CF4 and O2, CF4=60sccm, O2=2sccm, pressure=1Pa, upper electrode power=100W, lower electrode power=25W, and the 120nm thick SiN passivation layer in the interconnect opening area is removed.

[0126] Step 6, photolithography a metal interconnection layer region on the source electrode and the drain electrode in the metal interconnection opening region and the SiN passivation layer that has not been etched through the opening, and use an electron beam evaporation process to form a metal interconnection layer.

[0127] 1) Photolithography of the metal interconnect layer on the source electrode and drain electrode in the metal interconnect opening area and the SiN passivation layer that has not been etched:

[0128] (a) Place the sample with metal interconnect hole etching on a hot plate at 200°C for 5 min.

[0129] (b) Applying a stripping glue (PMGI SF6) on the AlGaN back-to-back barrier layer, the spin speed of the spinner is 2000 rad / min, the spin time is 40 sec, and the spin thickness is 0.35 μm. Then the sample is placed on a hot plate at 200°C and baked for 5 min.

[0130] (c) coating photoresist (EPI621) on the stripping glue, with a spinning speed of 5000 rad / min, a spinning time of 30 sec, and a spinning thickness of 0.77 μm. The sample was then baked on a hot plate at 90° C. for 1 min.

[0131] (d) placing the sample after the glue coating and the glue spinning into a photolithography machine to expose the glue coated surface for 270 ms, and baking the exposed sample on a hot plate at 110° C. for 1 min;

[0132] (e) placing the substrate in a developer (EPD1000) to remove the photoresist and stripping adhesive in the metal interconnection area for 60 seconds, and then rinsing the substrate with ultrapure water and drying it with nitrogen gas;

[0133] 2) Evaporating the metal interconnect layer on the electrode and SiN passivation layer in the metal interconnect area and the photoresist outside the metal interconnect area:

[0134] (a) Place the sample with metal interconnection area in a plasma stripper for bottom film treatment, power 200W, O2=100sccm, treatment time 5min;

[0135] (b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After the evaporation of the metal interconnection metal on the electrode and SiN passivation layer in the metal interconnection area and the photoresist outside the metal interconnection area, the metal interconnection layer is formed. To extract the electrode;

[0136] (c) If Figure 7h As shown, the sample after interconnect metal evaporation is stripped to remove the metal, photoresist and stripping glue outside the metal interconnect area layer, and the sample is rinsed with ultrapure water and blown dry with nitrogen to complete the device manufacturing.

[0137] The device has a modulation effect on the energy band due to the non-uniform change of Al composition in the barrier layer, making the carriers in the channel quasi-three-dimensional distribution, such as Figure 3 As shown. This also improves the nonlinearity of the conventional barrier structure, which is reflected in the improvement of transconductance flatness, as shown in Figure 4 Compared with the bottom barrier with only decreasing Al content, the back-to-back double-layer barrier also has the effect of modulating and improving the electric field distribution under the gate, as shown in Figure 5 a and Figure 5 As shown in b.

[0138] The method for preparing the GaN HEMT device provided in this embodiment is used to prepare the GaN HEMT device of the first embodiment. Its implementation principle and technical effect are similar and will not be described in detail here.

[0139] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0140] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or special data points described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or special data points described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0141] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A GaN HEMT device for improving linearity, characterized in that: The GaN HEMT device comprises: substrate layer; A GaN buffer layer, wherein the buffer layer is disposed on the substrate layer; A back-to-back barrier layer, wherein the back-to-back barrier layer is disposed on the GaN buffer layer, wherein the Al component in the back-to-back barrier layer increases from x to y from top to bottom, and then decreases from y to 0; A source electrode and a drain electrode, wherein a portion of the depth of the source electrode and the drain electrode is located inside the two ends of the GaN buffer layer, and the sidewall of the back-to-back barrier layer is in contact with the sidewall of the source electrode and the drain electrode; A passivation layer, wherein the passivation layer is disposed on the back-to-back barrier layer, and a sidewall of the passivation layer contacts the sidewalls of the source electrode and the drain electrode, and the passivation layer has a gate electrode region exposing the back-to-back barrier layer; A gate electrode is disposed on the back-to-back barrier layer in a gate electrode region.

2. The GaN HEMT device for improving linearity according to claim 1, characterized in that: The substrate layer includes one of sapphire, SiC and Si.

3. The GaN HEMT device for improving linearity according to claim 1, characterized in that: The value range of x is 0.1~0.4, and the value range of y is 0.5~0.

8.

4. The GaN HEMT device for improving linearity according to claim 3, characterized in that: The thickness of the back-to-back barrier layer is in the range of 5 nm to 40 nm.

5. The GaN HEMT device for improving linearity according to claim 4, characterized in that: The thickness of the top barrier layer is in the range of 2nm-20nm, and the thickness of the bottom barrier layer is in the range of 3nm-20nm.

6. The GaN HEMT device for improving linearity according to any one of claims 1 to 5, characterized in that: The back-to-back barrier layer includes one of AlGaN and InAlN.

7. The GaN HEMT device for improving linearity according to claim 1, characterized in that: The passivation layer includes one of SiN, SiO2, and Al2O3.

8. The GaN HEMT device for improving linearity according to claim 1, characterized in that: A distance between the gate electrode and the source electrode is smaller than a distance between the gate electrode and the drain electrode.

9. A method for preparing a GaN HEMT device for improving linearity, characterized in that: The method for preparing the GaN HEMT device is used to prepare the GaN HEMT device according to any one of claims 1 to 8, and the method for preparing the GaN HEMT device comprises: Step 1: Select the substrate layer; Step 2: growing a GaN buffer layer on the substrate layer; Step 3, growing a back-to-back barrier layer on the GaN buffer layer, wherein the Al component in the back-to-back barrier layer increases from x to y from top to bottom, and then decreases from y to 0; Step 4, photolithography a source electrode region and a drain electrode region on the back-to-back barrier layer, fabricating a source electrode and a drain electrode in the source electrode region and the drain electrode region, respectively, and using an annealing process to sink the source electrode and the drain electrode into the GaN buffer layer, wherein the source electrode and the drain electrode are respectively located at two ends of the GaN buffer layer; Step 5, growing a passivation layer on the source electrode, the drain electrode and the back-to-back barrier layer; Step 6: photolithography and etching of a gate electrode region on the passivation layer, and manufacturing a gate electrode in the gate electrode region; Step seven: photolithography a metal interconnection region on the source electrode and the drain electrode in the metal interconnection opening area and the passivation layer that has not been etched by the opening, so as to evaporate and form a metal interconnection layer in the metal interconnection region.

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