A brushless DC motor commutation control circuit

Abstract

The present invention relates to a brushless DC motor commutation control circuit, which belongs to the field of brushless DC motor commutation technology, and solves the problem of large switching loss and motor loss in the commutation control circuit in the prior art. The brushless DC motor commutation control circuit includes: a commutation control logic circuit, which is used to receive and process a direction control signal, a PWM signal, a position Hall signal output by a brushless DC motor, and a signal after the position Hall signal and the direction control signal are subjected to a non-logical operation, and generate a commutation control logic signal adapted to the PWM modulation mode of the power main circuit; a drive circuit, which is used to amplify the commutation control logic signal to obtain a drive signal; the power main circuit is used to generate a brushless DC motor input control signal based on the drive signal, and use the brushless DC motor input control signal to drive the brushless DC motor to work. The circuit can effectively reduce switching loss and motor loss.

Description

Technical Field

[0001] The invention relates to the technical field of brushless DC motor commutation technology, and in particular to a brushless DC motor commutation control circuit. Background Art

[0002] Brushless DC motors have the advantages of simple structure, small size, high power density, high efficiency, etc., and are widely used in various fields of national economy such as national defense, aerospace, aviation, automobiles, and home appliances. With the emergence of permanent magnet materials and the rapid development of electronic components, permanent magnet brushless DC motors are more widely used, and small size and high reliability brushless DC motor drive circuits have become one of the key technologies in the development of brushless DC motors.

[0003] At present, there are mainly two methods for the commutation control circuit of a brushless DC motor. The first method is a method that adopts a position sensor, a bridge drive circuit and a processor chip to jointly implement the method. The processor chip collects the signal of the position sensor, and outputs a control signal to control the bridge drive circuit to realize the commutation of the motor according to the commutation control algorithm. The advantages of this method are mature technology and simple control algorithm, but the disadvantages are that due to the need for a processor chip and peripheral circuits, the circuit is complex, large in size, and high in cost, which is limited when used in low-cost applications. The second method is a method without a position sensor, which uses a processor chip, a control algorithm and a detection circuit to jointly realize the commutation of the motor. The advantage of this method is that the position sensor is omitted and the motor leads are reduced, but the disadvantage is that the detection circuit and the control algorithm are relatively complex, and the processor chip and the control algorithm need to be combined, resulting in high cost, reduced reliability, and large switching loss and motor loss. Summary of the invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a brushless DC motor commutation control circuit to solve the problems of poor reliability, large size, high cost, large switching loss and motor loss in existing motor commutation control circuits.

[0005] A brushless DC motor commutation control circuit, comprising:

[0006] A commutation control logic circuit is used to receive and process a direction control signal, a PWM signal, a position Hall signal output by a brushless DC motor, and a signal after a logical negation operation of the position Hall signal and the direction control signal, and generate a commutation control logic signal adapted to a PWM modulation mode of a power main circuit;

[0007] A driving circuit, used for amplifying the commutation control logic signal to obtain a driving signal;

[0008] The power main circuit is used to generate a brushless DC motor input control signal based on the driving signal, and use the brushless DC motor input control signal to drive the brushless DC motor to work.

[0009] Based on the above solution, this embodiment also makes the following improvements:

[0010] Further, when the PWM modulation mode is the H-PWM_L-ON mode, the corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR in the commutation control logic circuit and the commutation control logic signals S1-S6 is:

[0011] If HA, HB, HC, and DIR are "1011" or "0100", the waveform of signal S1 is a PWM signal, signals S2, S3, S4, and S5 are low levels, and signal S6 is high level;

[0012] If HA, HB, HC, and DIR are "1001" or "0110", the waveform of signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low level, and signal S2 is high level;

[0013] If HA, HB, HC, and DIR are "1101" or "0010", the waveform of signal S3 is a PWM signal, signals S1, S4, S5, and S6 are all low level, and signal S2 is high level;

[0014] If HA, HB, HC, and DIR are "0101" or "1010", the waveform of signal S3 is a PWM signal, signals S1, S2, S5, and S6 are all low level, and signal S4 is high level;

[0015] If HA, HB, HC, and DIR are "0111" or "1000", the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S6 are all low level, and signal S4 is high level;

[0016] If HA, HB, HC, and DIR are "0011" or "1100", the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low level, and signal S6 is high level;

[0017] When DIR is 1, the motor rotates forward, and when DIR is 0, the motor rotates reversely.

[0018] Further, the signals S1, S3, and S5 are respectively used to control the opening or closing of the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; the signals S2, S4, and S6 are respectively used to control the opening or closing of the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on one bridge arm, VT3 and VT6 are on one bridge arm, and VT5 and VT2 are on one bridge arm.

[0019] Furthermore, if the waveform of S1 is a PWM signal, signals S2, S3, S4, and S5 are all low levels, and signal S6 is high level, then the input control signal UA of the A-phase brushless DC motor is an alternating change between DC+ / 2 and 0: when the PWM signal is high level, it is DC+ / 2, and when the PWM signal is low level, it is 0; the input control signal UB of the B-phase brushless DC motor is 0; the input control signal UC of the C-phase brushless DC motor is a linear decrease from DC+ / 2 to -DC+ / 2;

[0020] If the waveform of signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low level, and signal S2 is high level, then UA is an alternating change between DC+ / 2 and 0; UC is 0; UB is a linear increase from -DC+ / 2 to DC+ / 2;

[0021] If the waveform of signal S3 is a PWM signal, signals S1, S4, S5, and S6 are all low level, and signal S2 is high level, then UB is an alternating change between DC+ / 2 and 0, UC is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2;

[0022] If the waveform of signal S3 is a PWM signal, signals S1, S2, S5, and S6 are all low level, and signal S4 is high level, then UB is an alternating change between DC+ / 2 and 0, UA is 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2;

[0023] If the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S6 are all low level, and signal S4 is high level, then UC is an alternating change between DC+ / 2 and 0, UA is 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2;

[0024] If the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low levels, and signal S6 is high level, then UC is an alternating change between DC+ / 2 and 0, UB is 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2.

[0025] Furthermore, the commutation control circuit also includes an overcurrent protection circuit.

[0026] When the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is a low level; otherwise, the output overcurrent protection signal is a high level;

[0027] The overcurrent protection signal is input to the commutation control logic circuit. When the overcurrent protection signal is at a low level, the commutation control logic signals S2, S4 and S6 are pulled down.

[0028] Furthermore, the commutation control circuit further includes a fault counting and latching circuit,

[0029] The fault counting and latching control circuit receives the overcurrent protection signal, and each time the overcurrent protection signal is detected to switch from a high level to a low level, the count value stored in the fault counting and latching circuit is increased by 1;

[0030] When the count value does not reach the set count threshold, the first locking signal output by the fault counting and latching circuit is latched as a low level, and the second locking signal is latched as a high level;

[0031] When the count value reaches the set count threshold, the first locking signal output by the fault counting and latching circuit is latched as a high level, and the second locking signal is latched as a low level;

[0032] The first locking signal is input to the driving circuit, and when the first latch signal is at a high level, the driving signal is simultaneously locked to a low level;

[0033] The second locking signal is input to the phase switching control logic circuit. When the second locking signal is at a low level, the phase switching control logic signals S2, S4 and S6 are pulled low.

[0034] Further, the initial value of the count value is zero;

[0035] When the fault counting and latching circuit receives a reset signal, the count value is reset.

[0036] Furthermore, the commutation control logic circuit includes: S1-S6 logic control modules, each logic control module is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the logical negation operation are HA1, HB1, and HC1 respectively, and the signals of DIR after the logical negation operation are DIR1; wherein:

[0037] The S1 logic control module includes AND gates 1-6 and OR gate 1; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 receive signals DIR and PWM respectively; the two input ends of AND gate 3 are connected to the output ends of AND gate 1 and AND gate 2 respectively; the two input ends of AND gate 4 receive signals HA1 and HB respectively, and the two input ends of AND gate 5 receive signals DIR1 and PWM respectively; the two input ends of AND gate 6 are connected to the output ends of AND gate 4 and AND gate 5 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 3 and AND gate 6 respectively, and the output end of OR gate 1 outputs signal S1;

[0038] The S3 logic control module includes AND gates 7-12 and an OR gate 2; the two input ends of the AND gate 7 receive signals HB and HC1 respectively, and the two input ends of the AND gate 8 receive signals DIR and PWM respectively; the two input ends of the AND gate 9 are connected to the output ends of the AND gate 7 and the AND gate 8 respectively; the two input ends of the AND gate 10 receive signals HB1 and HC respectively, and the two input ends of the AND gate 11 receive signals DIR1 and PWM respectively; the two input ends of the AND gate 12 are connected to the output ends of the AND gate 10 and the AND gate 11 respectively; the two input ends of the OR gate 2 are connected to the output ends of the AND gate 9 and the AND gate 12 respectively, and the output end of the OR gate 2 outputs a signal S3;

[0039] The S5 logic control module includes AND gates 13-18 and an OR gate 3; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 receive signals DIR and PWM respectively; the two input ends of the AND gate 15 are connected to the output ends of the AND gates 13 and 14 respectively; the two input ends of the AND gate 16 receive signals HC1 and HA respectively, and the two input ends of the AND gate 17 receive signals DIR1 and PWM respectively; the two input ends of the AND gate 18 are connected to the output ends of the AND gate 16 and the AND gate 17 respectively; the two input ends of the OR gate 3 are connected to the output ends of the AND gate 15 and the AND gate 18 respectively, and the output end of the OR gate 3 outputs a signal S5;

[0040] The S2 logic control module includes AND gates 19-24 and an OR gate 4; the two input ends of the AND gate 19 receive signals HC and HA1 respectively, and the two input ends of the AND gate 20 receive signals DIR1 and ST respectively; the two input ends of the AND gate 21 are connected to the output ends of the AND gate 19 and the AND gate 20 respectively; the two input ends of the AND gate 22 receive signals HC1 and HA respectively, and the two input ends of the AND gate 23 receive signals DIR and ST respectively; the two input ends of the AND gate 24 are connected to the output ends of the AND gate 22 and the AND gate 23 respectively; the two input ends of the OR gate 4 are connected to the output ends of the AND gate 21 and the AND gate 24 respectively, and the output end of the OR gate 4 outputs a signal S2;

[0041] The S4 logic control module includes AND gates 25-30 and an OR gate 5; the two input ends of the AND gate 25 receive signals HA and HB1 respectively, and the two input ends of the AND gate 26 receive signals DIR1 and ST respectively; the two input ends of the AND gate 27 are connected to the output ends of the AND gate 25 and the AND gate 26 respectively; the two input ends of the AND gate 28 receive signals HA1 and HB respectively, and the two input ends of the AND gate 29 receive signals DIR and ST respectively; the two input ends of the AND gate 30 are connected to the output ends of the AND gate 28 and the AND gate 29 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 27 and the AND gate 30 respectively, and the output end of the OR gate 5 outputs a signal S4;

[0042] The S6 logic control module includes AND gates 31-36 and an OR gate 6; the two input ends of the AND gate 31 receive signals HB and HC1 respectively, and the two input ends of the AND gate 32 receive signals DIR1 and ST respectively; the two input ends of the AND gate 33 are connected to the output ends of the AND gate 31 and the AND gate 32 respectively; the two input ends of the AND gate 34 receive signals HB1 and HC respectively, and the two input ends of the AND gate 35 receive signals DIR and ST respectively; the two input ends of the AND gate 36 are connected to the output ends of the AND gate 34 and the AND gate 35 respectively; the two input ends of the OR gate 6 are connected to the output ends of the AND gate 33 and the AND gate 36 respectively, and the output end of the OR gate 6 outputs a signal S6;

[0043] If the brushless DC motor commutation control circuit includes an overcurrent protection circuit and a fault counting and latching circuit, the signal ST is obtained by performing an AND logic operation on the second latch signal and the overcurrent protection signal; otherwise, the signal ST is 1.

[0044] Furthermore, the driving circuit includes three IR2110 driving chips, each IR2110 driving chip is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit;

[0045] If the brushless DC motor commutation control circuit includes an overcurrent protection circuit and a fault counting and latching circuit, the SD pin of each IR2110 driver chip is connected to a low level; otherwise, the SD pin of each IR2110 driver chip is controlled by the first locking signal.

[0046] Furthermore, the circuit also includes a signal shaping circuit for performing the negation logic operation on the position Hall signal and the direction control signal output by the brushless DC motor.

[0047] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0048] The brushless DC motor commutation drive circuit provided by the present invention can realize the commutation control of the brushless DC motor by adopting a commutation control logic circuit, and only one PWM signal and one square control signal are used. At this time, the power main circuit control mode adopts the H-PWM_L-ON mode, that is, the upper bridge arm is in the PWM chopping mode, and the lower bridge arm is in a constant on or constant off state, which is beneficial to reduce the switching loss and the motor loss. The circuit has the advantages of high reliability, small size, low cost, etc.

[0049] In addition, the overcurrent protection circuit is used to protect against single instantaneous overcurrent faults and can automatically recover. The overcurrent tolerance times are set by the fault counting and latching circuit, which can achieve continuous protection against overcurrent tolerance times exceeding the limit. After the fault is eliminated, the fault protection can be cleared through the fault clearing signal. No special controller chip is required, which simplifies the control system and improves system reliability.

[0050] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0052] Figure 1 The brushless DC motor commutation control circuit in embodiment 1 of the present invention;

[0053] Figure 2 The signal shaping circuit in Embodiment 1 of the present invention;

[0054] Figure 3 The phase-change control logic circuit in Embodiment 1 of the present invention;

[0055] Figure 4 The driving circuit in Embodiment 1 of the present invention;

[0056] Figure 5 The main power circuit in Embodiment 1 of the present invention;

[0057] Figure 6 The brushless DC motor commutation control circuit with overcurrent protection in embodiment 2 of the present invention;

[0058] Figure 7 The commutation control logic circuit with overcurrent protection in Embodiment 2 of the present invention;

[0059] Figure 8 The overcurrent protection circuit in Embodiment 2 of the present invention;

[0060] Fig. 9 The fault counting and latching circuit in Embodiment 2 of the present invention;

[0061] Fig.10 This is the driving circuit in embodiment 2 of the present invention. DETAILED DESCRIPTION

[0062] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0063] Example 1

[0064] A specific embodiment 1 of the present invention discloses a brushless DC motor commutation control circuit, the structural diagram of which is shown in FIG. Figure 1 As shown, it includes: a commutation control logic circuit, which is used to receive and process a direction control signal, a PWM signal, a position Hall signal output by a brushless DC motor, and a signal after a logical negation operation of the position Hall signal and the direction control signal, and generate a commutation control logic signal adapted to the PWM modulation mode of the power main circuit; a drive circuit, which is used to amplify the commutation control logic signal to obtain a drive signal; the power main circuit is used to generate a brushless DC motor input control signal based on the drive signal, and use the brushless DC motor input control signal to drive the brushless DC motor to work.

[0065] Compared with the prior art, the brushless DC motor commutation control circuit provided in this embodiment is designed in conjunction with the PWM modulation method of the power main circuit. The commutation control of the brushless DC motor can be achieved through only one PWM signal and one direction control signal. It has the advantages of simple circuit structure, high reliability, and small size. It is also beneficial to reduce switching loss and motor loss.

[0066] It should be noted that the direction control signal in this embodiment is used to indicate whether the brushless DC motor rotates forward or reversely. In this embodiment, when the motor is controlled to rotate forward, the direction control signal DIR is set to a high level; when the motor is controlled to rotate reversely, the direction control signal DIR is set to a low level; in addition, the PWM signal in this embodiment is used to adjust the speed of the brushless DC motor. Optionally, the frequency of the PWM signal can be set to 5k~20kz, and the duty cycle d of the PWM signal ranges from 0 to 1. The motor speed regulation can be achieved by changing the duty cycle of the PWM signal: the larger the duty cycle, the higher the corresponding motor speed; the smaller the duty cycle, the smaller the corresponding motor speed; a duty cycle of 1 corresponds to the highest adjustable speed, and a duty cycle of 0 corresponds to the lowest adjustable speed (i.e., 0 speed).

[0067] Exemplarily, the circuit further comprises a signal shaping circuit, such as Figure 2 As shown, it is used to perform negation logic operations on the position Hall signal and the direction control signal respectively.

[0068] like Figure 1 As shown, the position Hall signals output by the brushless DC motor include the A-phase position Hall signal HA, the B-phase position Hall signal HB, and the C-phase position Hall signal HC; the corresponding signals of the position Hall signals HA, HB, HC and the direction control signal DIR after the signal shaping circuit performs a negation logic operation are represented as HA1, HB1, HC1, and DIR1 respectively; the commutation control logic circuit processes the signals HA, HB, HC, DIR, HA1, HB1, HC1, DIR1 and the PWM signal, and outputs the commutation logic signals S1-S6; among which, the signals S1, S3, S5 is the switching control logic signal for the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; signals S2, S4, and S6 are the switching control logic signals for the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on the same bridge arm, and the connection point of VT1 and VT4 outputs signal UA; VT3 and VT6 are on the same bridge arm, and the connection point of VT3 and VT6 outputs signal UB; VT5 and VT2 are on the same bridge arm, and the connection point of VT5 and VT2 outputs signal UC. After being driven by the driving circuit, signals S1-S6 output driving signals G1-G6, wherein signal S1 drives the amplified output signal G1, signal S2 drives the amplified output signal G2, signal S3 drives the amplified output signal G3, signal S4 drives the amplified output signal G4, signal S5 drives the amplified output signal G5, and signal S6 drives the amplified output signal G6. The power main circuit adjusts the opening or closing of the power tubes VT1-VT6 according to the drive signals G1-G6, and outputs the brushless DC motor input control signals UA, UB, UC, and uses UA, UB, UC to control the rotation of the brushless DC motor. Specifically, the signals G1, G3, and G5 implement PWM chopping control, and the frequency and duty cycle are the same as the input PWM signal. The signals G4, G6, and G2 are in a constant on or constant off state, and no PWM chopping is performed. Therefore, the upper bridge arms VT1, VT3, and VT5 of the power main circuit are in a PWM chopping mode, and the lower bridge arms VT4, VT6, and VT2 are in a constant on or constant off state, and no PWM chopping is performed. Therefore, when the power main circuit control mode adopts the H-PWM_L-ON mode, it is beneficial to reduce switching losses and motor losses.

[0069] When the motor rotates one circle, the position Hall signals HA, HB, and HC will have six states, namely "101", "100", "110", "010", "011", and "001". Assuming that the duty cycle of the PWM signal is d (the range of duty cycle d is 0 to 1), then when the PWM modulation mode is H-PWM_L-ON mode (that is, the upper bridge arm is in PWM chopping mode, and the lower bridge arm is in a constant on or constant off state), the corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR in the commutation control logic circuit and the commutation control logic signals S1-S6 is:

[0070] When the motor rotates forward, DIR is 1; at this time,

[0071] If HA, HB, HC are "101" (that is, the states of HA, HB, HC are 1, 0, 1 respectively), after passing through the signal shaping circuit, the signals HA1, HB1, HC1 are "010", DIR1 is "0", after passing through the commutation circuit, the waveform of S1 is a PWM signal with a duty cycle of d, S2, S3, S4, S5 are all low level, S6 is high level, after passing through the drive circuit, the waveform of G1 is a PWM signal with a duty cycle of d, G2, G3, G4, G5 are all low level, G6 is high level, when passing through the power main circuit, VT1 of the power main circuit is affected by G 1 signal modulation and is in an alternating on-off action (when G1 is 1, VT1 is on, when G1 is 0, VT1 is off), VT2, VT3, VT4, and VT5 of the power main circuit are all off, and VT6 is turned on due to the high level of G6. At this time, UA of the power main circuit is an alternating change between DC+ / 2 and 0 (when the PWM signal takes a high level, VT1 is on, UA is DC+ / 2; when the PWM signal takes a low level, VT1 is off, UA is 0), UB is 0, and UC is a linear decrease from DC+ / 2 to -DC+ / 2 (when HA, HB, and HC are "101");

[0072] If HA, HB, and HC are "100" (that is, the states of HA, HB, and HC are 1, 0, and 0, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "011", and DIR1 is "0". After passing through the commutation circuit, the waveform of S1 is a PWM signal with a duty cycle of d, S3, S4, S5, and S6 are all low levels, and S2 is high level. After passing through the drive circuit, the waveform of G1 is a PWM signal with a duty cycle of d, G3, G4, G5, and G6 are all low levels, and G2 is high level. When passing through the power main circuit, the power VT1 of the main circuit is modulated by the G1 signal and is in an alternating on-off action (when G1 is 1, VT1 is on, and when G1 is 0, VT1 is off), VT3, VT4, VT5, and VT6 of the power main circuit are all off, and VT2 is turned on due to the high level of G2. At this time, UA of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT1 is on, UA is DC+ / 2, and when VT1 is off, UA is 0), UC is 0, and UB is a linear increase from -DC+ / 2 to DC+ / 2 (when HA, HB, and HC are "100");

[0073] If HA, HB, and HC are "110" (that is, the states of HA, HB, and HC are 1, 1, and 0, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "001", and DIR1 is "0". After passing through the commutation circuit, the waveform of S3 is a PWM signal with a duty cycle of d, S1, S4, S5, and S6 are all low levels, and S2 is high level. After passing through the drive circuit, the waveform of G3 is a PWM signal with a duty cycle of d, G1, G4, G5, and G6 are all low levels, and G2 is high level. When passing through the power main circuit, the power VT3 of the main circuit is modulated by the G3 signal and is in an alternating on-off action (when G3 is 1, VT3 is on, and when G3 is 0, VT3 is off), VT1, VT4, VT5, and VT6 of the power main circuit are all off, and VT2 is turned on due to the high level of G2. At this time, UB of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT3 is on, UB is DC+ / 2, and when VT3 is off, UB is 0), UC is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2 (when HA, HB, and HC are "110");

[0074] If HA, HB, and HC are "010" (that is, the states of HA, HB, and HC are 0, 1, and 0, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "101", and DIR1 is "0". After passing through the commutation circuit, the waveform of S3 is a PWM signal with a duty cycle of d, S1, S2, S5, and S6 are all low levels, and S4 is high level. After passing through the drive circuit, the waveform of G3 is a PWM signal with a duty cycle of d, G1, G2, G5, and G6 are all low levels, and G4 is high level. When passing through the power main circuit, the power VT3 of the main circuit is modulated by the G3 signal and is in an alternating on-off action (when G3 is 1, VT3 is on, and when G3 is 0, VT3 is off), VT1, VT2, VT5, and VT6 of the power main circuit are all off, and VT4 is turned on due to the high level of G4. At this time, UB of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT3 is on, UB is -DC+ / 2, and when VT3 is off, UB is 0), UA is 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2 (when HA, HB, and HC are "010");

[0075] If HA, HB, and HC are "011" (that is, the states of HA, HB, and HC are 0, 1, and 1, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "100", and DIR1 is "0". After passing through the commutation circuit, the waveform of S5 is a PWM signal with a duty cycle of d, S1, S2, S3, and S6 are all low levels, and S4 is high level. After passing through the drive circuit, the waveform of G5 is a PWM signal with a duty cycle of d, G1, G2, G3, and G6 are all low levels, and G4 is high level. When passing through the power main circuit, the power VT5 of the main circuit is modulated by the G5 signal and is in an alternating on-off action (when G5 is 1, VT5 is on, and when G5 is 0, VT5 is off), VT1, VT2, VT3, and VT6 of the power main circuit are all off, and VT4 is turned on due to the high level of G4. At this time, UC of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT5 is on, UC is DC+ / 2, and when VT5 is off, UC is 0), UA is 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2 (when HA, HB, and HC are "011");

[0076] If HA, HB, HC are "001" (that is, the states of HA, HB, HC are 0, 0, 1 respectively), after passing through the signal shaping circuit, the signals HA1, HB1, HC1 are "110", DIR1 is "0", after passing through the commutation circuit, the waveform of S5 is a PWM signal with a duty cycle of d, S1, S2, S3, S4 are all low levels, S6 is high level, after passing through the drive circuit, the waveform of G5 is a PWM signal with a duty cycle of d, G1, G2, G3, G4 are all low levels, G6 is high level, when passing through the power main circuit, the power VT5 of the main circuit is modulated by the G5 signal and is in an alternating on-off action (when G5 is 1, VT5 is on, and when G5 is 0, VT5 is off), VT1, VT2, VT3, and VT4 of the power main circuit are all off, and VT6 is turned on due to the high level of G6. At this time, UC of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT5 is on, UC is DC+ / 2, and when VT5 is off, UC is 0), UB is 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2 (when HA, HB, and HC are "001");

[0077] When the motor reverses, DIR is 0; at this time,

[0078] If HA, HB, and HC are "010" (that is, the states of HA, HB, and HC are 0, 1, and 0, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "101", and DIR1 is "1". After passing through the commutation circuit, the waveform of S1 is a PWM signal with a duty cycle of d, S2, S3, S4, and S5 are all low levels, and S6 is high level. After passing through the drive circuit, the waveform of G1 is a PWM signal with a duty cycle of d, G2, G3, G4, and G5 are all low levels, and G6 is high level. When passing through the power main circuit, the power VT1 of the main circuit is modulated by the G1 signal and is in an alternating on-off action (when G1 is 1, VT1 is on, and when G1 is 0, VT1 is off), VT2, VT3, VT4, and VT5 of the power main circuit are all off, and VT6 is turned on due to the high level of G6. At this time, UA of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT1 is on, UA is DC+ / 2, and when VT1 is off, UA is 0), UB is 0, and UC is a linear decrease from DC+ / 2 to -DC+ / 2 (when HA, HB, and HC are "010");

[0079] If HA, HB, and HC are "011" (that is, the states of HA, HB, and HC are 0, 1, and 1, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "100", and DIR1 is "1". After passing through the commutation circuit, the waveform of S1 is a PWM signal with a duty cycle of d, S3, S4, S5, and S6 are all low levels, and S2 is high level. After passing through the drive circuit, the waveform of G1 is a PWM signal with a duty cycle of d, G3, G4, G5, and G6 are all low levels, and G2 is high level. When passing through the power main circuit, the power VT1 of the main circuit is modulated by the G1 signal and is in an alternating on-off action (when G1 is 1, VT1 is on, and when G1 is 0, VT1 is off), VT3, VT4, VT5, and VT6 of the power main circuit are all off, and VT2 is turned on due to the high level of G2. At this time, UA of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT1 is on, UA is DC+ / 2, and when VT1 is off, UA is 0), UC is 0, and UB is a linear increase from -DC+ / 2 to DC+ / 2 (when HA, HB, and HC are "011");

[0080] If HA, HB, HC are "001" (that is, the states of HA, HB, HC are 0, 0, 1 respectively), after passing through the signal shaping circuit, the signals HA1, HB1, HC1 are "110", DIR1 is "1", after passing through the commutation circuit, the waveform of S3 is a PWM signal with a duty cycle of d, S1, S4, S5, S6 are all low level, S2 is high level, after passing through the drive circuit, the waveform of G3 is a PWM signal with a duty cycle of d, G1, G4, G5, G6 are all low level, G2 is high level, when passing through the power main circuit, the power VT3 of the main circuit is modulated by the G3 signal and is in an alternating on-off action (when G3 is 1, VT3 is on, and when G3 is 0, VT3 is off), VT1, VT4, VT5, and VT6 of the power main circuit are all off, and VT2 is turned on due to the high level of G2. At this time, UB of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT3 is on, UB is DC+ / 2, and when VT3 is off, UB is 0), UC is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2 (when HA, HB, and HC are "001");

[0081] If HA, HB, and HC are "101" (that is, the states of HA, HB, and HC are 1, 0, and 1, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "010", and DIR1 is "1". After passing through the commutation circuit, the waveform of S3 is a PWM signal with a duty cycle of d, S1, S2, S5, and S6 are all low levels, and S4 is high level. After passing through the drive circuit, the waveform of G3 is a PWM signal with a duty cycle of d, G1, G2, G5, and G6 are all low levels, and G4 is high level. When passing through the power main circuit, the power VT3 of the main circuit is modulated by the G3 signal and is in an alternating on-off action (when G3 is 1, VT3 is on, and when G3 is 0, VT3 is off), VT1, VT2, VT5, and VT6 of the power main circuit are all off, and VT4 is turned on due to the high level of G4. At this time, UB of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT3 is on, UB is -DC+ / 2, and when VT3 is off, UB is 0), UA is 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2 (when HA, HB, and HC are "101");

[0082] If HA, HB, and HC are "100" (that is, the states of HA, HB, and HC are 1, 0, and 0, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "011", and DIR1 is "1". After passing through the commutation circuit, the waveform of S5 is a PWM signal with a duty cycle of d, S1, S2, S3, and S6 are all low levels, and S4 is high level. After passing through the drive circuit, the waveform of G5 is a PWM signal with a duty cycle of d, G1, G2, G3, and G6 are all low levels, and G4 is high level. When passing through the power main circuit, the power VT5 of the main circuit is modulated by the G5 signal and is in an alternating on-off action (when G5 is 1, VT5 is on, and when G5 is 0, VT5 is off), VT1, VT2, VT3, and VT6 of the power main circuit are all off, and VT4 is turned on due to the high level of G4. At this time, UC of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT5 is on, UC is DC+ / 2, and when VT5 is off, UC is 0), UA is 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2 (when HA, HB, and HC are "100");

[0083] If HA, HB, and HC are "110" (that is, the states of HA, HB, and HC are 1, 1, and 0, respectively), after passing through the signal shaping circuit, the signals HA1, HB1, and HC1 are "001", and DIR1 is "1". After passing through the commutation circuit, the waveform of S5 is a PWM signal with a duty cycle of d, S1, S2, S3, and S4 are all low levels, and S6 is high level. After passing through the drive circuit, the waveform of G5 is a PWM signal with a duty cycle of d, G1, G2, G3, and G4 are all low levels, and G6 is high level. When passing through the power main circuit, the power VT5 of the main circuit is modulated by the G5 signal and is in an alternating on-off action (when G5 is 1, VT5 is on, and when G5 is 0, VT5 is off), VT1, VT2, VT3, and VT4 of the power main circuit are all off, and VT6 is turned on due to the high level of G6. At this time, UC of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT5 is on, UC is DC+ / 2, and when VT5 is off, UC is 0), UB is 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2 (when HA, HB, and HC are "110");

[0084] Preferably, the commutation control logic circuit is as follows Figure 3As shown, it includes: S1-S6 logic control modules, each of which is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the logical operation of negation are HA1, HB1, and HC1 respectively, and the signal of DIR after the logical operation of negation is DIR1; wherein: S1 logic control module includes AND gates 1-6 and OR gate 1; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 receive signals DIR and PWM respectively; the two input ends of AND gate 3 are connected to the output ends of AND gate 1 and AND gate 2 respectively; the two input ends of AND gate 4 receive signals HA1 and HB respectively, and the two input ends of AND gate 5 receive signals DIR1 and PWM respectively; the two input ends of AND gate 6 are connected to the output ends of AND gate 4 and AND gate 5 respectively output terminal; the two input terminals of OR gate 1 are respectively connected to the output terminals of AND gate 3 and AND gate 6, and the output terminal of OR gate 1 outputs signal S1; S3 logic control module includes AND gates 7-12 and OR gate 2; the two input terminals of AND gate 7 receive signals HB and HC1 respectively, and the two input terminals of AND gate 8 receive signals DIR and PWM respectively; the two input terminals of AND gate 9 are respectively connected to the output terminals of AND gate 7 and AND gate 8; the two input terminals of AND gate 10 receive signals HB1 and HC respectively, and the two input terminals of AND gate 11 receive signals DIR1 and PWM respectively; the two input terminals of AND gate 12 are respectively connected to the output terminals of AND gate 10 and AND gate 11; the two input terminals of OR gate 2 are respectively connected to the output terminals of AND gate 9 and AND gate 12, and the output terminal of OR gate 2 outputs signal S3; S The logic control module includes AND gates 13-18 and OR gate 3; the two input ends of AND gate 13 receive signals HC and HA1 respectively, and the two input ends of AND gate 14 receive signals DIR and PWM respectively; the two input ends of AND gate 15 are connected to the output ends of AND gate 13 and AND gate 14 respectively; the two input ends of AND gate 16 receive signals HC1 and HA respectively, and the two input ends of AND gate 17 receive signals DIR1 and PWM respectively; the two input ends of AND gate 18 are connected to the output ends of AND gate 16 and AND gate 17 respectively; the two input ends of OR gate 3 are connected to the output ends of AND gate 15 and AND gate 18 respectively, and the output end of OR gate 3 outputs signal S5; the logic control module includes AND gates 19-24, OR gate 4; the two input ends of AND gate 19 receive signals HC1 and HA1 respectively, and the two input ends of AND gate 17 receive signals DIR1 and PWM respectively; the two input ends of AND gate 18 are connected to the output ends of AND gate 16 and AND gate 17 respectively; the two input ends of OR gate 3 are connected to the output ends of AND gate 15 and AND gate 18 respectively, and the output end of OR gate 3 outputs signal S5; The two input ends of AND gate 20 receive signals HC and HA1, and the two input ends of AND gate 20 receive signals DIR1 and ST respectively; the two input ends of AND gate 21 are connected to the output ends of AND gate 19 and AND gate 20 respectively; the two input ends of AND gate 22 receive signals HC1 and HA respectively, and the two input ends of AND gate 23 receive signals DIR and ST respectively; the two input ends of AND gate 24 are connected to the output ends of AND gate 22 and AND gate 23 respectively; the two input ends of OR gate 4 are connected to the output ends of AND gate 21 and AND gate 24 respectively, and the output end of OR gate 4 outputs signal S2; S4 logic control module includes AND gates 25-30 and OR gate 5; the two input ends of AND gate 25 receive signals HA and HB1 respectively, and the two input ends of AND gate 26 receive signals DIR1 and ST respectively;The two input ends of AND gate 27 are connected to the output ends of AND gate 25 and AND gate 26 respectively; the two input ends of AND gate 28 receive signals HA1 and HB respectively, and the two input ends of AND gate 29 receive signals DIR and ST respectively; the two input ends of AND gate 30 are connected to the output ends of AND gate 28 and AND gate 29 respectively; the two input ends of OR gate 5 are connected to the output ends of AND gate 27 and AND gate 30 respectively, and the output end of OR gate 5 outputs signal S4; S6 logic control module includes AND gates 31-36 and OR gate 6; the two input ends of AND gate 31 are connected to the output ends of AND gate 28 and AND gate 29 respectively; The two input ends of AND gate 32 receive signals HB and HC1, and the two input ends of AND gate 32 receive signals DIR1 and ST respectively; the two input ends of AND gate 33 are connected to the output ends of AND gate 31 and AND gate 32 respectively; the two input ends of AND gate 34 receive signals HB1 and HC respectively, and the two input ends of AND gate 35 receive signals DIR and ST respectively; the two input ends of AND gate 36 are connected to the output ends of AND gate 34 and AND gate 35 respectively; the two input ends of OR gate 6 are connected to the output ends of AND gate 33 and AND gate 36 respectively, and the output end of OR gate 6 outputs signal S6. At this time, signal ST takes 1. ;

[0085] Drive circuit such as Figure 4 As shown, it includes three IR2110 driver chips, each of which is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit; after power-on, the SD pin of each IR2110 driver chip is connected to a low level. Figure 5 shown.

[0086] Example 2

[0087] A specific embodiment 2 of the present invention improves the brushless DC motor commutation control circuit in embodiment 1 by adding an overcurrent protection circuit and a fault counting and latching circuit to form a Figure 6 The brushless DC motor commutation control circuit with overcurrent protection is shown in the figure to realize overcurrent protection during the commutation control process.

[0088] An overcurrent protection circuit, when the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is a low level; otherwise, the output overcurrent protection signal is a high level; the overcurrent protection signal is input to the phase-changing control logic circuit, and when the overcurrent protection signal is a low level, the phase-changing control logic signals S2, S4 and S6 are pulled down.

[0089] The fault counting and latching control circuit receives the overcurrent protection signal, and each time the overcurrent protection signal is detected to switch from a high level to a low level, the count value stored in the fault counting and latching circuit is increased by 1; when the count value does not reach the set count threshold, the first locking signal output by the fault counting and latching circuit is latched as a low level, and the second locking signal is latched as a high level; when the count value reaches the set count threshold, the first locking signal output by the fault counting and latching circuit is latched as a high level, and the second locking signal is latched as a low level; the first locking signal is input to the driving circuit, and when the first latching signal is a high level, the driving signal is simultaneously locked to a low level; the second locking signal is input to the phase-changing control logic circuit, and when the second locking signal is a low level, the phase-changing control logic signals S2, S4 and S6 are pulled down. Preferably, the initial value of the count value is zero; when the fault counting and latching circuit receives a reset signal, the count value is reset.

[0090] The overcurrent protection circuit is used to protect against single instantaneous overcurrent faults and can automatically recover. The overcurrent tolerance times are set by the fault counting and latching circuit, which can realize continuous protection when the overcurrent tolerance times exceed the limit. After the fault is eliminated, the fault protection can be cleared through the fault clearing signal. No special controller chip is required, which simplifies the control system and improves system reliability.

[0091] like Figure 6 As shown, the overcurrent protection circuit receives the overcurrent signal OV1 output by the power main circuit. After the above judgment, the overcurrent protection circuit outputs the overcurrent protection signal OV2, and simultaneously inputs the signal OV2 to the phase-changing control logic circuit and the fault counting and latching circuit. After the above processing, the fault counting and latching circuit outputs the first locking signal Lock1 to the driving circuit and the second latching signal Lock2 to the phase-changing control logic circuit. The fault counting and latching circuit also receives a clearing signal Clear for clearing the count value.

[0092] At this time, the signal ST in the commutation control logic circuit is obtained by performing an AND operation on the second latch signal Lock2 and the overcurrent protection signal OV2, such as Figure 7 The commutation control logic circuit shown;

[0093] For example, the overcurrent protection circuit is as follows: Figure 8As shown: the overcurrent protection circuit is composed of resistors R1-R5 and an NPN transistor K1; wherein, one end of the resistor R2 is connected to one end of the resistor R4, one end of the resistor R3 is connected to one end of the resistor R5, the other end of the resistor R2 is connected to the other end of the resistor R3 and receives the signal OV1, the other end of the resistor R4 is connected to the other end of the resistor R5 and is grounded; one end of the resistor R2 is also connected to one end of the resistor R3 and one end of the resistor R1, one end of the resistor R1 is connected to the base of the NPN transistor K1, the emitter of the transistor K1 is grounded, the collector of the transistor K1 is connected to the positive electrode of the power supply after passing through the resistor R5, and at the same time, the collector of the transistor K1 outputs the overcurrent protection signal OV2.

[0094] Exemplarily, the fault counting and latch control circuit is as follows Fig. 9 As shown; it consists of two 74LS161, 74LS151, a NOT gate, a resistor R30, a resistor R31, a transistor K2, a selection switch and three pull-up resistors. Among them, the D0-D3 terminals, CEP terminals and DET terminals of the two 74LS161s are all connected to the positive pole of the power supply (such as 5V), the MR terminals of the two 74LS161s are connected, and the PE terminals of the two 74LS161s are connected. The CP terminal of one 74LS161 receives the overcurrent protection signal OV2, Q0-Q3 correspond to D0-D3 in 74LS151 respectively, the TC terminal is connected to the CP terminal of the other 74LS161, and Q0-Q3 of the other 74LS161 corresponds to D4-D7 in 74LS151 respectively. The OUT terminal of 74LS151 outputs the signal Lock1, and the signal Lock1 is reversed to output the signal Lock2. Lock2 is connected to the PE terminals of the two 74LS161s; A, B, and C of 74LS151 are respectively connected to the three ports of the selection switch and one end of the pull-up resistor, and the other end of the pull-up resistor is connected to the positive pole of the power supply. The MR terminals of the two 74LS161s are connected to the collector of the transistor K2, and the collector is also connected to the positive power supply via the resistor R30. The emitter of the transistor K2 is grounded, and the base of the transistor K2 is connected to one end of the resistor R31. The other end of the resistor R31 receives the Clear signal. The circuit latches the count value threshold to the 74LS151 by selecting the open, and receives the signal of OV2 switching from high level to low level through the two 74LS161s. Each time it is received, the count value recorded in the two 74LS161s is increased by 1; when the count value recorded by the two 74LS161s is the same as the count value threshold latched in the 74LS151, the first lock signal Lock1 is latched as a high level and the second lock signal Lock2 is latched as a low level. The count value in the 74LS161 can also be cleared by the Clear signal.

[0095] At this time, the driving circuit includes three IR2110 driving chips, each of which is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit; the SD pin of each IR2110 driving chip is controlled by the first locking signal Lock1, and the circuit diagram is as shown in FIG. Fig.10 shown.

[0096] In the above-mentioned brushless DC motor commutation control circuit with overcurrent protection, if an instantaneous overcurrent occurs during the operation of the motor, the overcurrent protection circuit output signal OV2 will be low level, OV2 passes through the commutation control logic circuit, and pulls down the drive signals S4, S6, and S2 at the same time, thereby pulling down the lower bridge arm drive signals G4, G6, and G2 of the power main circuit, blocking the lower bridge arm to ensure the safety of the power main circuit. After the lower bridge arm is blocked, the current of the power main circuit will decrease, and the overcurrent protection circuit output signal OV2 will gradually become high level. OV2 passes through the commutation control logic circuit, and releases the drive signals S4, S6, and S2 from the forced low state at the same time, thereby restoring the lower bridge arm drive signals G4, G6, and G2 of the power main circuit to normal. At this point, the power main circuit completes an overcurrent protection and recovery. The output signal OV2 of the overcurrent protection circuit is simultaneously input to the fault counting and latching circuit. Each time an overcurrent occurs, the fault counting and latching circuit count values ​​will increase. When the count value reaches the set value, the lock signal Lock2 output by the fault counting and latching circuit will be constantly latched as a low level, and the signals S4, S6, and S2 output by the commutation control logic circuit will be pulled down at the same time, thereby pulling down the lower bridge arm drive signals G4, G6, and G2 of the power main circuit, blocking the lower bridge arm. At the same time, the lock signal Lock1 output by the fault counting and latching circuit will be constantly latched as a high level, and the SD end of the drive circuit will be pulled up, and the drive signals G1~G6 will be blocked at the same time as a low level, and the upper and lower bridge arms will be blocked at the same time. Lock1 and Lock2 realize the double insurance of overcurrent protection, ensuring reliable protection of the power main circuit. After troubleshooting, the fault can be cleared by changing the Clear signal from high to low.

[0097] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0098] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A brushless DC motor commutation control circuit, characterized in that: include: A commutation control logic circuit is used to receive and process a direction control signal, a PWM signal, a position Hall signal output by a brushless DC motor, and a signal after a logical negation operation of the position Hall signal and the direction control signal, and generate a commutation control logic signal adapted to a PWM modulation mode of a power main circuit; A driving circuit, used for amplifying the commutation control logic signal to obtain a driving signal; The power main circuit is used to generate a brushless DC motor input control signal based on the drive signal, and use the brushless DC motor input control signal to drive the brushless DC motor to work; The commutation control logic circuit includes: S1-S6 logic control modules, each logic control module is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the logical negation operation are HA1, HB1, and HC1 respectively, and the signals of DIR after the logical negation operation are DIR1; wherein: The S1 logic control module includes AND gates 1-6 and OR gate 1; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 receive signals DIR and PWM respectively; the two input ends of AND gate 3 are connected to the output ends of AND gate 1 and AND gate 2 respectively; the two input ends of AND gate 4 receive signals HA1 and HB respectively, and the two input ends of AND gate 5 receive signals DIR1 and PWM respectively; the two input ends of AND gate 6 are connected to the output ends of AND gate 4 and AND gate 5 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 3 and AND gate 6 respectively, and the output end of OR gate 1 outputs signal S1; The S3 logic control module includes AND gates 7-12 and an OR gate 2; the two input ends of the AND gate 7 receive signals HB and HC1 respectively, and the two input ends of the AND gate 8 receive signals DIR and PWM respectively; the two input ends of the AND gate 9 are connected to the output ends of the AND gate 7 and the AND gate 8 respectively; the two input ends of the AND gate 10 receive signals HB1 and HC respectively, and the two input ends of the AND gate 11 receive signals DIR1 and PWM respectively; the two input ends of the AND gate 12 are connected to the output ends of the AND gate 10 and the AND gate 11 respectively; the two input ends of the OR gate 2 are connected to the output ends of the AND gate 9 and the AND gate 12 respectively, and the output end of the OR gate 2 outputs a signal S3; The S5 logic control module includes AND gates 13-18 and an OR gate 3; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 receive signals DIR and PWM respectively; the two input ends of the AND gate 15 are connected to the output ends of the AND gates 13 and 14 respectively; the two input ends of the AND gate 16 receive signals HC1 and HA respectively, and the two input ends of the AND gate 17 receive signals DIR1 and PWM respectively; the two input ends of the AND gate 18 are connected to the output ends of the AND gate 16 and the AND gate 17 respectively; the two input ends of the OR gate 3 are connected to the output ends of the AND gate 15 and the AND gate 18 respectively, and the output end of the OR gate 3 outputs a signal S5; The S2 logic control module includes AND gates 19-24 and an OR gate 4; the two input ends of the AND gate 19 receive signals HC and HA1 respectively, and the two input ends of the AND gate 20 receive signals DIR1 and ST respectively; the two input ends of the AND gate 21 are connected to the output ends of the AND gate 19 and the AND gate 20 respectively; the two input ends of the AND gate 22 receive signals HC1 and HA respectively, and the two input ends of the AND gate 23 receive signals DIR and ST respectively; the two input ends of the AND gate 24 are connected to the output ends of the AND gate 22 and the AND gate 23 respectively; the two input ends of the OR gate 4 are connected to the output ends of the AND gate 21 and the AND gate 24 respectively, and the output end of the OR gate 4 outputs a signal S2; The S4 logic control module includes AND gates 25-30 and an OR gate 5; the two input ends of the AND gate 25 receive signals HA and HB1 respectively, and the two input ends of the AND gate 26 receive signals DIR1 and ST respectively; the two input ends of the AND gate 27 are connected to the output ends of the AND gate 25 and the AND gate 26 respectively; the two input ends of the AND gate 28 receive signals HA1 and HB respectively, and the two input ends of the AND gate 29 receive signals DIR and ST respectively; the two input ends of the AND gate 30 are connected to the output ends of the AND gate 28 and the AND gate 29 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 27 and the AND gate 30 respectively, and the output end of the OR gate 5 outputs a signal S4; The S6 logic control module includes AND gates 31-36 and an OR gate 6; the two input ends of the AND gate 31 receive signals HB and HC1 respectively, and the two input ends of the AND gate 32 receive signals DIR1 and ST respectively; the two input ends of the AND gate 33 are connected to the output ends of the AND gate 31 and the AND gate 32 respectively; the two input ends of the AND gate 34 receive signals HB1 and HC respectively, and the two input ends of the AND gate 35 receive signals DIR and ST respectively; the two input ends of the AND gate 36 are connected to the output ends of the AND gate 34 and the AND gate 35 respectively; the two input ends of the OR gate 6 are connected to the output ends of the AND gate 33 and the AND gate 36 respectively, and the output end of the OR gate 6 outputs a signal S6; If the brushless DC motor commutation control circuit includes an overcurrent protection circuit and a fault counting and latching circuit, the signal ST is obtained by performing an AND logic operation on the second latch signal and the overcurrent protection signal; otherwise, the signal ST is 1.

2. The brushless DC motor commutation control circuit according to claim 1, characterized in that: When the PWM modulation mode is the H-PWM_L-ON mode, the corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR in the commutation control logic circuit and the commutation control logic signals S1-S6 is: If HA, HB, HC, and DIR are "1011" or "0100", the waveform of signal S1 is a PWM signal, signals S2, S3, S4, and S5 are low level, and signal S6 is high level; If HA, HB, HC, and DIR are "1001" or "0110", the waveform of signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low level, and signal S2 is high level; If HA, HB, HC, and DIR are "1101" or "0010", the waveform of signal S3 is a PWM signal, signals S1, S4, S5, and S6 are all low level, and signal S2 is high level; If HA, HB, HC, and DIR are "0101" or "1010", the waveform of signal S3 is a PWM signal, signals S1, S2, S5, and S6 are all low level, and signal S4 is high level; If HA, HB, HC, and DIR are "0111" or "1000", the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S6 are all low level, and signal S4 is high level; If HA, HB, HC, and DIR are "0011" or "1100", the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low level, and signal S6 is high level; When DIR is 1, the motor rotates forward, and when DIR is 0, the motor rotates reversely.

3. The brushless DC motor commutation control circuit according to claim 2, characterized in that: The signals S1, S3, and S5 are respectively used to control the opening or closing of the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; the signals S2, S4, and S6 are respectively used to control the opening or closing of the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on one bridge arm, VT3 and VT6 are on one bridge arm, and VT5 and VT2 are on one bridge arm.

4. The brushless DC motor commutation control circuit according to claim 3, characterized in that: If the waveform of S1 is a PWM signal, signals S2, S3, S4, and S5 are all low levels, and signal S6 is high level, then the input control signal UA of the A-phase brushless DC motor is an alternating change between DC+ / 2 and 0: when the PWM signal is high level, it is DC+ / 2, and when the PWM signal is low level, it is 0; the input control signal UB of the B-phase brushless DC motor is 0; the input control signal UC of the C-phase brushless DC motor is a linear decrease from DC+ / 2 to -DC+ / 2; If the waveform of signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low level, and signal S2 is high level, then UA is an alternating change between DC+ / 2 and 0; UC is 0; UB is a linear increase from -DC+ / 2 to DC+ / 2; If the waveform of signal S3 is a PWM signal, signals S1, S4, S5, and S6 are all low level, and signal S2 is high level, then UB is an alternating change between DC+ / 2 and 0, UC is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2; If the waveform of signal S3 is a PWM signal, signals S1, S2, S5, and S6 are all low level, and signal S4 is high level, then UB is an alternating change between DC+ / 2 and 0, UA is 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2; If the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S6 are all low level, and signal S4 is high level, then UC is an alternating change between DC+ / 2 and 0, UA is 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2; If the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low levels, and signal S6 is high level, then UC is an alternating change between DC+ / 2 and 0, UB is 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2.

5. The brushless DC motor commutation control circuit according to claim 4, characterized in that: The commutation control circuit also includes an overcurrent protection circuit. When the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is a low level; otherwise, the output overcurrent protection signal is a high level; The overcurrent protection signal is input to the phase switching control logic circuit. When the overcurrent protection signal is at a low level, the phase switching control logic signals S2, S4 and S6 are pulled low.

6. The brushless DC motor commutation control circuit according to claim 5, characterized in that: The commutation control circuit also includes a fault counting and latching circuit, The fault counting and latching control circuit receives the overcurrent protection signal, and each time the overcurrent protection signal is detected to switch from a high level to a low level, the count value stored in the fault counting and latching circuit is increased by 1; When the count value does not reach the set count threshold, the first locking signal output by the fault counting and latching circuit is latched as a low level, and the second locking signal is latched as a high level; When the count value reaches the set count threshold, the first locking signal output by the fault counting and latching circuit is latched as a high level, and the second locking signal is latched as a low level; The first locking signal is input to the driving circuit, and when the first locking signal is at a high level, the driving signal is simultaneously locked to a low level; The second locking signal is input to the phase switching control logic circuit. When the second locking signal is at a low level, the phase switching control logic signals S2, S4 and S6 are pulled low.

7. The brushless DC motor commutation control circuit according to claim 6, characterized in that: The initial value of the count value is zero; When the fault counting and latching circuit receives a reset signal, the count value is reset.

8. The brushless DC motor commutation control circuit according to claim 6 or 7, characterized in that: The driving circuit includes three IR2110 driving chips, each IR2110 driving chip is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit; If the brushless DC motor commutation control circuit includes an overcurrent protection circuit and a fault counting and latching circuit, the SD pin of each IR2110 driver chip is connected to a low level; otherwise, the SD pin of each IR2110 driver chip is controlled by the first locking signal.

9. The brushless DC motor commutation control circuit according to claim 1, characterized in that: The circuit also includes a signal shaping circuit for performing the negation logic operation on the position Hall signal and the direction control signal output by the brushless DC motor.

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