FPGA with built-in interconnect module including heterogeneous selectors

Abstract

The present application discloses an FPGA with a built-in interconnection module including a heterogeneous selector, and relates to FPGA technology. The interconnection modules inside the FPGA are no longer all built-in symmetrical selectors, but at least one interconnection module has a built-in heterogeneous selector. The heterogeneous selector includes not only a first selection circuit but also a second selection circuit. When an input signal is connected to an interconnection input point of the interconnection module and fanned out to multiple interconnection output points, part of the conduction path is realized by the first selection circuit, and part of the conduction path is realized by the second selection circuit. Since the second selection circuit is not connected to a pull-up circuit, it almost does not generate a load demand. Therefore, a larger number of fan-outs can be achieved by using a driving pull-down circuit with a smaller driving capability, thereby reducing the area and power consumption occupied by the driving pull-down circuit, and also reducing the waste of area and power consumption.

Description

Technical Field

[0001] The present invention relates to the field of FPGA, and in particular to an FPGA with a built-in interconnection module including a heterogeneous selector. Background Art

[0002] FPGA (Field Programmable Gate Array) contains a large number of resource modules such as CLB, BRAM, DSP, IOB, etc. These resource modules are surrounded by interconnection modules INT. The input and output of each resource module are connected to other resource modules through the corresponding interconnection module INT, thus forming a wiring architecture that is expanded to the entire FPGA.

[0003] For the most commonly used wiring architecture for FPGAs, please refer to Figure 1 Each interconnection module INT has a rectangular structure and includes interconnection input points E_IN, S_IN, W_IN, and N_IN in four directions, so that signal input in each direction can be obtained. Each interconnection module INT also includes interconnection output points E_OUT, S_OUT, W_OUT, and N_OUT in four directions, so that signals can be output in each direction. Inside the interconnection module INT, different interconnection input points and interconnection output points are connected via switch boxes.

[0004] Each interconnect output point is connected to the interconnect input points in all directions, and the signal received by one of the interconnect input points is fanned out to the interconnect output point through code flow control. Figure 1 A schematic diagram showing that the interconnection input points E_IN, S_IN, W_IN, and N_IN in four directions are connected to the interconnection output point E_OUT through the first selection circuit and the buffer circuit U0. The first selection circuit can fan out the signal of one of the interconnection input points to E_OUT according to the four control signals C0, C1, C2, and C3 received, thereby achieving the design goal. In addition, the output end of the first selection circuit connected to each interconnection output point of the interconnection module INT is also connected to the pull-up circuit PU, thereby ensuring that even if any interconnection input point connected to it is not selected, there is still a default output without the circuit floating phenomenon, that is, the y0 point is neither 0 nor 1.

[0005] The input signal inside the FPGA is input to an interconnection input point of an interconnection module INT and fans out to the corresponding interconnection output point. The input signal is connected to a driving pull-down circuit. When the input signal is to drive 0, the driving pull-down circuit connected to the input signal pulls down the path that is turned on inside the interconnection module INT to 0, thereby realizing signal fan-out. However, as described above, a pull-up circuit is provided at each interconnection output point of the interconnection module INT. The pull-up circuit serves as a load for driving the pull-down circuit. In order to ensure that the signal 0 is transmitted to the interconnection output point in time, the driving capability of the input signal connected to the driving pull-down circuit needs to be large enough to avoid being affected by the pull-up circuit. Moreover, in actual operation, when the input signal is input to the interconnection input point of each interconnection module INT, it can fan out to multiple interconnection output points of the interconnection module INT. Therefore, it is necessary to ensure that the driving capability of the driving pull-down circuit connected to the input signal meets the high load requirements during multiple fan-outs during design. Therefore, in order to ensure normal driving, the driving capability of the pull-down circuit often needs to be redundantly designed according to the upper limit of the fan-out number. This not only requires a larger circuit area, but also causes a considerable waste of area and power consumption when not so many fan-out numbers are used in actual use. Summary of the invention

[0006] In view of the above problems and technical requirements, the applicant proposes an FPGA with a built-in interconnection module including a heterogeneous selector. The technical solution of the application is as follows:

[0007] An FPGA having an interconnection module including a heterogeneous selector built in, wherein at least one interconnection module in the FPGA has a built-in heterogeneous selector to realize interconnection between an interconnection input point and an interconnection output point, the interconnection output point in the interconnection module is connected to a first selection circuit in the heterogeneous selector, and at least one interconnection output point is also connected to a second selection circuit in the heterogeneous selector;

[0008] An interconnection input point connected to an input signal forms multiple conduction paths with multiple interconnection output points through a heterogeneous selector at the same time, the input signal is grounded through a driving pull-down circuit, and there is at least one conduction path that is controlled by the second code stream segment through the second selection circuit, and the remaining conduction paths are controlled by the first code stream segment through the first selection circuit;

[0009] The input end of the first selection circuit is connected to the interconnection input point, the output end of the first selection circuit is connected to the pull-up power supply through the pull-up circuit, and the output end of the first selection circuit is also connected to the corresponding interconnection output point through the buffer circuit;

[0010] The input end of the second selection circuit is connected to the interconnection input point, and the output end of the second selection circuit is connected to the corresponding interconnection output point through the buffer circuit.

[0011] A further technical solution is that, among the multiple conduction paths formed by the interconnection module for simultaneously fanning out the input signal to multiple interconnection output points, the number of conduction paths realized by the first selection circuit does not exceed a quantity threshold N1.

[0012] A further technical solution is that the driving capability of the pull-down circuit connected to the input signal is designed according to the load requirement of the pull-up circuit in the N1 conduction paths realized via the first selection circuit.

[0013] A further technical solution is that when the input signal is connected to an interconnection input point of an interconnection module, the number of conduction paths for transmitting the input signal implemented by the first selection circuit inside the interconnection module does not exceed a number threshold N1;

[0014] Alternatively, the input signal is simultaneously connected to the interconnection input points of multiple interconnection modules, and the input signal is simultaneously fanned out to multiple interconnection output points of multiple interconnection modules through multiple conductive paths formed inside each interconnection module, then the total number of conductive paths for transmitting the input signal implemented by the first selection circuit inside all interconnection modules connected to the input signal does not exceed the number threshold N1.

[0015] A further technical solution is that the number of input terminals included is (2 P-1 , 2 P ] The first code stream segment received by the first selection circuit within the range includes P code stream bits; the second code stream segment received by the second selection circuit including Q input terminals includes Q code stream bits;

[0016] Among the N2 conductive paths formed by the interconnection module for simultaneously fanning out input signals to multiple interconnection output points, N1 conductive paths are implemented by the first selection circuit, and the remaining N2-N1 conductive paths are implemented by the second selection circuit.

[0017] A further technical solution is that a method for forming multiple conduction paths for simultaneously fanning out input signals to multiple interconnected output points comprises:

[0018] The first selection circuit inside the interconnection module is preferentially used to implement multiple conduction paths for simultaneously fanning out input signals. When the number of conduction paths implemented by the first selection circuit reaches N1, the second selection circuit inside the interconnection module is used to implement the remaining conduction paths.

[0019] Its further technical solution is that a structure in which the first selection circuit and the second selection circuit are simultaneously connected at an interconnected output point includes: the output end of the first selection circuit and the output end of the second selection circuit are both connected to the input end of the buffer circuit, the output end of the buffer circuit is connected to the interconnected output point, and the output end of the first selection circuit is also connected to the pull-up power supply through the pull-up circuit; some interconnected input points in the interconnected module are connected to the various input ends of the first selection circuit, and the remaining interconnected input points are connected to the various input ends of the second selection circuit.

[0020] A further technical solution is that a first selection circuit connected to the same interconnected output point is controlled by a first code stream segment to conduct a path between one of the input terminals and the output terminal to form a conduction path realized by the first selection circuit, and a second selection circuit is controlled by a second code stream segment to control all paths between the input terminals and the output terminals to be non-conductive;

[0021] Alternatively, the second selection circuit connected to the same interconnected output point is controlled by the second code stream segment to connect a path between one of the input terminals and the output terminal to form a conduction path implemented by the second selection circuit, and the first selection circuit is controlled by the first code stream segment to control all paths between the input terminals and the output terminals to be non-conductive.

[0022] A further technical solution is that all interconnection output points of the interconnection module are respectively connected to the first selection circuit and the second selection circuit at the same time;

[0023] Alternatively, some interconnection output points of the interconnection module are respectively connected to the first selection circuit and the second selection circuit at the same time, and the remaining interconnection output points are respectively only connected to the first selection circuit.

[0024] A further technical solution is that the second selection circuit is constructed based on one or more three-state buffers, the input end of each three-state buffer is connected to an interconnection input point in the interconnection module, the output end of the three-state buffer is connected to the input end of the buffer circuit, and the second code stream segment of the second selection circuit includes the code stream bits of each three-state buffer;

[0025] The first code stream segment and the second code stream segment are both included in the control code stream of the FPGA. When the conduction paths implemented by the first selection circuit and / or the second selection circuit are different, the total number of code stream bits included in the control code stream of the FPGA remains unchanged.

[0026] The beneficial technical effect of the present application is: the present application discloses an FPGA with a built-in interconnection module including a heterogeneous selector. The interconnection modules inside the FPGA are no longer all built-in symmetrical selectors, but at least one interconnection module has a built-in heterogeneous selector. The heterogeneous selector includes not only a first selection circuit but also a second selection circuit. When an input signal is connected to the interconnection input point of the interconnection module and fanned out to multiple interconnection output points, part of the conduction path is realized by the first selection circuit, and part of the conduction path is realized by the second selection circuit. Since the second selection circuit is not connected to the pull-up circuit, it almost does not generate a load demand. Therefore, a larger number of fan-outs can be achieved by using a driving pull-down circuit with a smaller driving capability, thereby reducing the area and power consumption occupied by the driving pull-down circuit, and also reducing the waste of area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of an existing interconnection module INT realizing connection between an interconnection input point and an interconnection output point through a built-in symmetric selector.

[0028] Figure 2 is based on Figure 1 Schematic diagram of the existing interconnection module INT of this structure fanning out the input signal IN to various interconnection output points.

[0029] Figure 3 This is a schematic diagram of an embodiment of the present application, in which the input signal IN is fanned out to various interconnection output points using the heterogeneous selector built into the interconnection module INT in the FPGA of the present application.

[0030] Figure 4 It is a schematic diagram of fanning out an input signal IN to interconnect output points of multiple interconnect modules in one embodiment of the present application. DETAILED DESCRIPTION

[0031] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0032] The present application discloses an FPGA with a built-in interconnection module including a heterogeneous selector. The structures of all interconnection modules INT in a conventional FPGA are as described in the background technology. The interconnection module INT has a built-in symmetric selector to realize the interconnection between the interconnection input point and the interconnection output point. The symmetric selector includes a plurality of first selection circuits. The connection diagram of each first selection circuit with the interconnection input point and the interconnection output point of the interconnection module INT is as shown in FIG. Figure 1 As shown, each input terminal of the first selection circuit is connected to each interconnection input point of the interconnection module INT respectively. Figure 1Taking the example that the four input ends of the first selection circuit are respectively connected to the interconnection input points E_IN, S_IN, W_IN, and N_IN in four directions of the interconnection module INT, the output end of the first selection circuit is connected to the input end of the buffer circuit U0, and the output end of the buffer circuit U0 is connected to an interconnection output point of the interconnection module INT. Figure 1 Take the output end of the buffer circuit U0 connected to the interconnection output point E_OUT of the interconnection module INT as an example. The output end of the first selection circuit is also connected to the pull-up power supply through the pull-up circuit PU.

[0033] In order to avoid the difference between the paths connected to different interconnection input points, the first selection circuit in the existing general interconnection module INT generally adopts a symmetrical selection structure. Figure 1 A typical structure of a first selection circuit including four input terminals is shown, wherein the interconnected input point E_IN is connected to one end of the switch tube M3 through the switch tube M1, the interconnected input point S_IN is connected to one end of the switch tube M3 through the switch tube M2, and the other end of the switch tube M3 is connected to the output end of the first selection circuit. The interconnected input point W_IN is connected to one end of the switch tube M6 through the switch tube M4, the interconnected input point N_IN is connected to one end of the switch tube M6 through the switch tube M5, and the other end of the switch tube M6 is connected to the output end of the first selection circuit. The switch tubes M1 and M4 are both controlled by the control signal C0, the switch tubes M2 and M5 are both controlled by the control signal C1, the switch tube M3 is controlled by the control signal C2, and the switch tube M6 is controlled by the control signal C3. When the first selection circuit has more input terminals, those skilled in the art can expand its circuit structure in the same way, and this application will not repeat it.

[0034] Thus, the first selection circuit forms a symmetrical selection structure. Therefore, when the control code stream generated after layout and routing is used to control the four control signals of the first selection circuit, only two code stream bits are actually used, such as Figure 1 As shown, the first code stream bit generates the control signal C0 and is inverted to generate the control signal C1, and the second code stream bit generates the control signal C2 and is inverted to generate the control signal C3.

[0035] Therefore, thanks to the symmetrical selection structure of the first selection circuit, when the number of input terminals of the first selection circuit exceeds 2 P-1 and not more than 2 P When the first code stream segment received by the first selection circuit only needs to contain P code stream bits, a conductive path can be selected from the path formed by the first selection circuit as the conductive path, and the signal of the interconnection input point connected by the conductive path can be fanned out to the interconnection output point connected by the conductive path.

[0036] However, in the present application, there is at least one interconnection module INT in the FPGA that does not adopt this general structure. The improved interconnection module INT does not use a symmetric selector inside, but uses a heterogeneous selector to realize the interconnection between the interconnection input point and the interconnection output point. Compared with the general symmetric selector, the heterogeneous selector includes a second selection circuit in addition to the first selection circuit. The interconnection output point in the interconnection module is connected to the first selection circuit in the heterogeneous selector, and there is at least one interconnection output point that is also connected to the second selection circuit in the heterogeneous selector. The first selection circuit in the heterogeneous selector has the same structure as the first selection circuit in the general INT. The input end of the first selection circuit is connected to the interconnection input point, and the output end of the first selection circuit is connected to the pull-up power supply through the pull-up circuit. The output end of the first selection circuit is also connected to the corresponding interconnection output point through the buffer circuit U0. The first selection circuit is controlled by the code stream bit of the first code stream segment Ctrl1 to control the on and off of each path formed internally. The input end of the second selection circuit in the improved interconnection module INT is connected to the interconnection input point of the interconnection module INT, and the output end of the second selection circuit is connected to the corresponding interconnection output point through a buffer circuit. The second selection circuit is controlled by the code stream bit of the second code stream segment Ctrl2 to control the on and off of each path formed internally.

[0037] In one embodiment, all interconnect modules INT in the FPGA have a second selection circuit added inside and a built-in heterogeneous selector. Alternatively, only some interconnect modules INT in the FPGA have a second selection circuit added inside and a built-in heterogeneous selector, and the remaining interconnect modules INT still use a conventional structure with a built-in symmetric selector.

[0038] Based on the built-in symmetric selector of the conventional interconnection module INT, when an input signal IN is connected to the interconnection input point W_IN of the interconnection module INT and needs to be fanned out to three interconnection output points N_OUT, E_OUT, and S_OUT at the same time, the circuit structure diagram is as follows: Figure 2 As shown. The interconnect input point W_IN is connected to the input signal IN, and the input signal IN is also grounded through the driving pull-down circuit PD. The interconnect input point W_IN connected to the input signal IN forms multiple conduction paths with multiple interconnect output points N_OUT, E_OUT, and S_OUT through the built-in symmetric selector, and these three conduction paths are all controlled by the first code stream segment through the first selection circuit connected to the three interconnect output points. For example Figure 2In the structure, when the input signal IN is 0, the driving pull-down circuit PD connected to the input signal IN needs to pull all the conducting paths to 0 within a set time. Then, the driving capability of the driving pull-down circuit PD connected to the input signal IN needs to at least meet the load requirements of the pull-up circuits in all the conducting paths. Moreover, in actual applications, the number of conducting paths connected to the actual interconnection input point W_IN varies due to the influence of layout and wiring. Therefore, the driving capability of the driving pull-down circuit PD is generally designed according to the upper limit of the conducting paths. For example, in Figure 2 In the structure, the interconnected input point W_IN can form at most four conduction paths with the four interconnected output points respectively. Therefore, in the design stage, the driving capability of the pull-down circuit PD connected to the input signal IN is generally designed according to the load requirements of the pull-up circuits in all four conduction paths to ensure that the signal can be accurately transmitted. However, in the use stage, the interconnected input point W_IN may only form two conduction paths with the two interconnected output points. In this case, the driving capability of the pull-down circuit PD is actually redundant, which not only occupies too much unnecessary area, but also causes additional power consumption waste. Moreover, the example of this application only takes a single INT module including four interconnected output points as an example. The number of interconnected input points and interconnected output points of the INT structure in the actual FPGA is more, and the number of INT modules is also large. The waste of area and power consumption caused by this is very considerable.

[0039] In the present application, based on the built-in heterogeneous selector of the improved interconnection module INT, the interconnection input point connected to the input signal forms multiple conduction paths with multiple interconnection output points through the heterogeneous selector at the same time, and there is at least one conduction path controlled by the second code stream segment Ctrl2 via the second selection circuit, and the remaining conduction paths are controlled by the first code stream segment Ctrl1 via the first selection circuit. Figure 2 In the example of FIG. 1 , the connection diagram of the heterogeneous selector implemented based on the improved interconnect module INT in the FPGA of the present application is as follows: Figure 3 As shown. Figure 2 and Figure 3 It can be seen that, in the same case, not all the conduction paths are implemented by the first selection circuit, but some of the conduction paths are implemented by the second selection circuit. Figure 3 In the embodiment, the first selection circuit connected to the interconnection output point N_OUT is controlled by the first code stream segment Ctrl(1) to select the conduction path between the interconnection input point W_IN and the interconnection output point N_OUT, the first selection circuit connected to the interconnection output point E_OUT is controlled by the first code stream segment Ctrl(2) to select the conduction path between the interconnection input point W_IN and the interconnection output point E_OUT, and the second selection circuit connected to the interconnection output point S_OUT is controlled by the second code stream segment Ctrl2 to select the conduction path between the interconnection input point W_IN and the interconnection output point S_OUT.

[0040] Similarly, in order to avoid the circuit floating phenomenon at the interconnection output point, when a second selection circuit is added inside the interconnection module INT to connect the interconnection output point, the original first selection circuit is not cancelled, but a second selection circuit is added on the basis of the original first selection circuit. Figure 3 Take the interconnection output point S_OUT connecting the first selection circuit and the second selection circuit at the same time as an example. The structure of connecting the first selection circuit and the second selection circuit at the same time at an interconnection output point includes: the output end of the first selection circuit and the output end of the second selection circuit are both connected to the input end of the buffer circuit U0, the output end of the buffer circuit U0 is connected to the interconnection output point, the output end of the first selection circuit is also connected to the pull-up power supply through the pull-up circuit, and some interconnection input points in the interconnection module INT are connected to the various input ends of the first selection circuit, and the remaining interconnection input points are connected to the various input ends of the second selection circuit. Under this structure, the phenomenon of circuit floating can be avoided, that is, the occurrence of Figure 3 The y0 point at S_OUT in the circuit is neither 0 nor 1, and at the same time, there is no pull-up circuit in the conduction path implemented by the second selection circuit, and the input ends of the first selection circuit and the second selection circuit are respectively connected to the interconnected input point.

[0041] The first selection circuit connected to the same interconnected output point is controlled by the first code stream segment, and conducts a path between one of the input terminals and the output terminal to form a conduction path realized by the first selection circuit, and the second selection circuit is controlled by the second code stream segment, and controls all paths between the input terminals and the output terminals to be non-conductive. Alternatively, the second selection circuit connected to the same interconnected output point is controlled by the second code stream segment, and conducts a path between one of the input terminals and the output terminal to form a conduction path realized by the second selection circuit, and the first selection circuit is controlled by the first code stream segment, and controls all paths between the input terminals and the output terminals to be non-conductive. That is, the first selection circuit and the second selection circuit connected to the same interconnected output point only form one conduction path in total.

[0042] So Figure 3For example, based on this structure, the conduction path realized by the second selection circuit is not connected to the pull-up circuit, and almost no load demand is generated. Therefore, when the input signal IN is 0, the driver pull-down circuit PD connected to the input signal IN needs to pull all conduction paths down to 0 within the set time, and the driving capability of the driver pull-down circuit PD connected to the input signal IN does not need to meet the load requirements of the pull-up circuits in all conduction paths, but only needs to meet the load requirements of the pull-up circuits in the conduction paths realized by the first selection circuit, that is, it only needs to meet the load requirements of the pull-up circuits in some conduction paths. For example, compare Figure 2 and Figure 3 , in Figure 2 The driving capability of the pull-down circuit PD must meet the load requirements of the pull-up circuits in the three conduction paths. Figure 3 The driving capability of the medium drive pull-down circuit PD only needs to meet the load requirements of the pull-up circuits in the two conduction paths, thereby reducing the driving capability requirements of the drive pull-down circuit PD, thereby reducing the waste of area and power consumption caused by having to use a drive pull-down circuit PD with a large driving capability.

[0043] In an interconnection module INT with a built-in heterogeneous selector, all interconnection output points can be connected to the first selection circuit and the second selection circuit at the same time. Or only some interconnection output points of the interconnection module are connected to the first selection circuit and the second selection circuit at the same time, and the remaining interconnection output points are only connected to the first selection circuit. For example, Figure 3 In the embodiment, the interconnection output point S_OUT is connected to both the first selection circuit and the second selection circuit, but the interconnection output point N_OUT is only connected to the first selection circuit, and the interconnection output point E_OUT is also only connected to the first selection circuit.

[0044] In one embodiment, the second selection circuit is constructed based on one or more tri-state buffers, the input end of each tri-state buffer is connected to an interconnection input point in the interconnection module, and the output end of the tri-state buffer is connected to the input end of the buffer circuit U0. Figure 3 Taking a tri-state buffer as an example, when the second selection circuit has more tri-state buffers, the input ends of the multiple tri-state buffers are connected to different interconnection input points, and the output ends of the multiple tri-state buffers are all connected to the input end of the buffer circuit U0.

[0045] The second code stream segment Ctrl2 of the second selection circuit includes the code stream bits of each tri-state buffer, and therefore the second code stream segment received by the second selection circuit including Q input terminals includes Q code stream bits, for example Figure 3 In the embodiment, the second selection circuit has only one input terminal for connecting to W_IN, and its second code stream segment Ctrl2 includes one code stream bit.

[0046] Compared with the first selection circuit and the second selection circuit, the second selection circuit is implemented based on a three-state buffer and occupies a slightly larger area than the first selection circuit. Moreover, when the same number of input terminals are included, the code stream bits required by the first selection circuit are much less than the code stream bits required by the second selection circuit. Therefore, in actual application, many second selection circuits will not be added inside the interconnection module INT of the FPGA, but only a limited number of second selection circuits will be added, thereby reducing the area and power consumption caused by driving the pull-down circuit PD while also reducing the additional area and power consumption caused by the second selection circuit. In the structural design stage, it is determined in which interconnection modules INT and at which interconnection output points the second selection circuit needs to be added. When the FPGA is manufactured, the structure is fixed and cannot be changed. Once the structure and number of the second selection circuits are fixed, the number of code stream bits required by the second code stream segment required by the second selection circuit is determined, and the first code stream segment and the second code stream segment are both included in the control code stream of the FPGA. Therefore, the length of the control code stream generated after the FPGA is laid out and wired is fixed. When the conduction paths implemented by the first selection circuit and / or the second selection circuit are different, the total number of code stream bits included in the control code stream of the FPGA remains unchanged, that is, no matter how many second selection circuits are ultimately required to implement the number of conduction paths, the total length of the control code stream remains unchanged, and only the content of each code stream segment is affected.

[0047] As described above, based on the FPGA of the structure of the present application, using the second selection circuit to realize a partial conduction path can reduce the demand for the driving capability of the driver pull-down circuit PD, but in the structural design stage, it is still necessary to predetermine the driving capability of the driver pull-down circuit PD. Then, the driving capability of the driver pull-down circuit connected to the input signal can be designed in advance according to the load requirements of the pull-up circuit in the N1 conduction paths realized by the first selection circuit. Then, during layout and routing, in the multiple conduction paths formed by the interconnection module for simultaneously fanning out the input signal to multiple interconnected output points, the number of conduction paths realized by the first selection circuit does not exceed the number threshold N1, thereby ensuring that the driving capability of the driver pull-down circuit PD can always meet the load requirements. However, the number of conduction paths actually used to simultaneously fan out the input signal to multiple interconnected output points may exceed N1.

[0048] Under the restriction that the number of conduction paths realized by the first selection circuit does not exceed the number threshold N1, there can be multiple combinations of which conduction paths are realized by the first selection circuit and which are realized by the second selection circuit. In one embodiment, considering that the first selection circuit requires fewer code stream bits under the same number of input terminals, and the number of second selection circuits is also relatively limited, the first selection circuit should be used as much as possible. Assuming that a total of N2 conduction paths for simultaneously fanning out input signals to multiple interconnected output points need to be formed through the interconnection module, when N2≤N1, all N2 conduction paths are realized through the first selection circuit. When N2>N1, within the limit range of the number of conduction paths realized by the first selection circuit, N1 of the conduction paths are realized through the first selection circuit, and then the remaining N2-N1 conduction paths are realized through the second selection circuit. Moreover, when all N2 conduction paths are realized through the first selection circuit, the driving capability of the pull-down circuit PD is exceeded.

[0049] In order to achieve this function, during layout and routing, the first selection circuit inside the interconnection module is preferentially used to implement multiple conduction paths for simultaneously fanning out the input signal IN. When the number of conduction paths implemented by the first selection circuit reaches N1, the second selection circuit inside the interconnection module is used to implement the remaining conduction paths.

[0050] In each of the above embodiments, the input signal may be connected to only one interconnection input point of the interconnection module, such as Figure 3 As shown, the input signal is fanned out to the interconnection output point of the interconnection module only through the conductive path inside one interconnection module. The number of conductive paths implemented by the first selection circuit inside the interconnection module for transmitting the input signal IN does not exceed the number threshold N1;

[0051] Alternatively, the input signal can be connected to the interconnection input points of multiple interconnection modules at the same time, and the input signal can be fanned out to multiple interconnection output points of multiple interconnection modules at the same time through multiple conductive paths formed inside each interconnection module. Then the total number of conductive paths for transmitting the input signal IN implemented by all interconnection module INT parts connected to the input signal IN via the first selection circuit does not exceed the number threshold N1.

[0052] for example Figure 4In the embodiment, the driving capability of the driving pull-down circuit PD connected to the input signal IN is designed in advance according to the load requirements of the pull-up circuits in the four conduction paths realized by the first selection circuit. The input signal IN is simultaneously connected to the interconnection input points in the three interconnection modules, including: connecting to the interconnection input point S_IN in the interconnection module 1, connecting to the interconnection input point W_IN in the interconnection module 2, and connecting to the interconnection input point W_IN in the interconnection module 3. In this example, in the layout and routing stage, six conduction paths for simultaneously fanning out the input signal IN are implemented according to the following process: the conduction path between the interconnection input point S_IN and the interconnection output point N_OUT in the interconnection module 1 is implemented by the first selection circuit, the conduction path between the interconnection input point S_IN and the interconnection output point W_OUT in the interconnection module 1 is implemented by the first selection circuit, the conduction path between the interconnection input point W_IN and the interconnection output point N_OUT in the interconnection module 2 is implemented by the first selection circuit, the conduction path between the interconnection input point W_IN and the interconnection output point E_OUT in the interconnection module 2 is implemented by the first selection circuit, the conduction path between the interconnection input point W_IN and the interconnection output point S_OUT in the interconnection module 2 is implemented by the second selection circuit, and the conduction path between the interconnection input point W_IN and the interconnection output point E_OUT in the interconnection module 3 is implemented by the second selection circuit. Figure 4 In FIG. 4 , four conduction paths realized by the first selection circuit are indicated by solid lines, and two conduction paths realized by the second selection circuit are indicated by dot-dash lines.

Claims

1. An FPGA having a built-in interconnect module including a heterogeneous selector, characterized in that: There is at least one interconnection module in the FPGA with a built-in heterogeneous selector to realize the interconnection between the interconnection input point and the interconnection output point, the interconnection output point in the interconnection module is connected to the first selection circuit in the heterogeneous selector, and there is at least one interconnection output point that is also connected to the second selection circuit in the heterogeneous selector; An interconnection input point connected to an input signal forms multiple conduction paths with multiple interconnection output points through the heterogeneous selector at the same time, the input signal is grounded through a driving pull-down circuit, and there is at least one conduction path that is controlled by the second code stream segment through the second selection circuit, and the remaining conduction paths are controlled by the first code stream segment through the first selection circuit; The input end of the first selection circuit is connected to the interconnection input point, the output end of the first selection circuit is connected to the pull-up power supply through the pull-up circuit, and the output end of the first selection circuit is also connected to the corresponding interconnection output point through the buffer circuit; The input end of the second selection circuit is connected to the interconnection input point, and the output end of the second selection circuit is connected to the corresponding interconnection output point through a buffer circuit; In the structural design stage, the driving capability of the driving pull-down circuit connected to the input signal is designed according to the load requirement of the pull-up circuit in N1 conduction paths realized by the first selection circuit; during layout and routing, among the multiple conduction paths formed by the interconnection module for simultaneously fanning out the input signal to multiple interconnection output points, the number of conduction paths realized by the first selection circuit does not exceed the number threshold N1; When a total of N2 conduction paths are required to be formed through the interconnection module for simultaneously fanning out the input signal to multiple interconnection output points, when N2≤N1, all N2 conduction paths are implemented through the first selection circuit; when N2>N1, within the limit of the number of conduction paths implemented through the first selection circuit, N1 of the conduction paths are implemented through the first selection circuit, and the remaining N2-N1 conduction paths are implemented through the second selection circuit, and when all N2 conduction paths are implemented through the first selection circuit, the driving capability of the pull-down circuit PD is exceeded.

2. The FPGA according to claim 1, characterized in that: The input signal is connected to an interconnection input point of an interconnection module, and the number of conduction paths for transmitting the input signal implemented by the first selection circuit inside the interconnection module does not exceed a number threshold N1; Alternatively, the input signal is simultaneously connected to the interconnection input points of multiple interconnection modules, and the input signal is simultaneously fanned out to multiple interconnection output points of multiple interconnection modules through multiple conductive paths formed inside each interconnection module, then the total number of conductive paths for transmitting the input signal implemented by the first selection circuit inside all interconnection modules connected to the input signal does not exceed the number threshold N1.

3. The FPGA according to claim 1, characterized in that: The number of input ports included is (2 P-1 , 2 P ] The first code stream segment received by the first selection circuit within the range includes P code stream bits; the second code stream segment received by the second selection circuit including Q input terminals includes Q code stream bits.

4. The FPGA according to claim 1, characterized in that: The structure in which the first selection circuit and the second selection circuit are simultaneously connected at one interconnection output point comprises: the output end of the first selection circuit and the output end of the second selection circuit are both connected to the input end of the buffer circuit, the output end of the buffer circuit is connected to the interconnection output point, and the output end of the first selection circuit is also connected to the pull-up power supply through the pull-up circuit; some interconnection input points in the interconnection module are connected to the respective input ends of the first selection circuit, and the remaining interconnection input points are connected to the respective input ends of the second selection circuit.

5. The FPGA according to claim 4, characterized in that: The first selection circuit connected to the same interconnected output point is controlled by the first code stream segment to conduct a path between one of the input terminals and the output terminal to form a conduction path realized by the first selection circuit, and the second selection circuit is controlled by the second code stream segment to control all paths between the input terminals and the output terminals to be non-conductive; Alternatively, a second selection circuit connected to the same interconnected output point is controlled by the second code stream segment to conduct a path between one of the input terminals and the output terminal to form a conduction path implemented by the second selection circuit, and the first selection circuit is controlled by the first code stream segment to control all paths between the input terminals and the output terminals to be non-conductive.

6. The FPGA according to claim 4, characterized in that: All interconnection output points of the interconnection module are respectively connected to the first selection circuit and the second selection circuit at the same time; Alternatively, some interconnection output points of the interconnection module are respectively connected to the first selection circuit and the second selection circuit at the same time, and the remaining interconnection output points are respectively only connected to the first selection circuit.

7. The FPGA according to claim 5, characterized in that: The second selection circuit is constructed based on one or more three-state buffers, the input end of each three-state buffer is connected to an interconnection input point in the interconnection module, the output end of the three-state buffer is connected to the input end of the buffer circuit, and the second code stream segment of the second selection circuit includes the code stream bits of each three-state buffer; The first code stream segment and the second code stream segment are both included in the control code stream of the FPGA. When the conduction paths implemented by the first selection circuit and / or the second selection circuit are different, the total number of code stream bits included in the control code stream of the FPGA remains unchanged.

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