A bus-controlled clock delay circuit
By designing a bus-controlled clock delay circuit in an integrated circuit, and using the bus control signal to adjust the clock signal delay online, the problem of insufficient clock delay control accuracy in traditional methods is solved, and a high linearity and real-time clock signal is achieved Delay control.
Patent Information
- Application Number
- CN202310875774.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-17
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2043-07-17
AI Technical Summary
In integrated circuit design, traditional clock delay control methods have uncontrollable deviations from the design expected value due to process parameters uncertainty and accuracy problems. Especially when the integrated circuit scale increases, precise control of clock delay is carried out. It becomes more difficult.
A bus-controlled clock delay circuit is designed, and the delay time of the clock signal is adjusted online by connecting multiple delay units and OR gates in serial, using external bus control signals to realize accurate delay control of the clock signal. The delay unit is composed of an RC delay circuit and a MOS tube. By changing the position of the set data bit in the bus control signal, the output of the delay unit at each stage is adjusted, and the clock signal delay time at the final output end is realized.
It realizes accurate adjustment and linear control of the clock signal delay time, with high linearity and real-timeness, and can adjust the delay time of the clock signal according to actual needs, and is suitable for different clock frequency ranges.
Smart Images
Figure CN116979936B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a bus-controlled clock delay circuit. Background Art
[0002] In integrated circuits, digital circuit modules often require a clock signal to determine when the internal circuit elements perform specific operations, and sometimes use clock signals to synchronize data. Clock signal delay control is a key link in integrated circuit design. Designers usually need to adjust the delay time of the clock signal from the signal source to the signal terminal to ensure that the timing of the clock transition edge reaching the receiving circuit unit meets the design requirements.
[0003] Traditional clock delay control methods generally use the delay of the interconnected transmission line itself and the method of serially connecting buffers. The delay of the transmission line can be calculated by combining the resistance and capacitance electrical parameters of different metal layers provided by the process manufacturer with the relevant calculation formula of RC delay, or it can be simulated together with the buffer through design simulation software. In the chip design stage, quantitative transmission line delay control can be achieved by adjusting the width and length of the transmission line and the specifications and number of the buffer.
[0004] However, in the process of semiconductor chip manufacturing, due to the uncertainty of process parameters and the problem of process control accuracy, there will be electrical parameter deviations between the electrical parameters of the finished semiconductor chip and the design values. Generally speaking, according to Moore's Law, the feature size of semiconductor process tape-out is getting smaller and smaller, which makes the electrical characteristics of transmission lines and transistors caused by tiny process deviations change more and more, resulting in a large error between the performance of integrated circuit products and the original design goals. In this way, the use of traditional clock delay control methods will cause uncontrollable deviations between the actual clock delay of the integrated circuit after tape-out and the expected design value. Moreover, with the advancement of technology, the scale of integrated circuits is getting larger and larger, and the length of the clock line is inevitably getting longer and longer, which increases the difficulty of accurately controlling the clock delay. Summary of the invention
[0005] The problem solved by the present invention is to overcome the deficiencies of the prior art and to propose a method for online control of clock signal delay, which can more accurately adjust the clock delay time to an expected value according to actual application requirements.
[0006] The technical solution of the present invention is:
[0007] The present invention discloses a bus-controlled clock delay circuit, comprising: a clock input end, a bus control input end, a final output end, N delay units and an OR gate; wherein the delay unit comprises a receiving end, a transmitting end, a control end and an output end; the delay units of each level are connected in series through the receiving end and the transmitting end, the receiving end of the delay unit of the first level is connected to the clock input end, the clock input end is connected to an external clock, and the transmitting end of the delay unit of the last level is suspended; the bus control input end comprises N data bits, and the control end of the delay unit is respectively connected to each data bit of the bus control input end; N is an integer greater than or equal to 2;
[0008] The output ends of the N delay units are sequentially connected to the input poles of the OR gates, and the output poles of the OR gates are cascaded with the input poles of the OR gates at the subsequent stages, so that the final output end outputs one signal;
[0009] The bus control input terminal receives an external bus control signal, and by changing the position of the high-level data bit in the bus control signal, online control of the delay time of the clock signal output by the final output terminal is achieved; the bus control signal is used to quantitatively adjust the clock signal delay.
[0010] Furthermore, in the above-mentioned delay circuit, the delay unit includes: a first inverter, a second inverter, a resistor, and a capacitor; wherein the input electrode of the first inverter serves as a receiving end of the delay unit to receive an external clock signal, and the output electrode of the first inverter is connected to one end of the resistor; the input electrode of the second inverter is connected to the other end of the resistor and one end of the capacitor, and the output electrode of the second inverter serves as a sending end of the delay unit; the other end of the capacitor is grounded, and the resistor and the capacitor form an RC delay circuit.
[0011] Furthermore, in the above-mentioned delay circuit, the delay unit also includes a first NMOS transistor, a second NMOS transistor and a PMOS transistor; wherein the drain of the first NMOS transistor and the source of the PMOS transistor are connected to the output of the second inverter; the source of the first NMOS transistor is connected to the drain of the second NMOS transistor and the drain of the PMOS transistor, and serves as the output end of the delay unit; the source of the second NMOS transistor is grounded.
[0012] Furthermore, in the above-mentioned delay circuit, the delay unit also includes a third inverter; the input pole of the third inverter receives an external control signal and is connected to the gate of the first NMOS transistor, and the output pole of the third inverter is connected to the gate of the PMOS transistor and the gate of the second NMOS transistor.
[0013] Furthermore, in the above-mentioned delay circuit, when the control signal received by the delay unit is at a high level, the first NMOS transistor is turned on, the PMOS transistor is turned on, and the second NMOS transistor is turned off; the clock signal output by the output pole of the second inverter passes through the first NMOS transistor and the PMOS transistor and is output at the output end of the delay unit.
[0014] Furthermore, in the above delay circuit, when the control signal received by the delay unit is at a low level, the first NMOS transistor is turned off, the PMOS transistor is turned off, and the second NMOS transistor is turned on; the output end of the delay unit is grounded at this time and outputs a 0 signal.
[0015] Furthermore, in the above-mentioned delay circuit, in the bus control signal, one bit is set to a high level as required, and the remaining bits are set to a low level; only the output end of the delay unit at the first level whose control signal input is a high level outputs the delayed clock signal, and the output ends of the delay units at the remaining levels output a 0 signal; the signals output from the output ends of the delay units at each level pass through the OR gate circuit, and a logical OR operation is performed to output the delayed target clock signal.
[0016] Furthermore, in the above delay circuit, if the number of the output terminals of the delay units of all stages is less than the number of input terminals of the first stage OR gate, the input terminals of the redundant first stage OR gates are set to 0.
[0017] Furthermore, in the above delay circuit, in the delay unit, a plurality of inverters may be connected in series between the first inverter and the second inverter.
[0018] Furthermore, in the above delay circuit, the transmitting end of the delay unit at the last stage can be grounded via a resistor with a resistance value greater than 1K.
[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0020] 1) The present invention can flexibly adjust the delay time realized by the single-stage delay circuit by changing the specifications of the MOS tubes inside the first inverter and the second inverter and the specifications of the resistors and capacitors;
[0021] 2) The delay unit of the present invention is designed in accordance with the principle diagram and the layout. When the circuit state is determined, the clock delay time from the receiving end of the delay unit at each level to the sending end of the delay unit is substantially equal. The clock delay is adjusted by the circuit of the present invention with the characteristic of high linearity.
[0022] 3) The present invention can change the position of the data bit set to 1 in the bus control signal at any time according to actual needs, and adjust a bus-controlled clock delay circuit to output clock signals with different delay times online in real time. The clock delay adjustment by the circuit of the present invention has the characteristic of good real-time performance;
[0023] 4) The function and performance of the present invention are not restricted by the clock frequency within the range of clock frequencies that a bus-controlled clock delay circuit can pass. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 is a schematic diagram of the circuit structure of a first-stage delay unit according to an embodiment of the present invention;
[0025] Figure 2 is a schematic structural diagram of a global circuit according to an embodiment of the present invention;
[0026] Figure 3 FIG. 4 is a timing diagram of a clock signal according to an embodiment of the present invention. DETAILED DESCRIPTION
[0027] In the field of integrated circuit design, traditional clock delay control methods are mostly implemented by using the delay of the interconnected transmission lines themselves and the method of serial buffers. Usually, the delay time of the delay circuit after the chip is taped out is different from the design value, and it is impossible to adjust the clock delay time online in real time after the chip is taped out.
[0028] In the technical solution of the present invention, by designing delay circuit modules that can be connected in series, and configuring OR gates to collect the signals output by the delay circuit modules at each level into one output, and at the same time introducing external bus digital control signals to control the working state of each level of delay circuit modules, the circuit is finally implemented to adjust the delay time of the clock signal in the transmission process in real time with a certain step size.
[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0030] The invention discloses a bus-controlled clock delay circuit, comprising: a clock input end, a bus control input end, a final output end, N delay units and an OR gate; wherein the delay unit comprises a receiving end, a transmitting end, a control end and an output end; the delay units of each level are connected in series through a receiving end and a transmitting end, the receiving end of the first-level delay unit is connected to the clock input end, the clock input end is connected to an external clock, and the transmitting end of the last-level delay unit is suspended; the bus control input end comprises N data bits, and the control end of the delay unit is respectively connected to each data bit of the bus control input end; and N is an integer greater than or equal to 2.
[0031] Since the delay units at each level are connected in series, the delay time generated by the clock at the sending end of each level of delay unit is linearly accumulated. The bus control input receives the external bus control signal, and by changing the position of the data bit set to 1 in the bus control signal, the output end of each level of delay unit can be controlled to output the clock signal after each level of delay or a 0 signal.
[0032] The output ends of N delay units are connected to the input pole of the OR gate in sequence, and the output pole of the OR gate is cascaded with the input pole of the OR gate of the next stage, so that the final output end outputs one signal. In the specific implementation, one bit of the bus control signal is set to 1 as required, and the other bits are set to 0; only the output end of the first-stage delay unit with the control signal input of 1 outputs the delayed clock signal, and the output ends of the delay units of the remaining stages output 0 signals; in this way, the delayed clock signal is logically ORed with other 0 signals to output the delayed target clock signal.
[0033] By changing the position of the data bit set to 1 in the bus control signal, the delay time of the clock signal output from the final output end can be controlled online, and finally the function of the bus control signal to quantitatively adjust the clock signal delay can be realized.
[0034] Preferably, the delay unit comprises: a first inverter, a second inverter, a resistor, and a capacitor; wherein the input electrode of the first inverter serves as a receiving end of the delay unit to receive an external clock signal, and the output electrode of the first inverter is connected to one end of the resistor; the input electrode of the second inverter is connected to the other end of the resistor and one end of the capacitor, and the output electrode of the second inverter serves as a sending end of the delay unit; the other end of the capacitor is grounded, and the resistor and the capacitor form an RC delay circuit.
[0035] Preferably, the delay unit further includes a first NMOS transistor, a second NMOS transistor and a PMOS transistor; wherein the drain of the first NMOS transistor and the source of the PMOS transistor are connected to the output of the second inverter; the source of the first NMOS transistor is connected to the drain of the second NMOS transistor and the drain of the PMOS transistor, and serves as the output end of the delay unit; the source of the second NMOS transistor is grounded.
[0036] Preferably, the delay unit further includes a third inverter; the input of the third inverter receives an external control signal and is connected to the gate of the first NMOS transistor, and the output of the third inverter is connected to the gate of the PMOS transistor and the gate of the second NMOS transistor.
[0037] Preferably, when the control signal received by the delay unit is 1, the first NMOS transistor is turned on, the PMOS transistor is turned on, and the second NMOS transistor is turned off; the clock signal output by the output electrode of the second inverter passes through the first NMOS transistor and the PMOS transistor and is output at the output end of the delay unit.
[0038] Preferably, when the control signal received by the delay unit is 0, the first NMOS transistor is turned off, the PMOS transistor is turned off, and the second NMOS transistor is turned on; the output end of the delay unit is grounded at this time and outputs a 0 signal.
[0039] Optionally, in the delay unit, more inverters may be connected in series between the first inverter and the second inverter.
[0040] Optionally, the transmitting end of the last-stage delay unit may be grounded via a resistor having a resistance greater than 1K.
[0041] Optionally, in the delay unit, more inverters may be connected in series between the first inverter and the second inverter;
[0042] Optionally, the delay unit may not include a resistor or a capacitor;
[0043] Optionally, the number of cascaded OR gates can be varied, such as one, two, three, etc.;
[0044] Optionally, if the number of output terminals of the delay units of all stages is less than the number of input terminals of the first-stage OR gate, the input terminals of the redundant first-stage OR gates are set to 0.
[0045] Example
[0046] A bus-controlled clock delay circuit of this embodiment is mainly composed of a delay unit and an OR gate. The number of the delay units is greater than or equal to 2. For the purpose of simplifying the description, Figure 1 Only the circuit structure diagram of the first-stage delay unit in this embodiment is shown. The delay unit includes: a first inverter I1, a second inverter I2, a third inverter I3, a first NMOS transistor M1, a second NMOS transistor M2, a PMOS transistor M3, a resistor R1 and a capacitor C1.
[0047] The input terminal of the first inverter I1 is used as the receiving terminal of the delay unit and is suitable for receiving the clock signal. Specifically, Figure 1 The clock signal CLK[0] sent by the receiving signal source I0 is connected to one end of the resistor R1 through the output electrode of the first inverter I1;
[0048] The input electrode of the second inverter I2 is connected to the other end of the resistor R1 and one end of the capacitor C1, and the output electrode of the second inverter I2 serves as the sending end of the delay unit; the other end of the capacitor C1 is grounded, and the resistor R1 and the capacitor C1 form an RC delay circuit.
[0049] like Figure 1As shown, the clock signal CLK[0] enters the delay unit from the receiving end of the delay unit, and firstly undergoes phase inversion after passing through the first inverter I1, and generates a certain delay, and the delay time is set to △t1; then it is delayed by the RC delay circuit composed of the resistor R1 and the capacitor C1, and the delay time is set to △t2; then it passes through the second inverter I2, and the phase is reversed again, and a delay time of △t3 is generated. Generally, the design values of △t1 and △t3 are equal; at the same time, the transmission lines between the above components will also cause the delay of the clock signal, which is set to △t4; as shown Figure 1 As shown, the final delay unit transmitting end outputs the delayed clock signal CLK[1]. Let △T represent the delay time of the clock signal from the delay unit receiving end to the current stage delay unit transmitting end. In this embodiment, the total delay time of the clock signal CLK[1] compared to the clock signal CLK[0] is △T=△t1+△t2+△t3+△t4.
[0050] △T is the minimum step size of the clock delay adjustment of the present invention. The design and value of △T should be determined in combination with the frequency of the clock signal that needs delay adjustment. Generally speaking, the higher the clock signal frequency, the smaller △T should be designed. When the circuit state of the delay unit is determined, the △T of each level of delay unit can be regarded as a fixed value.
[0051] In other embodiments, the delay unit may not include a resistor or a capacitor. In this case, the time required for the clock to be transmitted from the receiving end of the delay unit to the sending end of the delay unit, i.e., ΔT, is mainly determined by the inverter;
[0052] In other embodiments, more inverters may be connected in series between the first inverter and the second inverter in the delay unit. The total number of inverters connected in series between the delay unit receiving end and the delay unit sending end needs to be an even number so that the phase of the clock signal output by the delay unit sending end is consistent with the phase of the clock signal received by the delay unit receiving end;
[0053] For the inverter, the delay of the clock signal is mainly determined by the width and length of the MOS tube; for the RC circuit, the delay of the clock signal mainly depends on the product of the resistance and capacitance, which is also called the RC time constant; the delay of the transmission line is determined by the length of the transmission line and the parasitic resistance and capacitance on the line; in actual circuit design, it is also necessary to consider the impact of other factors such as temperature changes and power supply noise on signal transmission delay. Those skilled in the art generally use circuit simulation tools or chip simulation software to design circuit elements to achieve a given clock delay. The software usage and debugging methods are well known to those skilled in the art and will not be repeated here.
[0054] refer to Figure 1, the drain of the first NMOS transistor M1 and the source of the PMOS transistor M3 are connected to the output of the second inverter I2; the source of the first NMOS transistor M1 is connected to the drain of the second NMOS transistor M2 and the drain of the PMOS transistor M3, and serves as the output of the delay unit. At this time, the circuit structure formed by the drain of the first NMOS transistor M1 and the PMOS transistor M3 in parallel is usually called a "transmission gate". Such a "transmission gate" design has a wider voltage dynamic range than a single NMOS or PMOS when transmitting signals, and its working principle is well known to those skilled in the art;
[0055] Continue to refer Figure 1 , the external control signal CTRL[1] is a digital level signal, including logic 1 (high level) and logic 0 (low level). The input of the third inverter I3 receives the control signal CTRL[1] and is connected to the gate of the first NMOS transistor M1; the third inverter I3 receives the control signal CTRL[1] and outputs a signal CTRL_N[1] which is the opposite of its logic; the output of the third inverter I3 is connected to the gate of the PMOS transistor M3 and the gate of the second NMOS transistor M2. The source of the second NMOS transistor is grounded;
[0056] Continue to refer Figure 1 When the control signal CTRL[1] received by the delay unit is 1, the first NMOS transistor M1 in the delay unit is turned on, the PMOS transistor M3 is turned on, the second NMOS transistor M2 is turned off, and the output pole of the second inverter I2, that is, the sending end of the delay unit of this stage, is connected to the output end of the delay unit of this stage. At this time, the signal OUT[1] output from the output end of the delay unit of this stage is the output signal of the clock signal CLK[1] output by the second inverter I2 after passing through the "transmission gate" formed by the first NMOS transistor M1 and the PMOS transistor M3. CLK[1] will also experience a certain delay T during this transmission process. offset , when the circuit state is determined, the T of each delay unit offset Can be considered as a fixed value.
[0057] Similarly, when the control signal CTRL[1] received by the delay unit is 0, the first NMOS transistor M1 in the delay unit is turned off, the PMOS transistor M3 is turned off, and the second NMOS transistor M2 is turned on. The output electrode of the second inverter I2, i.e., the transmitting end of the delay unit of this stage, is cut off from the output end of the delay unit of this stage. At the same time, the output end of the delay unit of this stage is grounded through the second NMOS transistor M2, and the OUT[1] signal outputted by the output end of the delay unit of this stage is 0.
[0058] Figure 2 FIG. 1 is a schematic diagram of the structure of the global circuit of an embodiment of the present invention. In this embodiment, the number of delay units is 4. To make the description more concise, Figure 2 Only the first and second delay units in this embodiment are shown, and each delay unit is connected in series through the delay unit receiving end and the delay unit sending end. The first delay unit receiving end is suitable for receiving the original clock signal CLK[0], and the first delay unit sending end outputs the clock signal CLK[1] after the delay of △T; the second delay unit receiving end receives the CLK[1] signal and then delays it by △T, and then outputs the CLK2 signal from the delay unit sending end to the third delay unit receiving end; the last delay unit sending end (the fourth level in this embodiment) is suspended. In other embodiments, the last delay unit sending end can be grounded through a large resistance, and the typical value of the resistance is greater than 1KΩ.
[0059] In other embodiments, the number of delay units may be different from that in this embodiment, but the structure of the delay units connected in series and the delay calculation method are consistent therewith. It can be concluded that the delay time of the clock signal CLK[K] sent by the transmitting end of the K-th level (K is a positive integer, K is not greater than the number of delay units) delay unit compared to the clock signal CLK[0] at the receiving end of the first level delay unit is: K×△T.
[0060] Continue to refer Figure 2 , the output ends of all delay units are connected to the input poles of the OR gates in sequence, and the output poles of these OR gates are cascaded with the input poles of the OR gates of the subsequent stage, finally realizing a bus-controlled clock delay circuit with only one final output end.
[0061] In other embodiments, the form of the OR gate can be varied, such as a four-input OR gate, an eight-input OR gate, etc.; the number of cascaded OR gates can also be varied, such as one stage, two stages, three stages, etc.; if the number of output terminals of the delay units of all stages is less than the number of input poles of the first-stage OR gate, the input poles of the redundant first-stage OR gates are set to 0.
[0062] The control signal of the delay unit input to the next stage is high, and the control signal of the delay unit input to the previous stage is low, forming a parallel bus control signal. In this embodiment, because a total of four delay units are included, the bus control signal is CTRL[4:1]. In order for the bus-controlled clock delay circuit of the present invention to work normally, it is necessary to set one bit of the bus control signal to 1, and the remaining bits need to be set to 0. Only the output end of the first-stage delay unit with the control signal input of 1 outputs the delayed clock signal, and the output ends of the remaining delay units output 0 signals.
[0063] To make the explanation more intuitive, Figure 3 Schematic diagram of the timing of the clock signal in this embodiment. Before time t1, the bus control signal is "1111", at which time the OUT[1], OUT[2], OUT[3] and OUT[4] signals are the original clock signal CLK[0] and are delayed by T offset, △T+T offset , 2×△T+T offset 、3×△T+T offset After time t1, the bus control signal is set to "0100", that is, only the control signal CTRL[3] received by the third-stage delay unit is set to 1, and OUT[3] is still the original clock signal CLK[0] delayed by 2×△T+T offset The clock signal after the OUT[1], OUT[2], and OUT[4] signals are changed to 0. The OUT[1], OUT[2], OUT[3], and OUT[4] signals are logically ORed through the OR gate circuit, so that the FOUT signal outputted from the final output terminal is consistent with the OUT[3] signal. Note that since the transmission and operation of digital signals in the OR gate circuit also consumes time, there will be a certain delay between the FOUT signal and the OUT[3] signal, which can be ignored when the clock frequency is low.
[0064] In this embodiment, after time t1, the bus-controlled clock delay circuit is in a normal working mode, and the bus control signal is set to "1111" before time t1 only for the convenience of describing the present invention. In other embodiments, the initial bus control signal before time t1 can be set to "0000", and the FOUT signal outputted by the final output terminal is 0 before time t1.
[0065] In other embodiments, by changing the position of the data bit set to 1 in the bus control signal, the output end of the delay unit of a specific level can be controlled to output the delayed clock signal, and the output ends of the delay units of the remaining levels can output a 0 signal, and the delay time of the clock signal output by the final output end can be controlled online. Specifically, if you want to make the circuit delay time x×△T+T offset , where x is a positive integer not less than 1 and not greater than the total number of delay units, then it is only necessary to set the xth bit (starting from the least significant bit as the first bit) of the bus control signal to 1.
[0066] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A bus-controlled clock delay circuit, characterized in that: include: A clock input terminal, a bus control input terminal, a final output terminal, N delay units and an OR gate; wherein the delay unit includes a receiving terminal, a transmitting terminal, a control terminal and an output terminal; the delay units at each level are connected in series through the receiving terminal and the transmitting terminal, the receiving terminal of the delay unit of the first level is connected to the clock input terminal, the clock input terminal is connected to an external clock, and the transmitting terminal of the delay unit of the last level is suspended; the bus control input terminal includes N data bits, and the control terminal of the delay unit is respectively connected to each data bit of the bus control input terminal; N is an integer greater than or equal to 2; The output ends of the N delay units are sequentially connected to the input poles of the OR gates, and the output poles of the OR gates are cascaded with the input poles of the OR gates at the subsequent stages, so that the final output end outputs one signal; The bus control input terminal receives an external bus control signal, and by changing the position of the high-level data bit in the bus control signal, the delay time of the clock signal output by the final output terminal is controlled online; the bus control signal is used to quantitatively adjust the clock signal delay; the delay unit includes: a first inverter, a second inverter, a resistor, and a capacitor; wherein the input electrode of the first inverter serves as the receiving end of the delay unit to receive the external clock signal, and the output electrode of the first inverter is connected to one end of the resistor; the input electrode of the second inverter is connected to the other end of the resistor and one end of the capacitor, and the output electrode of the second inverter serves as the sending end of the delay unit; the other end of the capacitor is grounded, and the resistor and the capacitor form an RC delay circuit; A first NMOS transistor, a second NMOS transistor and a PMOS transistor; wherein the drain of the first NMOS transistor and the source of the PMOS transistor are connected to the output of the second inverter; the source of the first NMOS transistor is connected to the drain of the second NMOS transistor and the drain of the PMOS transistor, and serves as the output of the delay unit; the source of the second NMOS transistor is grounded.
2. A bus-controlled clock delay circuit according to claim 1, characterized in that: The delay unit also includes a third inverter; the input of the third inverter receives an external control signal and is connected to the gate of the first NMOS transistor, and the output of the third inverter is connected to the gate of the PMOS transistor and the gate of the second NMOS transistor.
3. A bus-controlled clock delay circuit according to claim 1, characterized in that: When the control signal received by the delay unit is at a high level, the first NMOS transistor is turned on, the PMOS transistor is turned on, and the second NMOS transistor is turned off; the clock signal output by the output pole of the second inverter passes through the first NMOS transistor and the PMOS transistor and is output at the output end of the delay unit.
4. A bus-controlled clock delay circuit according to claim 1, characterized in that: When the control signal received by the delay unit is at a low level, the first NMOS transistor is turned off, the PMOS transistor is turned off, and the second NMOS transistor is turned on; the output end of the delay unit outputs a 0 signal.
5. A bus-controlled clock delay circuit according to claim 1, characterized in that: In the bus control signal, one bit is set to a high level as required, and the remaining bits are set to a low level; only the output end of the delay unit at the first level whose control signal input is a high level outputs the delayed clock signal, and the output ends of the delay units at the remaining levels output a 0 signal; the signals output from the output ends of the delay units at each level pass through the OR gate circuit, and a logical OR operation is performed to output the delayed target clock signal.
6. A bus-controlled clock delay circuit according to claim 1, characterized in that: If the number of the output terminals of the delay units of all stages is less than the number of the input terminals of the first stage OR gates, the input terminals of the redundant first stage OR gates are set to 0.
7. A bus-controlled clock delay circuit according to claim 1, characterized in that: In the delay unit, a plurality of inverters are connected in series between the first inverter and the second inverter.
8. A bus-controlled clock delay circuit according to claim 1, characterized in that: The sending end of the delay unit of the last stage is grounded through a resistor with a resistance value greater than 1K.