A PLL frequency synthesizer

Abstract

The invention discloses a PLL frequency synthesizer, which comprises a phase frequency detector PFD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, a frequency divider DIV, a frequency detector FC and a reference spurious filter SFP; the phase frequency detector PFD, the charge pump CP, the loop filter LF, the voltage controlled oscillator VCO and the frequency divider DIV are connected in sequence, the reference spurious filter SFP is connected in series between the charge pump CP and the loop filter LF or between the loop filter LF and the voltage controlled oscillator VCO, the frequency detector FC is connected to the reference spurious filter SFP, and the frequency detector FC and the phase frequency detector PFD are connected to a reference frequency signal Fref. The invention can effectively reduce the reference frequency spurious.

Description

Technical Field

[0001] The invention relates to the field of data communication, in particular to a PLL frequency synthesizer. Background Art

[0002] In data communication systems, PLL frequency synthesizers mainly provide stable local oscillator signals for transmitting / receiving radio waves. Figure 1 As shown, the commonly used PLL frequency synthesizer includes a voltage-controlled oscillator VCO', a programmable frequency divider DIV', a phase frequency detector PFD', a charge pump CP' and a loop filter LF'. Among them, the voltage-controlled oscillator VCO' is used to change the oscillation frequency of the local oscillator signal outputted by it according to the oscillation frequency control signal; the frequency divider DIV' is used to divide the local oscillator signal outputted from the voltage-controlled oscillator VCO' according to the frequency division ratio corresponding to the channel selection signal inputted from the outside; the phase frequency detector PFD' is used to detect the phase difference between the frequency division signal outputted from the frequency divider DIV' and the reference frequency signal Fref' inputted from the outside and output the corresponding phase difference signal; the charge pump CP' controls the current to flow into or out of the output point according to the phase difference signal outputted from the phase frequency detector PFD' and outputs a current signal; the loop filter LF' is used to filter the high-frequency component of the current signal outputted from the charge pump CP' and convert the current signal into an oscillation frequency control signal and feed it back to the voltage-controlled oscillator VCO'.

[0003] In actual operation, the existing PLL frequency synthesizer has non-ideal effects such as leakage of the input reference frequency signal Fref' by the chip substrate, asymmetry and delay inconsistency of the phase frequency detector PFD', dynamic current mismatch of the charge pump CP', charge sharing and clock collapse, etc., which result in a periodic disturbance of the frequency of the reference frequency signal Fref' at the output of the loop filter LF'. Subsequently, through the modulation of the voltage-controlled oscillator VCO', a fixed reference frequency leakage signal (generally referred to as reference frequency spurious) is present in the frequency spectrum of the local oscillator signal of the voltage-controlled oscillator VCO'.

[0004] At present, although the order of the loop filter LF' can be increased to suppress the reference frequency spurious, the improvement is limited; when the reference frequency spurious is large, the power of the useful signal between channels will be smaller than the power of the reference frequency spurious, thereby causing channel blocking and increasing the bit error rate.

[0005] In view of the existence of the above problems, it is necessary to study a PLL frequency synthesizer that can effectively reduce the reference frequency spurious. Summary of the invention

[0006] The object of the present invention is to provide a PLL frequency synthesizer which can effectively reduce reference frequency spurious.

[0007] In order to achieve the above object, the solution of the present invention is:

[0008] A PLL frequency synthesizer comprises a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage controlled oscillator (VCO), a frequency divider (DIV), a frequency detector (FC) and a reference spurious filter (SFP); a first input end of the phase frequency detector (PFD) is connected to a reference frequency signal (Fref); a second input end of the phase frequency detector (PFD) is connected to an output end of the frequency divider (DIV); the phase frequency detector (PFD) is used to detect a frequency difference and a phase difference between a frequency division signal output by the frequency divider (DIV) and a reference frequency signal (Fref) and output a phase difference signal; an input end of the charge pump (CP) is connected to an output end of the phase frequency detector (PFD); the charge pump (CP) is used to generate a corresponding control current signal according to the phase difference signal output by the phase frequency detector (PFD); an input end of the loop filter (LF) is connected to an output end of the charge pump (CP); the loop filter (LF) is used to filter a high frequency component in a control current signal output by the charge pump (CP), and the loop filter (LF) is also used to convert the control current signal output by the charge pump (CP) into a corresponding control voltage signal; The spurious filter SFP adopts a notch filter with an adjustable center frequency. The input end of the reference spurious filter SFP is connected to the output end of the loop filter LF, and the reference spurious filter SFP is used to perform notch filtering on the control voltage signal output by the loop filter LF; the input end of the voltage-controlled oscillator VCO is connected to the output end of the reference spurious filter SFP, and the voltage-controlled oscillator VCO changes the frequency of the local oscillator signal output by the voltage-controlled oscillator VCO according to the control voltage signal after notch filtering by the reference spurious filter SFP; the input end of the frequency divider DIV is connected to the output end of the voltage-controlled oscillator VCO, and the frequency divider DIV is used to divide the local oscillator signal output by the voltage-controlled oscillator VCO according to a predetermined frequency division ratio to obtain a corresponding frequency-divided signal; the input end of the frequency detector FC is connected to the reference frequency signal Fref, the output end of the frequency detector FC is connected to the reference spurious filter SFP, and the frequency detector FC is used to detect the frequency of the reference frequency signal Fref and change the center frequency of the reference spurious filter SFP accordingly.

[0009] The frequency detector FC includes a time-to-voltage converter TVC, a first voltage comparator COMP1, a second voltage comparator COMP2 and a digital logic circuit LOGIC; the input end of the time-to-voltage converter TVC is connected to the reference frequency signal Fref, the non-inverting input end of the first voltage comparator COMP1 and the inverting input end of the second voltage comparator COMP2 are connected to the output end of the time-to-voltage converter TVC, the inverting input end of the first voltage comparator COMP1 is connected to the first reference voltage signal Vref1, the non-inverting input end of the second voltage comparator COMP2 is connected to the second reference voltage signal Vref2, the output end of the first voltage comparator COMP1 and the output end of the second voltage comparator COMP2 are connected to the digital logic circuit LOGIC, and the digital logic circuit LOGIC is connected to the reference spurious filter SFP.

[0010] The reference stray filter SFP includes a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, a first adjustable capacitor C1, a second adjustable capacitor C2 and a third adjustable capacitor C3; the adjustment ends of the first adjustable resistor R1, the second adjustable resistor R2, the third adjustable resistor R3, the first adjustable capacitor C1, the second adjustable capacitor C2 and the third adjustable capacitor C3 are respectively connected to the digital logic circuit LOGIC of the frequency detector FC; the first end of the first adjustable resistor R1 and the first end of the first adjustable capacitor C1 are connected to the input end of the reference stray filter SFP, the second end of the first adjustable resistor R1 is connected to the first end of the third adjustable capacitor C3 and the first end of the second adjustable resistor R2, the second end of the first adjustable capacitor C1 is connected to the first end of the third adjustable resistor R3 and the first end of the second adjustable capacitor C2, the second end of the second adjustable resistor R2 and the second end of the second adjustable capacitor C2 are connected to the output end of the reference stray filter SFP, and the second end of the third adjustable resistor R3 and the second end of the third adjustable capacitor C3 are grounded.

[0011] Another PLL frequency synthesizer includes a phase frequency detector PFD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, a frequency divider DIV, a frequency detector FC and a reference spurious filter SFP; the first input end of the phase frequency detector PFD is connected to a reference frequency signal Fref, the second input end of the phase frequency detector PFD is connected to the output end of the frequency divider DIV, the phase frequency detector PFD is used to detect the frequency difference and phase difference between the frequency division signal output by the frequency divider DIV and the reference frequency signal Fref and output a phase difference signal; the input end of the charge pump CP is connected to the output end of the phase frequency detector PFD, the charge pump CP is used to generate a corresponding control current signal according to the phase difference signal output by the phase frequency detector PFD; the reference spurious filter SFP adopts a notch filter with adjustable center frequency, the input end of the reference spurious filter SFP is connected to the output end of the charge pump CP, and the reference spurious filter SFP is used to perform notch filtering on the control current signal output by the charge pump CP; the input end of the loop filter LF is connected to the reference spurious filter LF. The output end of the control circuit SFP is connected to the loop filter LF, and the loop filter LF is used to filter the high-frequency components in the control current signal after the reference stray filter SFP is notched filtered, and the loop filter LF is also used to convert the control current signal after the reference stray filter SFP is notched filtered into a corresponding control voltage signal; the input end of the voltage-controlled oscillator VCO is connected to the output end of the loop filter LF, and the voltage-controlled oscillator VCO changes the frequency of the local oscillator signal output by the voltage-controlled oscillator VCO according to the control voltage signal output by the loop filter LF; the input end of the frequency divider DIV is connected to the output end of the voltage-controlled oscillator VCO, and the frequency divider DIV is used to divide the local oscillator signal output by the voltage-controlled oscillator VCO according to a predetermined frequency division ratio to obtain a corresponding frequency division signal; the input end of the frequency detector FC is connected to the reference frequency signal Fref, the output end of the frequency detector FC is connected to the reference stray filter SFP, and the frequency detector FC is used to detect the frequency of the reference frequency signal Fref and change the center frequency of the reference stray filter SFP accordingly.

[0012] The frequency detector FC includes a time-to-voltage converter TVC, a first voltage comparator COMP1, a second voltage comparator COMP2 and a digital logic circuit LOGIC; the input end of the time-to-voltage converter TVC is connected to the reference frequency signal Fref, the non-inverting input end of the first voltage comparator COMP1 and the inverting input end of the second voltage comparator COMP2 are connected to the output end of the time-to-voltage converter TVC, the inverting input end of the first voltage comparator COMP1 is connected to the first reference voltage signal Vref1, the non-inverting input end of the second voltage comparator COMP2 is connected to the second reference voltage signal Vref2, the output end of the first voltage comparator COMP1 and the output end of the second voltage comparator COMP2 are connected to the digital logic circuit LOGIC, and the digital logic circuit LOGIC is connected to the reference spurious filter SFP.

[0013] The reference stray filter SFP includes a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, a first adjustable capacitor C1, a second adjustable capacitor C2 and a third adjustable capacitor C3; the adjustment ends of the first adjustable resistor R1, the second adjustable resistor R2, the third adjustable resistor R3, the first adjustable capacitor C1, the second adjustable capacitor C2 and the third adjustable capacitor C3 are respectively connected to the digital logic circuit LOGIC of the frequency detector FC; the first end of the first adjustable resistor R1 and the first end of the first adjustable capacitor C1 are connected to the input end of the reference stray filter SFP, the second end of the first adjustable resistor R1 is connected to the first end of the third adjustable capacitor C3 and the first end of the second adjustable resistor R2, the second end of the first adjustable capacitor C1 is connected to the first end of the third adjustable resistor R3 and the first end of the second adjustable capacitor C2, the second end of the second adjustable resistor R2 and the second end of the second adjustable capacitor C2 are connected to the output end of the reference stray filter SFP, and the second end of the third adjustable resistor R3 and the second end of the third adjustable capacitor C3 are grounded.

[0014] After adopting the above scheme, when a PLL frequency synthesizer of the present invention is in a locked state, a control voltage signal output by the loop filter LF or a control current signal output by the charge pump CP will be superimposed with a ripple signal with a frequency the same as that of the reference frequency signal Fref; and the reference spurious filter SFP of the present invention adopts a notch filter, and the reference spurious filter SFP can perform attenuation filtering on the signal whose frequency is near the center frequency of the reference spurious filter SFP; and the frequency detector FC of the present invention will detect the frequency of the reference frequency signal Fref and change the center frequency of the reference spurious filter SFP accordingly, so that the center frequency of the reference spurious filter SFP is near the frequency of the reference frequency signal Fref, so that the reference spurious filter SFP can filter out the ripple signal with a frequency the same as that of the reference frequency signal Fref, thereby reducing the leakage of the reference frequency spurious, and effectively improving the suppression ratio of the local oscillator signal output by the voltage-controlled oscillator VCO to the reference frequency spurious and the quality of the local oscillator signal output by the voltage-controlled oscillator VCO. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of a commonly used PLL frequency synthesizer.

[0016] Figure 2 This is a schematic diagram of the first embodiment of the present invention.

[0017] Figure 3 FIG. 4 is a schematic diagram of a frequency detector FC according to a first embodiment of the present invention.

[0018] Figure 4 It is a schematic diagram of a reference spurious filter SFP according to the first embodiment of the present invention.

[0019] Figure 5 This is a schematic diagram of the second embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to further explain the technical solution of the present invention, the present invention is described in detail below through specific embodiments.

[0021] Embodiment 1:

[0022] Cooperate Figures 2 to 4As shown, in the first embodiment of the present invention, a PLL frequency synthesizer of the present invention includes a phase frequency detector PFD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, a frequency divider DIV, a frequency detector FC and a reference spurious filter SFP; wherein, the first input end of the phase frequency detector PFD is connected to the reference frequency signal Fref, the second input end of the phase frequency detector PFD is connected to the output end of the frequency divider DIV, the phase frequency detector PFD is used to detect the frequency difference and phase difference between the frequency division signal output by the frequency divider DIV and the reference frequency signal Fref and output a phase difference signal; the input end of the charge pump CP is connected to the output end of the phase frequency detector PFD, the charge pump CP is used to generate a corresponding control current signal according to the phase difference signal output by the phase frequency detector PFD; the input end of the loop filter LF is connected to the output end of the charge pump CP, the loop filter LF is used to filter the high frequency component in the control current signal output by the charge pump CP, and the loop filter LF is also used to convert the control current signal output by the charge pump CP into a corresponding The reference spurious filter SFP adopts a notch filter with adjustable center frequency, the input end of the reference spurious filter SFP is connected to the output end of the loop filter LF, and the reference spurious filter SFP is used to perform notch filtering on the control voltage signal output by the loop filter LF; the input end of the voltage-controlled oscillator VCO is connected to the output end of the reference spurious filter SFP, and the voltage-controlled oscillator VCO changes the frequency of the local oscillator signal output by the voltage-controlled oscillator VCO according to the control voltage signal after notch filtering by the reference spurious filter SFP; the input end of the frequency divider DIV is connected to the output end of the voltage-controlled oscillator VCO, and the frequency divider DIV is used to divide the local oscillator signal output by the voltage-controlled oscillator VCO according to a predetermined frequency division ratio to obtain a corresponding frequency-divided signal; the input end of the frequency detector FC is connected to the reference frequency signal Fref, the output end of the frequency detector FC is connected to the reference spurious filter SFP, and the frequency detector FC is used to detect the frequency of the reference frequency signal Fref and change the center frequency of the reference spurious filter SFP accordingly.

[0023] In a PLL frequency synthesizer in the first embodiment of the present invention, when it is in a locked state, a control voltage signal output by the loop filter LF will be superimposed with a ripple signal with a frequency the same as that of the reference frequency signal Fref; and the reference spurious filter SFP of the present invention adopts a notch filter, and the reference spurious filter SFP can attenuate and filter the signal whose frequency is near the center frequency of the reference spurious filter SFP; and the frequency detector FC of the present invention will detect the frequency of the reference frequency signal Fref and change the center frequency of the reference spurious filter SFP accordingly, so that the center frequency of the reference spurious filter SFP is near the frequency of the reference frequency signal Fref, so that the reference spurious filter SFP can filter out the ripple signal with a frequency the same as that of the reference frequency signal Fref, thereby reducing the leakage of the reference frequency spurious, and effectively improving the suppression ratio of the local oscillator signal output by the voltage-controlled oscillator VCO to the reference frequency spurious and the quality of the local oscillator signal output by the voltage-controlled oscillator VCO.

[0024] Cooperate Figure 3 As shown, in the first embodiment of the present invention, the frequency detector FC includes a time-to-voltage converter TVC, a first voltage comparator COMP1, a second voltage comparator COMP2 and a digital logic circuit LOGIC; the input end of the time-to-voltage converter TVC is connected to the reference frequency signal Fref, the non-inverting input end of the first voltage comparator COMP1 and the inverting input end of the second voltage comparator COMP2 are connected to the output end of the time-to-voltage converter TVC, the inverting input end of the first voltage comparator COMP1 is connected to the first reference voltage signal Vref1, the non-inverting input end of the second voltage comparator COMP2 is connected to the second reference voltage signal Vref2, the output end of the first voltage comparator COMP1 and the output end of the second voltage comparator COMP2 are connected to the digital logic circuit LOGIC, and the digital logic circuit LOGIC is connected to the reference spurious filter SFP. Among them, the time-to-voltage converter TVC converts the reference frequency signal Fref into a corresponding frequency voltage signal, and the frequency voltage signal is compared with the first reference voltage signal Vref1 and the second reference voltage signal Vref2 through the first voltage comparator COMP1 and the second voltage comparator COMP2 respectively. The digital logic circuit LOGIC changes the center frequency of the reference stray filter SFP accordingly according to the comparison result, so that the center frequency of the reference stray filter SFP is close to the frequency of the reference frequency signal Fref.

[0025] Cooperate Figure 4As shown, in the first embodiment of the present invention, the reference stray filter SFP includes a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, a first adjustable capacitor C1, a second adjustable capacitor C2 and a third adjustable capacitor C3; the adjustment ends of the first adjustable resistor R1, the second adjustable resistor R2, the third adjustable resistor R3, the first adjustable capacitor C1, the second adjustable capacitor C2 and the third adjustable capacitor C3 are respectively connected to the digital logic circuit LOGIC of the frequency detector FC; the first end of the first adjustable resistor R1 and the first end of the first adjustable capacitor C1 are connected to the input end of the reference stray filter SFP, the second end of the first adjustable resistor R1 is connected to the first end of the third adjustable capacitor C3 and the first end of the second adjustable resistor R2, the second end of the first adjustable capacitor C1 is connected to the first end of the third adjustable resistor R3 and the first end of the second adjustable capacitor C2, the second end of the second adjustable resistor R2 and the second end of the second adjustable capacitor C2 are connected to the output end of the reference stray filter SFP, and the second end of the third adjustable resistor R3 and the second end of the third adjustable capacitor C3 are grounded. The digital logic circuit LOGIC adjusts the center frequency of the reference spurious filter SFP by adjusting the resistance values ​​of the first adjustable resistor R1, the second adjustable resistor R2 and the third adjustable resistor R3 and adjusting the capacitance values ​​of the first adjustable capacitor C1, the second adjustable capacitor C2 and the third adjustable capacitor C3.

[0026] Embodiment 2:

[0027] Cooperate Figure 5As shown, in the second embodiment of the present invention, a PLL frequency synthesizer of the present invention includes a phase frequency detector PFD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, a frequency divider DIV, a frequency detector FC and a reference stray filter SFP; wherein, the first input end of the phase frequency detector PFD is connected to the reference frequency signal Fref, the second input end of the phase frequency detector PFD is connected to the output end of the frequency divider DIV, the phase frequency detector PFD is used to detect the frequency difference and phase difference between the frequency division signal output by the frequency divider DIV and the reference frequency signal Fref and output a phase difference signal; the input end of the charge pump CP is connected to the output end of the phase frequency detector PFD, the charge pump CP is used to generate a corresponding control current signal according to the phase difference signal output by the phase frequency detector PFD; the reference stray filter SFP adopts a notch filter with adjustable center frequency, the input end of the reference stray filter SFP is connected to the output end of the charge pump CP, and the reference stray filter SFP is used to perform notch filtering on the control current signal output by the charge pump CP; the input end of the loop filter LF The end is connected to the output end of the reference stray filter SFP, the loop filter LF is used to filter the high-frequency components in the control current signal after the reference stray filter SFP is notched filtered, and the loop filter LF is also used to convert the control current signal after the reference stray filter SFP is notched filtered into a corresponding control voltage signal; the input end of the voltage-controlled oscillator VCO is connected to the output end of the loop filter LF, and the voltage-controlled oscillator VCO changes the frequency of the local oscillator signal output by the voltage-controlled oscillator VCO according to the control voltage signal output by the loop filter LF; the input end of the frequency divider DIV is connected to the output end of the voltage-controlled oscillator VCO, and the frequency divider DIV is used to divide the local oscillator signal output by the voltage-controlled oscillator VCO according to a predetermined frequency division ratio to obtain a corresponding frequency division signal; the input end of the frequency detector FC is connected to the reference frequency signal Fref, the output end of the frequency detector FC is connected to the reference stray filter SFP, and the frequency detector FC is used to detect the frequency of the reference frequency signal Fref and change the center frequency of the reference stray filter SFP accordingly. The specific structure of the frequency detector FC and the reference stray filter SFP of the second embodiment is the same as that of the first embodiment.

[0028] In a PLL frequency synthesizer of the second embodiment of the present invention, when it is in a locked state, a control current signal output by the charge pump CP will be superimposed with a ripple signal with a frequency the same as that of the reference frequency signal Fref; and the reference spurious filter SFP of the present invention adopts a notch filter, and the reference spurious filter SFP can attenuate and filter the signal whose frequency is near the center frequency of the reference spurious filter SFP; and the frequency detector FC of the present invention will detect the frequency of the reference frequency signal Fref and change the center frequency of the reference spurious filter SFP accordingly, so that the center frequency of the reference spurious filter SFP is near the frequency of the reference frequency signal Fref, so that the reference spurious filter SFP can filter out the ripple signal with a frequency the same as that of the reference frequency signal Fref, thereby reducing the leakage of the reference frequency spurious, and effectively improving the suppression ratio of the local oscillator signal output by the voltage-controlled oscillator VCO to the reference frequency spurious and the quality of the local oscillator signal output by the voltage-controlled oscillator VCO.

[0029] The above embodiments and drawings do not limit the product form and style of the present invention. Any appropriate changes or modifications made by ordinary technicians in the relevant technical field should be deemed to be within the patent scope of the present invention.

Claims

1. A PLL frequency synthesizer, characterized in that: It includes a phase frequency detector PFD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, a frequency divider DIV, a frequency detector FC and a reference spurious filter SFP; The first input terminal of the phase frequency detector PFD is connected to the reference frequency signal Fref, the second input terminal of the phase frequency detector PFD is connected to the output terminal of the frequency divider DIV, and the phase frequency detector PFD is used to detect the frequency difference and phase difference between the divided signal output by the frequency divider DIV and the reference frequency signal Fref and output a phase difference signal; The input end of the charge pump CP is connected to the output end of the phase frequency detector PFD, and the charge pump CP is used to generate a corresponding control current signal according to the phase difference signal output by the phase frequency detector PFD; The input end of the loop filter LF is connected to the output end of the charge pump CP. The loop filter LF is used to filter the high-frequency components in the control current signal output by the charge pump CP, and the loop filter LF is also used to convert the control current signal output by the charge pump CP into a corresponding control voltage signal; The reference stray filter SFP adopts a notch filter with adjustable center frequency. The input end of the reference stray filter SFP is connected to the output end of the loop filter LF. The reference stray filter SFP is used to perform notch filtering on the control voltage signal output by the loop filter LF. The input end of the voltage-controlled oscillator VCO is connected to the output end of the reference spurious filter SFP, and the voltage-controlled oscillator VCO changes the frequency of the local oscillator signal output by the voltage-controlled oscillator VCO according to the control voltage signal after notch filtering by the reference spurious filter SFP; The input end of the frequency divider DIV is connected to the output end of the voltage controlled oscillator VCO, and the frequency divider DIV is used to divide the local oscillator signal output by the voltage controlled oscillator VCO according to a predetermined frequency division ratio to obtain a corresponding frequency division signal; The input end of the frequency detector FC is connected to the reference frequency signal Fref, and the output end of the frequency detector FC is connected to the reference spurious filter SFP. The frequency detector FC is used to detect the frequency of the reference frequency signal Fref and change the center frequency of the reference spurious filter SFP accordingly. The frequency detector FC includes a time-to-voltage converter TVC, a first voltage comparator COMP1, a second voltage comparator COMP2 and a digital logic circuit LOGIC; the input end of the time-to-voltage converter TVC is connected to the reference frequency signal Fref, the non-inverting input end of the first voltage comparator COMP1 and the inverting input end of the second voltage comparator COMP2 are connected to the output end of the time-to-voltage converter TVC, the inverting input end of the first voltage comparator COMP1 is connected to the first reference voltage signal Vref1, the non-inverting input end of the second voltage comparator COMP2 is connected to the second reference voltage signal Vref2, the output end of the first voltage comparator COMP1 and the output end of the second voltage comparator COMP2 are connected to the digital logic circuit LOGIC, and the digital logic circuit LOGIC is connected to the reference spurious filter SFP.

2. A PLL frequency synthesizer as claimed in claim 1, characterized in that: The reference spurious filter SFP comprises a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, a first adjustable capacitor C1, a second adjustable capacitor C2 and a third adjustable capacitor C3; the adjustment ends of the first adjustable resistor R1, the second adjustable resistor R2, the third adjustable resistor R3, the first adjustable capacitor C1, the second adjustable capacitor C2 and the third adjustable capacitor C3 are respectively connected to the digital logic circuit LOGIC of the frequency detector FC; The first end of the first adjustable resistor R1 and the first end of the first adjustable capacitor C1 are connected to the input end of the reference stray filter SFP, the second end of the first adjustable resistor R1 is connected to the first end of the third adjustable capacitor C3 and the first end of the second adjustable resistor R2, the second end of the first adjustable capacitor C1 is connected to the first end of the third adjustable resistor R3 and the first end of the second adjustable capacitor C2, the second end of the second adjustable resistor R2 and the second end of the second adjustable capacitor C2 are connected to the output end of the reference stray filter SFP, and the second end of the third adjustable resistor R3 and the second end of the third adjustable capacitor C3 are grounded.

3. A PLL frequency synthesizer, characterized in that: It includes a phase frequency detector PFD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, a frequency divider DIV, a frequency detector FC and a reference spurious filter SFP; The first input terminal of the phase frequency detector PFD is connected to the reference frequency signal Fref, the second input terminal of the phase frequency detector PFD is connected to the output terminal of the frequency divider DIV, and the phase frequency detector PFD is used to detect the frequency difference and phase difference between the divided signal output by the frequency divider DIV and the reference frequency signal Fref and output a phase difference signal; The input end of the charge pump CP is connected to the output end of the phase frequency detector PFD, and the charge pump CP is used to generate a corresponding control current signal according to the phase difference signal output by the phase frequency detector PFD; The reference stray filter SFP adopts a notch filter with adjustable center frequency. The input end of the reference stray filter SFP is connected to the output end of the charge pump CP. The reference stray filter SFP is used to perform notch filtering on the control current signal output by the charge pump CP. The input end of the loop filter LF is connected to the output end of the reference stray filter SFP, the loop filter LF is used to filter the high-frequency components in the control current signal after notch filtering by the reference stray filter SFP, and the loop filter LF is also used to convert the control current signal after notch filtering by the reference stray filter SFP into a corresponding control voltage signal; The input end of the voltage controlled oscillator VCO is connected to the output end of the loop filter LF, and the voltage controlled oscillator VCO changes the frequency of the local oscillation signal output by the voltage controlled oscillator VCO according to the control voltage signal output by the loop filter LF; The input end of the frequency divider DIV is connected to the output end of the voltage controlled oscillator VCO, and the frequency divider DIV is used to divide the local oscillator signal output by the voltage controlled oscillator VCO according to a predetermined frequency division ratio to obtain a corresponding frequency division signal; The input end of the frequency detector FC is connected to the reference frequency signal Fref, and the output end of the frequency detector FC is connected to the reference spurious filter SFP. The frequency detector FC is used to detect the frequency of the reference frequency signal Fref and change the center frequency of the reference spurious filter SFP accordingly. The frequency detector FC includes a time-to-voltage converter TVC, a first voltage comparator COMP1, a second voltage comparator COMP2 and a digital logic circuit LOGIC; the input end of the time-to-voltage converter TVC is connected to the reference frequency signal Fref, the non-inverting input end of the first voltage comparator COMP1 and the inverting input end of the second voltage comparator COMP2 are connected to the output end of the time-to-voltage converter TVC, the inverting input end of the first voltage comparator COMP1 is connected to the first reference voltage signal Vref1, the non-inverting input end of the second voltage comparator COMP2 is connected to the second reference voltage signal Vref2, the output end of the first voltage comparator COMP1 and the output end of the second voltage comparator COMP2 are connected to the digital logic circuit LOGIC, and the digital logic circuit LOGIC is connected to the reference spurious filter SFP.

4. A PLL frequency synthesizer as claimed in claim 3, characterized in that: The reference spurious filter SFP comprises a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, a first adjustable capacitor C1, a second adjustable capacitor C2 and a third adjustable capacitor C3; the adjustment ends of the first adjustable resistor R1, the second adjustable resistor R2, the third adjustable resistor R3, the first adjustable capacitor C1, the second adjustable capacitor C2 and the third adjustable capacitor C3 are respectively connected to the digital logic circuit LOGIC of the frequency detector FC; The first end of the first adjustable resistor R1 and the first end of the first adjustable capacitor C1 are connected to the input end of the reference stray filter SFP, the second end of the first adjustable resistor R1 is connected to the first end of the third adjustable capacitor C3 and the first end of the second adjustable resistor R2, the second end of the first adjustable capacitor C1 is connected to the first end of the third adjustable resistor R3 and the first end of the second adjustable capacitor C2, the second end of the second adjustable resistor R2 and the second end of the second adjustable capacitor C2 are connected to the output end of the reference stray filter SFP, and the second end of the third adjustable resistor R3 and the second end of the third adjustable capacitor C3 are grounded.

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