Process optimization method and device for multi-layer flexible circuit board production line

Abstract

The present invention relates to the technical field of circuit board production and processing, in particular to a process optimization method and device for a multi-layer flexible circuit board production line. A bubble chart is constructed based on multiple electrical test data of a multi-layer flexible circuit board to analyze whether the test product is qualified or not. If the multi-layer flexible circuit board is a test unqualified product, the abnormal electrical test data is clustered into a corresponding wiring model chart; the copper foil material abnormality when the sub-circuit impedance deviation value appears in the abnormal wiring area is calculated and output according to the conductive transmission logic rule of the abnormal wiring area, and the material abnormality analysis result is obtained; if the material abnormality analysis result shows that it is a multi-layer abnormal material, a dynamic lamination field of the abnormal wiring area is created, and the lamination process of the multi-layer flexible circuit board is optimized based on the global update iteration of the abnormal parameters of the spatiotemporal lamination process in the dynamic lamination field. The present invention can accurately and efficiently optimize the production process of the multi-layer flexible circuit board production line and reduce the production scrap rate.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board production and processing, and in particular to a process optimization method and device for a multi-layer flexible circuit board production line. Background Art

[0002] A multilayer flexible circuit board is a flexible circuit board made of multiple layers of conductive patterns and insulating materials. It is usually used in situations that require high-density wiring and complex electrical connections. It combines the flexibility of a flexible circuit board with the high performance of a multilayer circuit board. It has the advantages of high flexibility, bendability, and space saving. It is widely used in electronic devices that are space-constrained and require lightweight. The production process of a multilayer flexible circuit board determines the quality of the product itself, so the process of the multilayer flexible circuit board needs to be accurately and efficiently optimized. However, the existing multilayer flexible circuit board process optimization method is usually a global optimization. It is difficult to carry out targeted and detailed optimization of processes such as photolithography coating, material etching, or material lamination in the production process based on the abnormal product performance of the multilayer flexible circuit board. Therefore, there are widespread optimization errors, which increase the scrap rate and defective rate of the multilayer flexible circuit board, increase the production rework cost, and greatly reduce product quality and production efficiency. Summary of the invention

[0003] The present invention overcomes the shortcomings of the prior art and provides a process optimization method and device for a multi-layer flexible circuit board production line.

[0004] To achieve the above object, the technical solution adopted by the present invention is:

[0005] A first aspect of the present invention provides a process optimization method for a multi-layer flexible circuit board production line, comprising the following steps:

[0006] S102: Acquire multiple electrical test data of the multi-layer flexible circuit board, and construct a bubble chart based on the multiple electrical test data to analyze whether the test product is qualified or not. If the multi-layer flexible circuit board is a test unqualified product, cluster the abnormal electrical test data into a corresponding wiring model diagram to obtain an abnormal wiring area;

[0007] S104: Acquire the conductive transmission logic rule of the abnormal wiring area, calculate and output the superimposed electric field migration distribution when the sub-circuit impedance deviation value appears in the abnormal wiring area according to the conductive transmission logic rule, analyze the copper foil material abnormality in the abnormal wiring area through the superimposed electric field migration distribution, and obtain the material abnormality analysis result;

[0008] S106: If the material variation analysis result shows that there are multiple layers of abnormal materials, a standard lamination process flow of the multi-layer flexible circuit board is obtained to create a dynamic lamination field of the abnormal wiring area, and the lamination process of the multi-layer flexible circuit board is optimized based on the global update iteration of the spatiotemporal lamination process abnormal parameters in the dynamic lamination field;

[0009] S108: If the material variation analysis result shows that it is a single-layer variation material, further analyze and obtain the abnormal state of the circuit pattern in the abnormal wiring area; if the abnormal wiring area is determined to be a type of circuit pattern abnormal state, mark the unqualified photolithography coating area by measuring the coating content value on the abnormal wiring area, and optimize the photolithography coating process of the multi-layer flexible circuit board based on the optimal process control parameters of the unqualified photolithography coating area;

[0010] S110: If the abnormal wiring area is determined to be in a Class II circuit pattern abnormal state, the necessary etching loss index of the residual etching defect characteristics and the over-etching defect characteristics is obtained, and the multi-dimensional etching process change parameters of the etching mechanism are dynamically optimized using the dynamic etching model of the target etching area according to the necessary etching loss index.

[0011] More specifically, the step S102 includes the following steps:

[0012] Obtaining electrical design requirements of a multi-layer flexible circuit board, and performing electrical performance tests on the produced multi-layer flexible circuit board according to the electrical design requirements to obtain a plurality of electrical test data;

[0013] Constructing a bubble chart framework, extracting multiple electrical performance test assessment items and qualified critical reference values ​​corresponding to each electrical performance test assessment item according to the electrical performance test strategy, and creating a qualified critical reference bubble in the bubble chart framework based on the qualified critical reference value corresponding to each electrical performance test assessment item;

[0014] Obtaining a reference bubble color code of a qualified critical reference bubble in a qualified critical state, injecting a plurality of the electrical test data into the qualified critical reference bubble for data fitting, generating an actual electrical test bubble, and obtaining a current bubble color code of the actual electrical test bubble;

[0015] A hash algorithm is introduced, and a hash misalignment function of the current bubble color code compared to the reference bubble color code is calculated using the hash algorithm based on the qualified critical reference bubble and the actual electrical test bubble. If the hash misalignment function is a positive value, the multilayer flexible circuit board is calibrated as a qualified product.

[0016] If the hash misalignment function is a negative value, the multi-layer flexible circuit board is marked as a test-unqualified product. At this time, the abnormal electrical test data that causes the hash misalignment function to be a negative value is stripped out from the multiple electrical test data, and a wiring model diagram of the test-unqualified product is constructed, and the wiring model diagram is divided into a plurality of sub-model diagram areas based on electrical design requirements;

[0017] Obtain the conductive control decision corresponding to the abnormal electrical test data generated in each sub-model graph area during the test process, define each abnormal data point of each abnormal electrical test data as an independent cluster, calculate the Mahalanobis distance when each two independent clusters execute the conductive control decision one by one, and generate a Mahalanobis distance matrix;

[0018] Only two independent clusters with the smallest Mahalanobis distance are extracted and merged to form an independent cluster pair, and the Mahalanobis distance between the independent cluster pair and the unmerged independent cluster is calculated to update the Mahalanobis distance matrix, and the merging and updating operations are repeated until all independent clusters are clustered, thereby generating a clustering result for abnormal electrical test data;

[0019] The sub-model graph area that causes abnormal electrical test data is extracted through the clustering result and marked as an abnormal wiring area.

[0020] More specifically, the step S104 includes the following steps:

[0021] Obtain the circuit impedance characteristics of the multi-layer flexible circuit board according to the electrical design requirements, and obtain the conductive transmission logic rules of the abnormal wiring area;

[0022] Constructing an AC circuit topology diagram for performing electrical performance testing in an abnormal wiring area in accordance with the conductive transmission logic rule, extracting several AC power transmission nodes in the abnormal wiring area through the circuit topology diagram, and introducing a Bayesian inference network to infer the influence weight values ​​of several AC power transmission nodes on the circuit impedance characteristics;

[0023] Taking the conductive transmission logic rule as the allocation premise, assigning the corresponding circuit impedance characteristic to each abnormal wiring area based on the influence weight value under the allocation premise to obtain the ideal sub-circuit impedance characteristic of each abnormal wiring area;

[0024] Presetting an ideal sub-circuit impedance threshold for each abnormal wiring area according to the ideal sub-circuit impedance characteristic, obtaining an actual sub-circuit impedance value outputted by the abnormal wiring area during the electrical performance test, and calculating a difference between the actual sub-circuit impedance value and the ideal sub-circuit impedance threshold to obtain a sub-circuit impedance deviation value;

[0025] Based on the big data network, a comprehensive material dielectric knowledge graph is obtained, the sub-circuit impedance deviation value and the wiring model diagram are imported into the comprehensive material dielectric knowledge graph for identification, and the superimposed electric field migration distribution when the sub-circuit impedance deviation value appears in the abnormal wiring area is output;

[0026] Preset the allowable variation threshold interval of the dielectric variation of the material of the lamination process of the multi-layer flexible circuit board, and obtain the dielectric variation value of the material in the abnormal wiring area when the sub-circuit impedance deviation value occurs by analyzing the superimposed electric field migration distribution;

[0027] If the dielectric variation value of the material is not within the allowable variation threshold range, the copper foil material in the abnormal wiring area is calibrated as a multi-layer variation material; if the dielectric variation value of the material is within the allowable variation threshold range, the copper foil material in the abnormal wiring area is calibrated as a single-layer variation material, and the material variation analysis result is obtained.

[0028] More specifically, the step S106 includes the following steps:

[0029] If the material variation analysis result shows that there are multiple layers of abnormal material, the lamination defect data generated by the AOI optical inspection equipment for the abnormal wiring area during the electrical performance test and the distribution pattern of each lamination defect data in the abnormal wiring area are retrieved;

[0030] Obtaining a standard lamination process flow of a multi-layer flexible circuit board, creating a dynamic lamination field of an abnormal wiring area according to the standard lamination process flow, and introducing an edge detection algorithm to calculate the lamination defect data to obtain lamination defect characteristics of the abnormal wiring area;

[0031] Embed the lamination defect feature into a dynamic lamination domain by the distribution pattern of each lamination defect data in the abnormal wiring area, generate a dynamic lamination defect distribution domain, and plan the dynamic lamination defect distribution domain into M sub-distribution domains;

[0032] Acquire the predetermined generation time sequence of each of the lamination defect features when processing the abnormal wiring area in the standard lamination process flow, and simultaneously acquire the spatiotemporal lamination process parameter set of the multi-layer flexible circuit board lamination processing module located on the predetermined generation time sequence;

[0033] Only the sub-distribution areas with each of the lamination defect characteristics are extracted and marked as lamination process abnormal areas, and a predetermined generation time sequence node for generating each lamination process abnormal area is obtained based on a predetermined generation time sequence;

[0034] According to the established generation sequence, the spatiotemporal lamination process parameters located in the corresponding lamination process abnormal area after the multi-layer flexible circuit board lamination processing module reaches each established generation sequence node are stripped out in the lamination process parameter set, and are defined as spatiotemporal lamination process abnormal parameters;

[0035] Obtaining the expected lamination process criterion for avoiding necessary defects in the lamination process anomaly field of the standard lamination process flow, introducing a genetic algorithm, and globally updating and iterating the spatiotemporal lamination process anomaly parameters in the genetic algorithm based on the expected lamination process criterion to generate the spatiotemporal lamination process parameters after global update and iteration;

[0036] The lamination process of the multi-layer flexible circuit board is optimized according to the spatiotemporal lamination process parameters after the global update iteration, so as to reduce the lamination defect rate of the multi-layer flexible circuit board.

[0037] More specifically, the step S108 includes the following steps:

[0038] If the material variation analysis result shows a single-layer variation material, a standard circuit pattern template for the abnormal wiring area is established based on the electrical design requirements, and the standard circuit pattern template is registered with the actual circuit pattern of the abnormal wiring area to obtain a registration coincidence rate;

[0039] If the registration coincidence rate is greater than the preset registration coincidence rate, the circuit pattern in the abnormal wiring area is marked as a photolithography abnormality, and a first-class circuit pattern abnormal state is obtained; if the registration coincidence rate is less than the preset registration coincidence rate, the circuit pattern in the abnormal wiring area is marked as an etching abnormality, and a second-class circuit pattern abnormal state is obtained;

[0040] If the actual circuit pattern in the abnormal wiring area is determined to be a type of circuit pattern abnormal state, an initial design draft of the photolithography coating mechanism is obtained, a simulation model of the photolithography coating mechanism is constructed according to the initial design draft, and a preset photolithography coating process decision of the photolithography coating mechanism for the abnormal wiring area is obtained;

[0041] Utilizing the photolithography coating mechanism simulation model to execute the preset photolithography coating process decision to simulate the abnormal wiring area, obtain a simulated circuit pattern model of the abnormal wiring area, and obtain a plurality of predetermined photolithography coating nodes of the photolithography coating mechanism constrained by the preset photolithography coating process decision;

[0042] According to the plurality of predetermined photolithography coating nodes, the simulation circuit pattern model diagram is divided into execution areas of the photolithography coating mechanism to obtain a plurality of sub-execution blocks, and the coating content value of the photoresist on each sub-execution block is calculated by the simulation circuit pattern model;

[0043] Preset a uniform coating content threshold range for each sub-execution block, and if the coating content value is not within the uniform coating content threshold range, mark the sub-execution block as an unqualified photolithography coating area, and obtain the actual photolithography coating working condition posture of the photolithography coating mechanism for the unqualified photolithography coating area;

[0044] Obtaining a historical photolithography coating working condition posture in which a photolithography coating mechanism processes an unqualified photolithography coating area until a coating content value reaches a uniform coating content threshold range, calculating a hash state value between an actual photolithography coating working condition posture and a historical photolithography coating working condition posture, and obtaining a plurality of hash state values;

[0045] The process control parameters corresponding to the historical photolithography coating working condition posture with the maximum hash state value are extracted and defined as the optimal process control parameters. The photolithography coating process of the multi-layer flexible circuit board is optimized based on the optimal process control parameters to improve the photolithography coating quality of the multi-layer flexible circuit board.

[0046] More specifically, the step S110 includes the following steps:

[0047] If the actual circuit pattern in the abnormal wiring area is determined to be in the second-class circuit pattern abnormal state, all etching defect features existing in the actual circuit pattern in the abnormal wiring area compared with the standard circuit pattern template are extracted through the inspection log of the AOI optical inspection equipment;

[0048] Obtaining a preset etching process strategy for a target etching area in an abnormal wiring area processed by an etching mechanism, dividing the target etching area into a plurality of sub-etching areas according to the preset etching process strategy, and obtaining sequential etching image information of each sub-etching area during an electrical performance test;

[0049] The ARMA model is introduced to perform time series autoregression and moving average analytical calculation on the time series etching image information of each sub-etching area, and a dynamic etching model of each sub-etching area is generated, and the multi-dimensional etching process change parameters of the etching solution in each sub-etching area are obtained through each dynamic etching model;

[0050] Obtaining the etching process knowledge graph based on the big data network, identifying the multi-dimensional etching process change parameters of the etching solution in each sub-etching area through the etching process knowledge graph, and obtaining the dynamic etching loss index of each sub-etching area;

[0051] Presetting a dynamic etching boundary threshold based on the dynamic etching loss index, dynamically defining an etching range in each of the sub-etching regions until the corresponding dynamic etching boundary threshold is reached one by one, thereby generating a dynamic etching loss range for each sub-etching region;

[0052] Obtaining specification parameters of each etching defect feature, calculating a necessary etching loss index of each etching defect feature based on the specification parameters, marking a plurality of dynamic etching loss ranges adjacent to each etching defect feature, and defining them as associated radiation etching loss ranges;

[0053] The intersection range of multiple associated radiation etching loss ranges is analyzed according to the necessary etching loss index of the residual etching defect characteristics and the over-etching defect characteristics to optimize the multi-dimensional etching process variation parameters of the etching mechanism.

[0054] More specifically, the necessary etching loss index analysis corresponding to the intersection range of multiple associated radiation etching loss ranges according to the residual etching defect characteristics and the over-etching defect characteristics in step S110 to optimize the multi-dimensional etching process variation parameters of the etching mechanism specifically includes the following steps:

[0055] If the etching defect feature is a residual etching defect feature, a synchronous expansion operation is performed on a plurality of associated radiation etching loss ranges corresponding to the residual etching defect feature based on the necessary etching loss index;

[0056] During the synchronous expansion process, the dynamic etching loss index of the intersection range generated by the multiple associated radiation etching loss ranges is calculated in real time, and when the necessary etching loss index exists in the dynamic etching loss index of the intersection range, the synchronous expansion is stopped, and the range expansion area value is obtained at this time;

[0057] Optimizing the multi-dimensional etching process variation parameters corresponding to each associated radiation etching loss range of the residual etching defect feature according to the range expansion area value to eliminate the residual etching phenomenon in the multi-layer flexible circuit board;

[0058] If the etching defect feature is an over-etching defect feature, obtaining an intersection range area value generated by a plurality of associated radiation etching loss ranges adjacent to the over-etching defect feature, and determining a dynamic etching loss index of the intersection range according to the intersection range area value;

[0059] Constructing a Bezier curve graph, drawing a dynamic etching loss Bezier curve of an intersection range in the Bezier curve graph according to the dynamic etching loss index, obtaining a slope value of the dynamic etching loss Bezier curve, and presetting a slope threshold value based on a necessary etching loss index of an over-etching defect feature;

[0060] The deviation between the slope value of the dynamic etching loss Bezier curve and the slope threshold is calculated to obtain a slope deviation value, and the multi-dimensional etching process change parameters of the etching mechanism are dynamically optimized according to the slope deviation value to reduce over-etching in the multi-layer flexible circuit board.

[0061] A second aspect of the present invention provides a process optimization device for a multi-layer flexible circuit board production line, the process optimization device comprising a memory and a processor, the memory storing a process optimization method program for a multi-layer flexible circuit board production line, and when the process optimization method program is executed by the processor, any one of the process optimization method steps is implemented.

[0062] The present invention solves the technical defects existing in the background technology, and the beneficial technical effects of the present invention are:

[0063] Based on multiple electrical test data of multi-layer flexible circuit boards, a bubble chart is constructed to analyze whether the test product is qualified or not. If the multi-layer flexible circuit board is a test unqualified product, the abnormal electrical test data is clustered to the corresponding wiring model diagram to obtain an abnormal wiring area; the copper foil material variation condition when the sub-circuit impedance deviation value appears in the abnormal wiring area is calculated according to the conductive transmission logic rule of the abnormal wiring area to obtain the material variation analysis result; if the material variation analysis result shows that it is a multi-layer variation material, a dynamic lamination field of the abnormal wiring area is created, and the lamination process of the multi-layer flexible circuit board is analyzed based on the global update iteration of the abnormal parameters of the spatiotemporal lamination process in the dynamic lamination field. Optimization; if the material variation analysis result shows a single-layer variation material, further analyze and obtain the abnormal state of the circuit pattern in the abnormal wiring area; if the abnormal wiring area is determined to be a type of circuit pattern abnormal state, then the unqualified photolithography coating area is marked by measuring the coating content value on the abnormal wiring area, and the photolithography coating process of the multi-layer flexible circuit board is optimized based on the optimal process control parameters of the unqualified photolithography coating area; if the abnormal wiring area is determined to be a type II circuit pattern abnormal state, the dynamic etching model of the target etching area is used to dynamically optimize the multi-dimensional etching process change parameters of the etching mechanism according to the necessary etching loss index of the residual etching defect characteristics and the over-etching defect characteristics. The present invention can accurately and efficiently optimize the production process of the multi-layer flexible circuit board production line to improve the production quality of the multi-layer flexible circuit board, increase the product qualification rate, and reduce the production scrap rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without paying creative work.

[0065] Figure 1 A first method flow chart of a process optimization method for a multi-layer flexible circuit board production line is shown;

[0066] Figure 2 A second method flow chart of a process optimization method for a multi-layer flexible circuit board production line is shown;

[0067] Figure 3 The device structure diagram of the process optimization device for a multi-layer flexible circuit board production line is shown. DETAILED DESCRIPTION

[0068] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0069] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0070] The first aspect of the present invention provides a process optimization method for a multi-layer flexible circuit board production line, such as Figure 1 As shown, the following steps are included:

[0071] S102: Acquire multiple electrical test data of the multi-layer flexible circuit board, and construct a bubble chart based on the multiple electrical test data to analyze whether the test product is qualified or not. If the multi-layer flexible circuit board is a test unqualified product, cluster the abnormal electrical test data into a corresponding wiring model diagram to obtain an abnormal wiring area;

[0072] S104: Acquire the conductive transmission logic rule of the abnormal wiring area, calculate and output the superimposed electric field migration distribution when the sub-circuit impedance deviation value appears in the abnormal wiring area according to the conductive transmission logic rule, analyze the copper foil material abnormality in the abnormal wiring area through the superimposed electric field migration distribution, and obtain the material abnormality analysis result;

[0073] S106: If the material variation analysis result shows that there are multiple layers of abnormal materials, a standard lamination process flow of the multi-layer flexible circuit board is obtained to create a dynamic lamination field of the abnormal wiring area, and the lamination process of the multi-layer flexible circuit board is optimized based on the global update iteration of the spatiotemporal lamination process abnormal parameters in the dynamic lamination field;

[0074] S108: If the material variation analysis result shows that it is a single-layer variation material, further analyze and obtain the abnormal state of the circuit pattern in the abnormal wiring area; if the abnormal wiring area is determined to be a type of circuit pattern abnormal state, mark the unqualified photolithography coating area by measuring the coating content value on the abnormal wiring area, and optimize the photolithography coating process of the multi-layer flexible circuit board based on the optimal process control parameters of the unqualified photolithography coating area;

[0075] S110: If the abnormal wiring area is determined to be in a Class II circuit pattern abnormal state, the necessary etching loss index of the residual etching defect characteristics and the over-etching defect characteristics is obtained, and the multi-dimensional etching process change parameters of the etching mechanism are dynamically optimized using the dynamic etching model of the target etching area according to the necessary etching loss index.

[0076] More specifically, the step S102 includes the following steps:

[0077] Obtaining electrical design requirements of a multi-layer flexible circuit board, and performing electrical performance tests on the produced multi-layer flexible circuit board according to the electrical design requirements to obtain a plurality of electrical test data;

[0078] Constructing a bubble chart framework, extracting multiple electrical performance test assessment items and qualified critical reference values ​​corresponding to each electrical performance test assessment item according to the electrical performance test strategy, and creating a qualified critical reference bubble in the bubble chart framework based on the qualified critical reference value corresponding to each electrical performance test assessment item;

[0079] Obtaining a reference bubble color code of a qualified critical reference bubble in a qualified critical state, injecting a plurality of the electrical test data into the qualified critical reference bubble for data fitting, generating an actual electrical test bubble, and obtaining a current bubble color code of the actual electrical test bubble;

[0080] A hash algorithm is introduced, and a hash misalignment function of the current bubble color code compared to the reference bubble color code is calculated using the hash algorithm based on the qualified critical reference bubble and the actual electrical test bubble. If the hash misalignment function is a positive value, the multilayer flexible circuit board is calibrated as a qualified product.

[0081] If the hash misalignment function is a negative value, the multi-layer flexible circuit board is marked as a test-unqualified product. At this time, the abnormal electrical test data that causes the hash misalignment function to be a negative value is stripped out from the multiple electrical test data, and a wiring model diagram of the test-unqualified product is constructed, and the wiring model diagram is divided into a plurality of sub-model diagram areas based on electrical design requirements;

[0082] Obtain the conductive control decision corresponding to the abnormal electrical test data generated in each sub-model graph area during the test process, define each abnormal data point of each abnormal electrical test data as an independent cluster, calculate the Mahalanobis distance when each two independent clusters execute the conductive control decision one by one, and generate a Mahalanobis distance matrix;

[0083] Only two independent clusters with the smallest Mahalanobis distance are extracted and merged to form an independent cluster pair, and the Mahalanobis distance between the independent cluster pair and the unmerged independent cluster is calculated to update the Mahalanobis distance matrix, and the merging and updating operations are repeated until all independent clusters are clustered, thereby generating a clustering result for abnormal electrical test data;

[0084] The sub-model graph area that causes abnormal electrical test data is extracted through the clustering result and marked as an abnormal wiring area.

[0085] It should be noted that comprehensive electrical performance tests, such as impedance test, short circuit test and open circuit test, are carried out for the complexity of different multi-layer flexible circuit boards produced by the production line to ensure that they meet the design specifications. However, the electrical performance quality of traditional multi-layer flexible circuit boards usually needs to be identified by manual and professional instruments. The steps are cumbersome and time-consuming, which reduces the efficiency of multi-layer flexible circuit board production quality inspection and the accuracy of targeted optimization of subsequent production processes. Usually, a qualified standard is set for each test assessment item. Therefore, this method creates a bubble in the bubble chart framework that can express the qualified critical benchmark of each electrical test assessment item, where the color coding of the bubble itself is expressed as the qualified critical benchmark value, and the actual electrical test bubbles generated by multiple electrical test data are analyzed based on the qualified critical benchmark bubble as the standard. The difference in the bubble color coding displayed by the two can determine whether the test is qualified or not. If the hash misalignment function is positive, it means that multiple electrical test data have reached the qualified critical benchmark value, so it is marked as a qualified product; otherwise, it means that multiple electrical test data have not reached the qualified critical benchmark value, and it is marked as a failed product. Therefore, compared with the traditional method, the present invention can improve the quality inspection efficiency of the multi-layer flexible circuit board and ensure the stability of the production process optimization.

[0086] It should be noted that when a multilayer flexible circuit board is a product that fails the test, it is necessary to locate the wiring area that causes the abnormality of the multilayer flexible circuit board based on the abnormal electrical test data that does not meet the standard. This method divides the wiring model diagram of the product that fails the test into several sub-model diagram areas, and according to the conductive control decision of each sub-model diagram area when the abnormal electrical test data is generated during the test, the independent clusters represented by the abnormal electrical test data are reasonably clustered into the sub-model diagram area, so that the abnormal wiring area that causes the abnormal electrical test data can be obtained. This method can accurately trace the abnormality of the multilayer flexible circuit board that fails the electrical performance test, thereby greatly improving the pertinence and accuracy of the process optimization of the multilayer flexible circuit board production line, and avoiding the occurrence of process optimization errors, omissions and mistakes.

[0087] More specifically, the step S104 is as follows: Figure 2 As shown, the specific steps include:

[0088] S202: Obtaining circuit impedance characteristics of the multilayer flexible circuit board according to electrical design requirements, and simultaneously obtaining conductive transmission logic rules of abnormal wiring areas;

[0089] S204: constructing an AC circuit topology diagram for performing an electrical performance test in the abnormal wiring area according to the conductive transmission logic rule, extracting a number of AC power transmission nodes in the abnormal wiring area through the circuit topology diagram, and introducing a Bayesian inference network to infer the influence weight values ​​of the number of AC power transmission nodes on the circuit impedance characteristics;

[0090] S206: taking the conductive transmission logic rule as the allocation premise, assigning a corresponding circuit impedance characteristic to each abnormal wiring area based on the influence weight value under the allocation premise, and obtaining an ideal sub-circuit impedance characteristic of each abnormal wiring area;

[0091] S208: Preset an ideal sub-circuit impedance threshold for each abnormal wiring area according to the ideal sub-circuit impedance characteristic, obtain an actual sub-circuit impedance value output by the abnormal wiring area during the electrical performance test, calculate a difference between the actual sub-circuit impedance value and the ideal sub-circuit impedance threshold, and obtain a sub-circuit impedance deviation value;

[0092] S210: Acquire a comprehensive material dielectric knowledge graph based on a big data network, import the sub-circuit impedance deviation value and the wiring model diagram into the comprehensive material dielectric knowledge graph for identification, and output a superimposed electric field migration distribution when a sub-circuit impedance deviation value appears in an abnormal wiring area;

[0093] S212: presetting an allowable variation threshold interval of dielectric variation tolerance of the multilayer flexible circuit board in the lamination process, and obtaining the dielectric variation value of the material in the abnormal wiring area when the sub-circuit impedance deviation value occurs by analyzing the superimposed electric field migration distribution;

[0094] S214: If the dielectric variation value of the material is not within the allowable variation threshold range, the copper foil material in the abnormal wiring area is calibrated as a multi-layer variation material; if the dielectric variation value of the material is within the allowable variation threshold range, the copper foil material in the abnormal wiring area is calibrated as a single-layer variation material, and a material variation analysis result is obtained.

[0095] It should be noted that a multi-layer flexible circuit board is usually composed of multiple inner circuit boards and insulating layers alternately stacked under high temperature and high pressure to combine all layers into a whole, so that it has a multi-layer structure. When an abnormal wiring area appears in a multi-layer flexible circuit board, it means that the wrong process in the production process has caused the laminated material to have an abnormality, and the object of the abnormality may involve multi-layer circuit board materials, which is caused by improper lamination process, or it may only form a single-layer circuit board material abnormality, which may be caused by errors in the photolithography coating process or etching errors. The electrical properties exhibited by the two after the abnormality are different. Among them, errors in the lamination process may cause changes in the dielectric constant of the material, affect the impedance characteristics of the circuit, and then affect the quality of electrical signal transmission. Therefore, in order to accurately locate and optimize the process that causes the multi-layer flexible circuit board to fail the electrical test, the method determines the ideal sub-circuit impedance characteristics of each abnormal wiring area by analyzing the AC transmission situation of the abnormal wiring area during the electrical performance test, and calculates the deviation between the actual sub-circuit impedance value output by the abnormal wiring area during the electrical performance test and the ideal sub-circuit impedance characteristic to identify and obtain the superimposed electric field migration distribution when the sub-circuit impedance deviation value appears in the abnormal wiring area. The superimposed electric field migration distribution reflects the electric field migration characteristics of the multi-layer circuit board material after lamination. According to the superimposed electric field migration distribution, the dielectric variation value of the material with higher credibility in the abnormal wiring area can be obtained; if the dielectric variation value of the material is not in the allowable variation threshold range, it means that the improper lamination process causes the copper foil material between different layers to change, so it is calibrated as a multi-layer variation material; otherwise, it means that the photolithography coating process or the etching process causes defects in the single-layer copper foil material, thereby causing electrical transmission abnormalities, so it is calibrated as a single-layer variation material. This method can analyze material variations in multi-layer flexible circuit boards, so that the production process that needs to be optimized can be accurately locked in according to the material variation conditions, effectively improving the accuracy of process optimization, and further ensuring the reliability of traceability optimization of multi-layer flexible circuit boards.

[0096] More specifically, the step S106 includes the following steps:

[0097] If the material variation analysis result shows that there are multiple layers of abnormal material, the lamination defect data generated by the AOI optical inspection equipment for the abnormal wiring area during the electrical performance test and the distribution pattern of each lamination defect data in the abnormal wiring area are retrieved;

[0098] Obtaining a standard lamination process flow of a multi-layer flexible circuit board, creating a dynamic lamination field of an abnormal wiring area according to the standard lamination process flow, and introducing an edge detection algorithm to calculate the lamination defect data to obtain lamination defect characteristics of the abnormal wiring area;

[0099] Embed the lamination defect feature into a dynamic lamination domain by the distribution pattern of each lamination defect data in the abnormal wiring area, generate a dynamic lamination defect distribution domain, and plan the dynamic lamination defect distribution domain into M sub-distribution domains;

[0100] Acquire the predetermined generation time sequence of each of the lamination defect features when processing the abnormal wiring area in the standard lamination process flow, and simultaneously acquire the spatiotemporal lamination process parameter set of the multi-layer flexible circuit board lamination processing module located on the predetermined generation time sequence;

[0101] Only the sub-distribution areas with each of the lamination defect characteristics are extracted and marked as lamination process abnormal areas, and a predetermined generation time sequence node for generating each lamination process abnormal area is obtained based on a predetermined generation time sequence;

[0102] According to the established generation sequence, the spatiotemporal lamination process parameters located in the corresponding lamination process abnormal area after the multi-layer flexible circuit board lamination processing module reaches each established generation sequence node are stripped out in the lamination process parameter set, and are defined as spatiotemporal lamination process abnormal parameters;

[0103] Obtaining the expected lamination process criterion for avoiding necessary defects in the lamination process anomaly field of the standard lamination process flow, introducing a genetic algorithm, and globally updating and iterating the spatiotemporal lamination process anomaly parameters in the genetic algorithm based on the expected lamination process criterion to generate the spatiotemporal lamination process parameters after global update and iteration;

[0104] The lamination process of the multi-layer flexible circuit board is optimized according to the spatiotemporal lamination process parameters after the global update iteration, so as to reduce the lamination defect rate of the multi-layer flexible circuit board.

[0105] It should be noted that during the lamination process of a multi-layer flexible circuit board processed by a laminating mechanism, if the lamination pressure and temperature process parameters are inappropriate, a large number of bubbles and gaps may be generated between the copper foil materials of different layers, and inappropriate process parameters will make the adhesion of each layer of material poor. For example, if the lamination temperature is too high or the pressure is uneven, it is easy to cause the board to warp or peel off between layers, thereby greatly reducing the electrical conductivity of each layer of copper foil material, affecting the electrical transmission performance. Therefore, this method first creates a dynamic lamination field of the abnormal wiring area through the standard lamination process flow of the multi-layer flexible circuit board. The dynamic lamination field is a dynamic visualization process field of the copper foil material of the abnormal wiring area laminated by a laminating mechanism, showing the lamination process of the abnormal wiring area; then the lamination defect characteristics are embedded in the dynamic lamination field to form a dynamic lamination defect distribution field. The dynamic lamination defect distribution field shows the dynamic generation process of each lamination defect in the abnormal wiring area during the lamination process, which has a certain time sequence. Then, the lamination process abnormal area is extracted. When lamination defects appear in the lamination process abnormal area, the lamination mechanism's spatiotemporal lamination process parameters for the lamination process abnormal area are wrong. Therefore, the wrong spatiotemporal lamination process abnormal parameters in the spatiotemporal lamination process parameter set are stripped and extracted by obtaining the established generation time sequence nodes where lamination defects appear in the lamination process abnormal area. The spatiotemporal lamination process abnormal parameters refer to the lamination process abnormal parameters in time and space, such as lamination time, lamination temperature and lamination pressure. Finally, according to the expected lamination process criteria, the incorrect spatiotemporal lamination process abnormal parameters are globally updated and iterated in the genetic algorithm, thereby optimizing the lamination process of the multi-layer flexible circuit board. This method can be used to optimize the lamination process of producing multi-layer flexible circuit boards globally and reasonably according to the material defect analysis between different layers, so as to reduce the lamination defect rate of the multi-layer flexible circuit boards, ensure good bonding of the materials of each layer, avoid the generation of bubbles, gaps, board warping or interlayer peeling, and prevent interlayer stress or uneven curing caused by improper lamination timing.

[0106] More specifically, the step S108 includes the following steps:

[0107] If the material variation analysis result shows a single-layer variation material, a standard circuit pattern template for the abnormal wiring area is established based on the electrical design requirements, and the standard circuit pattern template is registered with the actual circuit pattern of the abnormal wiring area to obtain a registration coincidence rate;

[0108] If the registration coincidence rate is greater than the preset registration coincidence rate, the circuit pattern in the abnormal wiring area is marked as a photolithography abnormality, and a first-class circuit pattern abnormal state is obtained; if the registration coincidence rate is less than the preset registration coincidence rate, the circuit pattern in the abnormal wiring area is marked as an etching abnormality, and a second-class circuit pattern abnormal state is obtained;

[0109] If the actual circuit pattern in the abnormal wiring area is determined to be a type of circuit pattern abnormal state, an initial design draft of the photolithography coating mechanism is obtained, a simulation model of the photolithography coating mechanism is constructed according to the initial design draft, and a preset photolithography coating process decision of the photolithography coating mechanism for the abnormal wiring area is obtained;

[0110] Utilizing the photolithography coating mechanism simulation model to execute the preset photolithography coating process decision to simulate the abnormal wiring area, obtain a simulated circuit pattern model of the abnormal wiring area, and obtain a plurality of predetermined photolithography coating nodes of the photolithography coating mechanism constrained by the preset photolithography coating process decision;

[0111] According to the plurality of predetermined photolithography coating nodes, the simulation circuit pattern model diagram is divided into execution areas of the photolithography coating mechanism to obtain a plurality of sub-execution blocks, and the coating content value of the photoresist on each sub-execution block is calculated by the simulation circuit pattern model;

[0112] Preset a uniform coating content threshold range for each sub-execution block, and if the coating content value is not within the uniform coating content threshold range, mark the sub-execution block as an unqualified photolithography coating area, and obtain the actual photolithography coating working condition posture of the photolithography coating mechanism for the unqualified photolithography coating area;

[0113] Obtaining a historical photolithography coating working condition posture in which a photolithography coating mechanism processes an unqualified photolithography coating area until a coating content value reaches a uniform coating content threshold range, calculating a hash state value between an actual photolithography coating working condition posture and a historical photolithography coating working condition posture, and obtaining a plurality of hash state values;

[0114] The process control parameters corresponding to the historical photolithography coating working condition posture with the maximum hash state value are extracted and defined as the optimal process control parameters. The photolithography coating process of the multi-layer flexible circuit board is optimized based on the optimal process control parameters to improve the photolithography coating quality of the multi-layer flexible circuit board.

[0115] It should be noted that if the material variation analysis result shows a single-layer variation material, it means that there are individual materials that have variation in the production process before the multi-layer material is laminated. This may be due to circuit pattern errors caused by photolithography coating or etching errors. Therefore, it is necessary to first analyze the degree of affiliation of the single-layer material variation caused by the two processes based on the registration overlap rate of the actual circuit pattern in the abnormal wiring area compared to the standard circuit pattern template; among them, if the registration overlap rate is greater than the preset registration overlap rate, it means that the deviation of the actual circuit pattern compared to the standard circuit pattern template is not large, and the variation of the single-layer material under the condition of small deviation may be uneven photoresist coating, which reduces the accuracy of pattern definition, rather than pattern missing, so it is marked as photolithography abnormality; on the contrary, it means that the actual circuit pattern has a large deviation from the standard circuit pattern template, and there is a missing or redundant circuit pattern, which may be due to excessive or incomplete etching of the material due to improper etching process parameters during material etching, which belongs to the pattern missing phenomenon. This method can further improve the credibility and accuracy of the traceability of single-layer material variation, which helps to improve the traceability efficiency of process optimization.

[0116] It should be noted that the actual photolithography coating working condition posture includes the coating thickness working condition posture, coating rate working condition posture and coating path working condition posture of the photolithography coating mechanism. If the actual circuit pattern of the abnormal wiring area is determined to be a type of circuit pattern abnormal state, it is necessary to optimize the photolithography coating process. This method simulates the photoresist coating process of the abnormal wiring area by the photolithography coating mechanism to obtain a simulated circuit pattern model of the abnormal wiring area. The coating content of the photoresist can be observed on this simulated circuit pattern model, and by analyzing whether the coating content value of the photoresist is within the uniform coating content threshold range, it is possible to further determine whether the actual photolithography coating working condition posture is reasonable, thereby selecting the optimal process control parameters of the historical photolithography coating working condition posture according to the unreasonable actual photolithography coating working condition posture to optimize the photolithography coating process of the multi-layer flexible circuit board, so as to improve the photolithography coating quality of the multi-layer flexible circuit board, ensure the accuracy of the pattern definition, and avoid the deviation of the pattern fineness caused by the error of parameters such as the thickness of the photoresist, the coating rate and the coating path.

[0117] More specifically, the step S110 includes the following steps:

[0118] If the actual circuit pattern in the abnormal wiring area is determined to be in the second-class circuit pattern abnormal state, all etching defect features existing in the actual circuit pattern in the abnormal wiring area compared with the standard circuit pattern template are extracted through the inspection log of the AOI optical inspection equipment;

[0119] Obtaining a preset etching process strategy for a target etching area in an abnormal wiring area processed by an etching mechanism, dividing the target etching area into a plurality of sub-etching areas according to the preset etching process strategy, and obtaining sequential etching image information of each sub-etching area during an electrical performance test;

[0120] The ARMA model is introduced to perform time series autoregression and moving average analytical calculation on the time series etching image information of each sub-etching area, and a dynamic etching model of each sub-etching area is generated, and the multi-dimensional etching process change parameters of the etching solution in each sub-etching area are obtained through each dynamic etching model;

[0121] Obtaining the etching process knowledge graph based on the big data network, identifying the multi-dimensional etching process change parameters of the etching solution in each sub-etching area through the etching process knowledge graph, and obtaining the dynamic etching loss index of each sub-etching area;

[0122] Presetting a dynamic etching boundary threshold based on the dynamic etching loss index, dynamically defining an etching range in each of the sub-etching regions until the corresponding dynamic etching boundary threshold is reached one by one, thereby generating a dynamic etching loss range for each sub-etching region;

[0123] Obtaining specification parameters of each etching defect feature, calculating a necessary etching loss index of each etching defect feature based on the specification parameters, marking a plurality of dynamic etching loss ranges adjacent to each etching defect feature, and defining them as associated radiation etching loss ranges;

[0124] The intersection range of multiple associated radiation etching loss ranges is analyzed according to the necessary etching loss index of the residual etching defect characteristics and the over-etching defect characteristics to optimize the multi-dimensional etching process variation parameters of the etching mechanism.

[0125] It should be noted that if the actual circuit pattern of the abnormal wiring area is determined to be in the abnormal state of the second type of circuit pattern, it means that the actual circuit pattern is missing or redundantly repeated, which means that the etching area of ​​the single-layer material has an over-etching defect or a residual etching defect. Therefore, the etching process of the multi-layer flexible circuit board needs to be optimized. This method first constructs a dynamic etching model for each sub-etching area through the time-series etching image information. The dynamic etching model visually displays the dynamic etching process of the target etching area, which contains the parameters such as the flow rate, concentration, flow rate and temperature of the etching solution during the etching process, that is, the multi-dimensional etching process change parameters; by analyzing the multi-dimensional process change parameters, the dynamic etching loss index of each sub-etching area can be further determined. The dynamic etching loss index is a measure of the loss of the material being etched during the dynamic etching process. Then, a dynamic etching loss range is planned for each sub-etching area according to the dynamic etching loss index. The dynamic etching loss range reflects the etching influence area of ​​the etching solution on the circuit board material in the sub-etching area, which can facilitate the efficient analysis of the subsequent influence of each sub-etching area on the etching defect characteristics; the necessary etching loss index is the etching loss index that must be achieved to eliminate the etching defect characteristics; finally, according to the necessary etching loss index of the residual etching defect characteristics and the over-etching defect characteristics, the intersection range of the corresponding multiple associated radiation etching loss ranges is analyzed to optimize the multi-dimensional etching process change parameters of the etching mechanism. This method can efficiently and accurately optimize the etching process during the production of multi-layer flexible circuit boards, thereby eliminating the phenomenon of frequent etching defects, reducing the etching scrap rate of multi-layer flexible circuit boards, and improving the quality of production processes and products. Among them, the Chinese name of the ARMA model is the autoregressive moving average model.

[0126] More specifically, the necessary etching loss index analysis corresponding to the intersection range of multiple associated radiation etching loss ranges according to the residual etching defect characteristics and the over-etching defect characteristics in step S110 to optimize the multi-dimensional etching process variation parameters of the etching mechanism specifically includes the following steps:

[0127] If the etching defect feature is a residual etching defect feature, a synchronous expansion operation is performed on a plurality of associated radiation etching loss ranges corresponding to the residual etching defect feature based on the necessary etching loss index;

[0128] During the synchronous expansion process, the dynamic etching loss index of the intersection range generated by the multiple associated radiation etching loss ranges is calculated in real time, and when the necessary etching loss index exists in the dynamic etching loss index of the intersection range, the synchronous expansion is stopped, and the range expansion area value is obtained at this time;

[0129] Optimizing the multi-dimensional etching process variation parameters corresponding to each associated radiation etching loss range of the residual etching defect feature according to the range expansion area value to eliminate the residual etching phenomenon in the multi-layer flexible circuit board;

[0130] If the etching defect feature is an over-etching defect feature, obtaining an intersection range area value generated by a plurality of associated radiation etching loss ranges adjacent to the over-etching defect feature, and determining a dynamic etching loss index of the intersection range according to the intersection range area value;

[0131] Constructing a Bezier curve graph, drawing a dynamic etching loss Bezier curve of an intersection range in the Bezier curve graph according to the dynamic etching loss index, obtaining a slope value of the dynamic etching loss Bezier curve, and presetting a slope threshold value based on a necessary etching loss index of an over-etching defect feature;

[0132] The deviation between the slope value of the dynamic etching loss Bezier curve and the slope threshold is calculated to obtain a slope deviation value, and the multi-dimensional etching process change parameters of the etching mechanism are dynamically optimized according to the slope deviation value to reduce over-etching in the multi-layer flexible circuit board.

[0133] It should be noted that if the etching defect feature is a residual etching defect feature, it means that the concentration, temperature and flow rate of the etching solution are insufficient so that the material in the area is not completely etched away, thereby causing etching residues and interfering with the conductive properties of the circuit pattern. Since the residual etching defect is not etched away due to the fact that the surrounding etching solution has not passed or the etching parameters are wrong, the method synchronously expands multiple associated radiation etching loss ranges adjacent to the residual etching defect feature so that the surrounding associated radiation etching loss ranges can radiate to the residual etching defect feature. At this time, multiple associated radiation etching loss ranges will produce an intersection range, which is the performance feedback of whether the etching process parameters of the surrounding sub-etching area can remove the residual etching defect feature. When the necessary etching loss index exists in the dynamic etching loss index of the intersection range, the synchronous expansion is stopped, indicating that the process parameters of the etching solution in the surrounding sub-etching area meet the requirements for removing the residual etching feature. At this time, the multi-dimensional etching process change parameters can be optimized according to the range expansion area value to eliminate the residual etching phenomenon in the multi-layer flexible circuit board. If the etching defect feature is an over-etching defect feature, it means that the concentration, temperature and flow rate of the etching solution in the surrounding sub-etching area are too high, so that the material to be retained in the area is over-etched, resulting in unstable electrical signal transmission of the circuit pattern and other phenomena. Since the process parameters of the etching solution in the surrounding sub-etching area are too high, there must be an intersection range in the multiple associated radiation etching loss ranges around the over-etching defect feature. Therefore, this method constructs a Bezier curve of dynamic etching loss according to the dynamic etching loss index of the intersection range, and dynamically optimizes the multi-dimensional etching process change parameters of the etching mechanism by analyzing the slope of the Bezier curve of dynamic etching loss to reduce the over-etching phenomenon in the multi-layer flexible circuit board. This method can optimize the process parameters that lead to different types of etching defects to ensure that the etching mechanism can uniformly etch the materials of the multi-layer flexible circuit board, minimize the phenomenon of over-etching or uneven etching, and has high reliability.

[0134] The second aspect of the present invention provides a process optimization device for a multi-layer flexible circuit board production line, such as Figure 3 As shown, the process optimization device includes a memory 31 and a processor 32. The memory 31 stores a process optimization method program for a multi-layer flexible circuit board production line. When the process optimization method program is executed by the processor 32, any one of the process optimization method steps is implemented.

[0135] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A process optimization method for a multi-layer flexible circuit board production line, characterized in that: The following steps are involved: S102: Acquire multiple electrical test data of the multi-layer flexible circuit board, and construct a bubble chart based on the multiple electrical test data to analyze whether the test product is qualified or not. If the multi-layer flexible circuit board is a test unqualified product, cluster the abnormal electrical test data into a corresponding wiring model diagram to obtain an abnormal wiring area; S104: Acquire the conductive transmission logic rule of the abnormal wiring area, calculate and output the superimposed electric field migration distribution when the sub-circuit impedance deviation value appears in the abnormal wiring area according to the conductive transmission logic rule, analyze the copper foil material abnormality in the abnormal wiring area through the superimposed electric field migration distribution, and obtain the material abnormality analysis result; S106: If the material variation analysis result shows that there are multiple layers of abnormal materials, a standard lamination process flow of the multi-layer flexible circuit board is obtained to create a dynamic lamination field of the abnormal wiring area, and the lamination process of the multi-layer flexible circuit board is optimized based on the global update iteration of the spatiotemporal lamination process abnormal parameters in the dynamic lamination field; S108: If the material variation analysis result shows that it is a single-layer variation material, further analyze and obtain the abnormal state of the circuit pattern in the abnormal wiring area; if the abnormal wiring area is determined to be a type of circuit pattern abnormal state, mark the unqualified photolithography coating area by measuring the coating content value on the abnormal wiring area, and optimize the photolithography coating process of the multi-layer flexible circuit board based on the optimal process control parameters of the unqualified photolithography coating area; S110: if the abnormal wiring area is determined to be in the abnormal state of the second type of circuit pattern, the necessary etching loss index of the residual etching defect characteristics and the over-etching defect characteristics is obtained, and the multi-dimensional etching process change parameters of the etching mechanism are dynamically optimized using the dynamic etching model of the target etching area according to the necessary etching loss index; The step S106 specifically includes the following steps: If the material variation analysis result shows that there are multiple layers of abnormal material, the lamination defect data generated by the AOI optical inspection equipment for the abnormal wiring area during the electrical performance test and the distribution pattern of each lamination defect data in the abnormal wiring area are retrieved; Obtaining a standard lamination process flow of a multi-layer flexible circuit board, creating a dynamic lamination field of an abnormal wiring area according to the standard lamination process flow, and introducing an edge detection algorithm to calculate the lamination defect data to obtain lamination defect characteristics of the abnormal wiring area; Embed the lamination defect feature into a dynamic lamination domain by the distribution pattern of each lamination defect data in the abnormal wiring area, generate a dynamic lamination defect distribution domain, and plan the dynamic lamination defect distribution domain into M sub-distribution domains; Acquire the predetermined generation time sequence of each of the lamination defect features when processing the abnormal wiring area in the standard lamination process flow, and simultaneously acquire the spatiotemporal lamination process parameter set of the multi-layer flexible circuit board lamination processing module located on the predetermined generation time sequence; Only the sub-distribution areas with each of the lamination defect characteristics are extracted and marked as lamination process abnormal areas, and a predetermined generation time sequence node for generating each lamination process abnormal area is obtained based on a predetermined generation time sequence; According to the established generation sequence, the spatiotemporal lamination process parameters located in the corresponding lamination process abnormal area after the multi-layer flexible circuit board lamination processing module reaches each established generation sequence node are stripped out in the lamination process parameter set, and are defined as spatiotemporal lamination process abnormal parameters; Obtaining the expected lamination process criterion for avoiding necessary defects in the lamination process anomaly field of the standard lamination process flow, introducing a genetic algorithm, and globally updating and iterating the spatiotemporal lamination process anomaly parameters in the genetic algorithm based on the expected lamination process criterion to generate the spatiotemporal lamination process parameters after global update and iteration; Optimizing the lamination process of the multi-layer flexible circuit board according to the spatiotemporal lamination process parameters after the global update iteration to reduce the lamination defect rate of the multi-layer flexible circuit board; The step S110 specifically includes the following steps: If the actual circuit pattern in the abnormal wiring area is determined to be in the second-class circuit pattern abnormal state, all etching defect features existing in the actual circuit pattern in the abnormal wiring area compared with the standard circuit pattern template are extracted through the inspection log of the AOI optical inspection equipment; Obtaining a preset etching process strategy for a target etching area in an abnormal wiring area processed by an etching mechanism, dividing the target etching area into a plurality of sub-etching areas according to the preset etching process strategy, and obtaining sequential etching image information of each sub-etching area during an electrical performance test; The ARMA model is introduced to perform time series autoregression and moving average analytical calculation on the time series etching image information of each sub-etching area, and a dynamic etching model of each sub-etching area is generated, and the multi-dimensional etching process change parameters of the etching solution in each sub-etching area are obtained through each dynamic etching model; Obtaining the etching process knowledge graph based on the big data network, identifying the multi-dimensional etching process change parameters of the etching solution in each sub-etching area through the etching process knowledge graph, and obtaining the dynamic etching loss index of each sub-etching area; Presetting a dynamic etching boundary threshold based on the dynamic etching loss index, dynamically defining an etching range in each of the sub-etching regions until the corresponding dynamic etching boundary threshold is reached one by one, thereby generating a dynamic etching loss range for each sub-etching region; Obtaining specification parameters of each etching defect feature, calculating a necessary etching loss index of each etching defect feature based on the specification parameters, marking a plurality of dynamic etching loss ranges adjacent to each etching defect feature, and defining them as associated radiation etching loss ranges; The intersection range of multiple associated radiation etching loss ranges is analyzed according to the necessary etching loss index of the residual etching defect characteristics and the over-etching defect characteristics to optimize the multi-dimensional etching process variation parameters of the etching mechanism.

2. The process optimization method for a multi-layer flexible circuit board production line according to claim 1, characterized in that: The step S102 specifically includes the following steps: Obtaining electrical design requirements of a multi-layer flexible circuit board, and performing electrical performance tests on the produced multi-layer flexible circuit board according to the electrical design requirements to obtain a plurality of electrical test data; Constructing a bubble chart framework, extracting multiple electrical performance test assessment items and qualified critical reference values ​​corresponding to each electrical performance test assessment item according to the electrical performance test strategy, and creating a qualified critical reference bubble in the bubble chart framework based on the qualified critical reference value corresponding to each electrical performance test assessment item; Obtaining a reference bubble color code of a qualified critical reference bubble in a qualified critical state, injecting a plurality of the electrical test data into the qualified critical reference bubble for data fitting, generating an actual electrical test bubble, and obtaining a current bubble color code of the actual electrical test bubble; A hash algorithm is introduced, and a hash misalignment function of the current bubble color code compared to the reference bubble color code is calculated using the hash algorithm based on the qualified critical reference bubble and the actual electrical test bubble. If the hash misalignment function is a positive value, the multilayer flexible circuit board is calibrated as a qualified product. If the hash misalignment function is a negative value, the multi-layer flexible circuit board is marked as a test-unqualified product. At this time, the abnormal electrical test data that causes the hash misalignment function to be a negative value is stripped out from the multiple electrical test data, and a wiring model diagram of the test-unqualified product is constructed, and the wiring model diagram is divided into a plurality of sub-model diagram areas based on electrical design requirements; Obtain the conductive control decision corresponding to the abnormal electrical test data generated in each sub-model graph area during the test process, define each abnormal data point of each abnormal electrical test data as an independent cluster, calculate the Mahalanobis distance when each two independent clusters execute the conductive control decision one by one, and generate a Mahalanobis distance matrix; Only two independent clusters with the smallest Mahalanobis distance are extracted and merged to form an independent cluster pair, and the Mahalanobis distance between the independent cluster pair and the unmerged independent cluster is calculated to update the Mahalanobis distance matrix, and the merging and updating operations are repeated until all independent clusters are clustered, thereby generating a clustering result for abnormal electrical test data; The sub-model graph area that causes abnormal electrical test data is extracted through the clustering result and marked as an abnormal wiring area.

3. The process optimization method for a multi-layer flexible circuit board production line according to claim 1, characterized in that: The step S104 specifically includes the following steps: Obtain the circuit impedance characteristics of the multi-layer flexible circuit board according to the electrical design requirements, and obtain the conductive transmission logic rules of the abnormal wiring area; Constructing an AC circuit topology diagram for performing electrical performance testing in an abnormal wiring area in accordance with the conductive transmission logic rule, extracting several AC power transmission nodes in the abnormal wiring area through the circuit topology diagram, and introducing a Bayesian inference network to infer the influence weight values ​​of several AC power transmission nodes on the circuit impedance characteristics; Taking the conductive transmission logic rule as the allocation premise, assigning the corresponding circuit impedance characteristic to each abnormal wiring area based on the influence weight value under the allocation premise to obtain the ideal sub-circuit impedance characteristic of each abnormal wiring area; Presetting an ideal sub-circuit impedance threshold for each abnormal wiring area according to the ideal sub-circuit impedance characteristic, obtaining an actual sub-circuit impedance value outputted by the abnormal wiring area during the electrical performance test, and calculating a difference between the actual sub-circuit impedance value and the ideal sub-circuit impedance threshold to obtain a sub-circuit impedance deviation value; Based on the big data network, a comprehensive material dielectric knowledge graph is obtained, the sub-circuit impedance deviation value and the wiring model diagram are imported into the comprehensive material dielectric knowledge graph for identification, and the superimposed electric field migration distribution when the sub-circuit impedance deviation value appears in the abnormal wiring area is output; Preset the allowable variation threshold interval of the dielectric variation of the material of the lamination process of the multi-layer flexible circuit board, and obtain the dielectric variation value of the material in the abnormal wiring area when the sub-circuit impedance deviation value occurs by analyzing the superimposed electric field migration distribution; If the dielectric variation value of the material is not within the allowable variation threshold range, the copper foil material in the abnormal wiring area is calibrated as a multi-layer variation material; if the dielectric variation value of the material is within the allowable variation threshold range, the copper foil material in the abnormal wiring area is calibrated as a single-layer variation material, and the material variation analysis result is obtained.

4. The process optimization method for a multi-layer flexible circuit board production line according to claim 1, characterized in that: The step S108 specifically includes the following steps: If the material variation analysis result shows a single-layer variation material, a standard circuit pattern template for the abnormal wiring area is established based on the electrical design requirements, and the standard circuit pattern template is registered with the actual circuit pattern of the abnormal wiring area to obtain a registration coincidence rate; If the registration coincidence rate is greater than the preset registration coincidence rate, the circuit pattern in the abnormal wiring area is marked as a photolithography abnormality, and a first-class circuit pattern abnormal state is obtained; if the registration coincidence rate is less than the preset registration coincidence rate, the circuit pattern in the abnormal wiring area is marked as an etching abnormality, and a second-class circuit pattern abnormal state is obtained; If the actual circuit pattern in the abnormal wiring area is determined to be a type of circuit pattern abnormal state, an initial design draft of the photolithography coating mechanism is obtained, a simulation model of the photolithography coating mechanism is constructed according to the initial design draft, and a preset photolithography coating process decision of the photolithography coating mechanism for the abnormal wiring area is obtained; Utilizing the photolithography coating mechanism simulation model to execute the preset photolithography coating process decision to simulate the abnormal wiring area, obtain a simulated circuit pattern model of the abnormal wiring area, and obtain a plurality of predetermined photolithography coating nodes of the photolithography coating mechanism constrained by the preset photolithography coating process decision; Divide the execution area of ​​the photolithography coating mechanism of the simulation circuit pattern model into blocks according to the plurality of predetermined photolithography coating nodes to obtain a plurality of sub-execution blocks, and calculate the coating content value of the photoresist on each sub-execution block through the simulation circuit pattern model; Preset a uniform coating content threshold range for each sub-execution block, and if the coating content value is not within the uniform coating content threshold range, mark the sub-execution block as an unqualified photolithography coating area, and obtain the actual photolithography coating working condition posture of the photolithography coating mechanism for the unqualified photolithography coating area; Obtaining a historical photolithography coating working condition posture in which a photolithography coating mechanism processes an unqualified photolithography coating area until a coating content value reaches a uniform coating content threshold range, calculating a hash state value between an actual photolithography coating working condition posture and a historical photolithography coating working condition posture, and obtaining a plurality of hash state values; The process control parameters corresponding to the historical photolithography coating working condition posture with the maximum hash state value are extracted and defined as the optimal process control parameters. The photolithography coating process of the multi-layer flexible circuit board is optimized based on the optimal process control parameters to improve the photolithography coating quality of the multi-layer flexible circuit board.

5. The process optimization method for a multi-layer flexible circuit board production line according to claim 1, characterized in that: The necessary etching loss index analysis of the residual etching defect characteristics and the over-etching defect characteristics in step S110 corresponds to the intersection range of multiple associated radiation etching loss ranges to optimize the multi-dimensional etching process variation parameters of the etching mechanism, specifically including the following steps: If the etching defect feature is a residual etching defect feature, a synchronous expansion operation is performed on a plurality of associated radiation etching loss ranges corresponding to the residual etching defect feature based on the necessary etching loss index; During the synchronous expansion process, the dynamic etching loss index of the intersection range generated by the multiple associated radiation etching loss ranges is calculated in real time, and when the necessary etching loss index exists in the dynamic etching loss index of the intersection range, the synchronous expansion is stopped, and the range expansion area value is obtained at this time; Optimizing the multi-dimensional etching process variation parameters corresponding to each associated radiation etching loss range of the residual etching defect feature according to the range expansion area value to eliminate the residual etching phenomenon in the multi-layer flexible circuit board; If the etching defect feature is an over-etching defect feature, obtaining an intersection range area value generated by a plurality of associated radiation etching loss ranges adjacent to the over-etching defect feature, and determining a dynamic etching loss index of the intersection range according to the intersection range area value; Constructing a Bezier curve graph, drawing a dynamic etching loss Bezier curve of an intersection range in the Bezier curve graph according to the dynamic etching loss index, obtaining a slope value of the dynamic etching loss Bezier curve, and presetting a slope threshold value based on a necessary etching loss index of an over-etching defect feature; The deviation between the slope value of the dynamic etching loss Bezier curve and the slope threshold is calculated to obtain a slope deviation value, and the multi-dimensional etching process change parameters of the etching mechanism are dynamically optimized according to the slope deviation value to reduce over-etching in the multi-layer flexible circuit board.

6. A process optimization device for a multi-layer flexible circuit board production line, characterized in that: The process optimization device includes a memory and a processor, wherein the memory stores a process optimization method program for a multi-layer flexible circuit board production line. When the process optimization method program is executed by the processor, the process optimization method steps as described in any one of claims 1 to 5 are implemented.

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