Programmable gain amplifier and pressure sensor

Abstract

The invention relates to the technical field of analog integrated circuits, and discloses a programmable gain amplifier and a pressure sensor, the gain amplifier comprises an operational amplifier A1, an operational amplifier A2, an operational amplifier A3, a first resistor branch, a second resistor branch and a third resistor branch; in actual use, the first resistor branch circuit, the second resistor branch circuit, the third resistor branch circuit and the first to sixth switches form a closed-loop resistor network, and the amplification factor of the amplifier adjusted by the closed-loop resistor network depends on the linear proportion of resistors in the first to third resistor branch circuits instead of the absolute value of the resistance value of the resistors. Therefore, the problem that the technological characteristic requirement for resistor manufacturing is extremely high when the magnification of an existing amplifier is adjusted is solved, the influence of the external temperature and the technology on the magnification determination and the resistance value proportion of the amplifier is relatively small, the linearity of a single operational amplifier is enhanced, and the overall linearity is further improved.

Description

Technical Field

[0001] The invention relates to the technical field of analog integrated circuits, and in particular to a programmable gain amplifier and a pressure sensor. Background Art

[0002] With the continuous advancement of science and technology, pressure sensors, as a key sensor, have been widely used in various fields such as industrial automation, hydraulic systems, medical health, wearable devices and the automotive industry.

[0003] Among them, in the equipment and systems on various production lines of industrial automation, high-precision measurement and control of pressure are required; in hydraulic systems, pressure sensors can monitor oil pressure in real time to ensure the normal operation of the machine; in air pressure detection, pressure sensors can ensure the safety of gas supply; in the field of medical health, ventilators and monitors in medical equipment need to use pressure sensors to monitor patient physiological parameters; in the automotive industry, pressure sensors are used in engine management systems and braking systems to improve the performance and safety of the car.

[0004] For pressure sensors, the programmable gain amplifier (PGA) is an important module, and its amplification factor can be controlled by the program. The main parameters of PGA are gain control range, gain step, gain linearity, dynamic range, output DC offset and noise characteristics. The PGA with better performance can greatly improve the measurement accuracy of the A / D converter, and can amplify the signal before the low-amplitude signal is connected to the 16-bit analog-to-digital converter, thereby increasing the dynamic range. In addition, PGA can convert and filter analog signals, interconnect multiple functional modules in the device, reconstruct the circuit, and adjust the gain, bandwidth and threshold of the circuit.

[0005] The existing PGA is usually composed of an amplifier circuit and a digital control system. The amplifier circuit is responsible for amplifying the signal, while the digital control system adjusts the amplification factor. When adjusting the amplification factor, the amplification factor is adjusted through an open-loop connected resistor network, specifically by adjusting the resistance value of the resistor connected to the amplifier circuit. This adjustment method requires the absolute stability of the resistance value of the resistor network, which is greatly affected by external temperature and process, and is not conducive to improving the accuracy of the pressure sensor. Summary of the invention

[0006] In view of the shortcomings of the background technology, the present invention provides a programmable gain amplifier and a pressure sensor. The technical problem to be solved is that when the amplification factor is adjusted through an open-loop connected resistor network in the existing PGA, there are high requirements on the resistance value and it is greatly affected by external temperature and process.

[0007] To solve the above technical problems, in a first aspect, the present invention provides the following technical solutions: a programmable gain amplifier and a pressure sensor, comprising an operational amplifier A1, an operational amplifier A2, an operational amplifier A3, a first resistance branch, a second resistance branch and a third resistance branch;

[0008] The first connection end of the first resistance branch is electrically connected to the positive input end of the operational amplifier A3 through the first switch, and the second connection end of the first resistance branch is electrically connected to the negative input end of the operational amplifier A3 through the second switch;

[0009] The first N intermediate nodes of the first resistance branch are respectively electrically connected to the third switches, and the output ends of all the third switches are electrically connected to the negative input end of the operational amplifier A1; the last N intermediate nodes of the first resistance branch are respectively electrically connected to the fourth switches, and the output ends of all the fourth switches are electrically connected to the positive input end of the operational amplifier A2; along the direction from the first connection end of the first resistance branch to the second connection end of the first resistance branch, the output end of the operational amplifier A1 is electrically connected to the input end of the first third switch, and the output end of the operational amplifier A2 is electrically connected to the input end of the last fourth switch; N is a positive integer;

[0010] The first connection end of the second resistance branch is electrically connected to the positive output end of the operational amplifier A3, and the nodes of the second resistance branch other than the first connection end are electrically connected to fifth switches, and the output ends of all the fifth switches are electrically connected to the positive input end of the operational amplifier A3;

[0011] The first connection end of the third resistance branch is electrically connected to the negative output end of the operational amplifier A3, and the nodes of the third resistance branch except the first connection end are electrically connected to the sixth switch respectively, and the output ends of all the sixth switches are electrically connected to the negative input end of the operational amplifier A3 respectively.

[0012] In certain implementations of the first aspect, the first resistance branch includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a resistor R9 connected in series in sequence;

[0013] The resistor R1 is electrically connected to the positive input terminal of the operational amplifier A3 through a first switch, and the resistor R9 is electrically connected to the negative input terminal of the operational amplifier A3 through a second switch;

[0014] The first four intermediate nodes of the first resistance branch are electrically connected to third switches respectively, and the four third switches are a third switch S30, a third switch S31, a third switch S32 and a fourth switch S33;

[0015] The last four intermediate nodes of the first resistance branch are electrically connected to fourth switches respectively. The four fourth switches are a fourth switch S40, a fourth switch S41, a fourth switch S42 and a fourth switch S43.

[0016] In a certain implementation of the first aspect, the resistance value of the resistor R2 is the same as the resistance value of the resistor R8, the resistance value of the resistor R3 is the same as the resistance value of the resistor R7, and the resistance value of the resistor R4 is the same as the resistance value of the resistor R6;

[0017] The resistance value of the resistor R2 is six times that of the resistor R3 , and the resistance value of the resistor R2 is twelve times that of the resistor R4 .

[0018] In a certain embodiment of the first aspect, the second resistance branch includes a resistor R10, a resistor R11, a resistor R12 and a resistor R13 connected in series in sequence, the resistor R10 is electrically connected to the positive output terminal of the operational amplifier A3, and the second resistance branch is electrically connected to four fifth switches, which are respectively a fifth switch S50, a fifth switch S51, a fifth switch S52 and a fifth switch S53.

[0019] In a certain embodiment of the first aspect, the third resistance branch includes a resistor R20, a resistor R21, a resistor R22 and a resistor R23 connected in series in sequence, the resistor R20 is electrically connected to the negative output terminal of the operational amplifier A3, and the third resistance branch is electrically connected to four sixth switches, which are respectively a sixth switch S60, a sixth switch S61, a sixth switch S62 and a sixth switch S63.

[0020] In a certain implementation manner of the first aspect, the resistance value of the resistor R10 is the same as the resistance value of the resistor R20, the resistance value of the resistor R11 is the same as the resistance value of the resistor R21, the resistance value of the resistor R12 is the same as the resistance value of the resistor R22, and the resistance value of the resistor R13 is the same as the resistance value of the resistor R23;

[0021] The resistance value of the resistor R13 is twice that of the resistor R12 , and the resistance value of the resistor R13 is four times that of the resistor R11 and the resistor R10 .

[0022] In a certain implementation manner of the first aspect, the third switch S30, the fourth switch S40, the fifth switch S50 and the sixth switch S60 are turned on or off at the same time;

[0023] The third switch S31, the fourth switch S41, the fifth switch S51 and the sixth switch S61 are turned on or off at the same time;

[0024] The third switch S32, the fourth switch S42, the fifth switch S52 and the sixth switch S62 are turned on or off at the same time;

[0025] The third switch S33 , the fourth switch S43 , the fifth switch S53 and the sixth switch S63 are turned on or off at the same time.

[0026] In a second aspect, the present invention provides a pressure sensor comprising the above-mentioned programmable gain amplifier.

[0027] Compared with the prior art, the present invention has the following beneficial effects: in actual use, the first resistance branch, the second resistance branch, the third resistance branch, and the first to sixth switches of the present invention form a closed-loop resistance network, and the amplification factor of the amplifier adjusted by the closed-loop resistance network depends on the linear ratio of the resistances in the first resistance branch to the third resistance branch, rather than the absolute value of the resistance, thereby solving the problem of extremely high requirements on the process characteristics of resistor manufacturing when adjusting the amplifier factor. Moreover, the amplifier factor amplification depends on the resistance ratio and is relatively less affected by external temperature and process, thereby enhancing the linearity of a single operational amplifier and further improving the overall linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of a gain amplifier in an embodiment;

[0029] Figure 2 A schematic diagram of a gain amplifier for illustrating amplification factor calculation in an embodiment;

[0030] Figure 3 is a circuit diagram of an operational amplifier A1 in the embodiment;

[0031] Figure 4 for Figure 3 Simulation schematic diagram of the circuit;

[0032] Figure 5 is a circuit diagram of an operational amplifier A3 in the embodiment;

[0033] Figure 6 for Figure 5 Simulation schematic diagram of the circuit;

[0034] Figure 7 It is a simulation schematic diagram of the present invention. DETAILED DESCRIPTION

[0035] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0036] Embodiment 1

[0037] like Figure 1As shown, a programmable gain amplifier and a pressure sensor include an operational amplifier A1, an operational amplifier A2, an operational amplifier A3, a first resistor branch 1, a second resistor branch 2 and a third resistor branch 3;

[0038] The first connection end of the first resistor branch 1 is electrically connected to the positive input end of the operational amplifier A3 through the first switch S1, and the second connection end of the first resistor branch 1 is electrically connected to the negative input end of the operational amplifier A3 through the second switch S2;

[0039] The first N intermediate nodes of the first resistor branch 1 are electrically connected to the third switches respectively, and the output ends of all the third switches are electrically connected to the negative input end of the operational amplifier A1; the last N intermediate nodes of the first resistor branch 1 are electrically connected to the fourth switches respectively, and the output ends of all the fourth switches are electrically connected to the positive input end of the operational amplifier A2; along the direction from the first connection end of the first resistor branch 1 to the second connection end of the first resistor branch 1, the output end of the operational amplifier A1 is electrically connected to the input end of the first third switch, and the output end of the operational amplifier A2 is electrically connected to the input end of the last fourth switch; N is a positive integer;

[0040] The first connection end of the second resistance branch 2 is electrically connected to the positive output end of the operational amplifier A3, and the nodes of the second resistance branch 2 other than the first connection end are electrically connected to the fifth switches, and the output ends of all the fifth switches are electrically connected to the positive input end of the operational amplifier A3;

[0041] The first connection end of the third resistor branch 3 is electrically connected to the negative output end of the operational amplifier A3, and the nodes of the third resistor branch except the first connection end are electrically connected to the sixth switches, and the output ends of all the sixth switches are electrically connected to the negative input end of the operational amplifier A3.

[0042] In actual use, the first resistor branch 1, the second resistor branch 2, the third resistor branch 3, and the first to sixth switches of the present invention form a closed-loop resistor network, and the closed-loop resistor network adjusts the amplification factor of the amplifier depending on the linear ratio of the resistors in the first resistor branch 1 to the third resistor branch 3, rather than the absolute value of the resistance of the resistors, thereby solving the problem of extremely high requirements on the process characteristics of resistor manufacturing when adjusting the amplifier multiple. In addition, the amplifier multiple amplification depends on the resistance ratio and is relatively less affected by external temperature and process, thereby enhancing the linearity of a single operational amplifier and further improving the overall linearity.

[0043] For example, Figure 2 The circuit shown explains the amplification factor as follows:

[0044] Figure 2The operational amplifier A1 and operational amplifier A2 in the circuit form the first stage amplifier circuit, and the operational amplifier A3 forms the second stage amplifier circuit. For the first stage amplifier circuit, the gain calculation formula is as follows:

[0045]

[0046] For the second stage amplifier circuit, if the resistance value of resistor R1 is the same as that of resistor R3, the resistance value of resistor R4 is the same as that of resistor R6, and the resistance value of resistor R5 is the same as that of resistor R7, then the entire Figure 2 The gain of the circuit is:

[0047]

[0048] Specifically, in this embodiment, the first resistance branch 1 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8 and a resistor R9 connected in series in sequence;

[0049] The resistor R1 is electrically connected to the positive input terminal of the operational amplifier A3 through the first switch S1, and the resistor R9 is electrically connected to the negative input terminal of the operational amplifier A3 through the second switch S2;

[0050] The first four middle nodes of the first resistance branch 1 are electrically connected to third switches respectively, and the four third switches are a third switch S30, a third switch S31, a third switch S32 and a fourth switch S33;

[0051] The last four intermediate nodes of the first resistance branch 1 are electrically connected to fourth switches respectively. The four fourth switches are a fourth switch S40, a fourth switch S41, a fourth switch S42 and a fourth switch S43.

[0052] Specifically, in this embodiment, the resistance value of the resistor R2 is the same as the resistance value of the resistor R8, the resistance value of the resistor R3 is the same as the resistance value of the resistor R7, and the resistance value of the resistor R4 is the same as the resistance value of the resistor R6;

[0053] The resistance value of the resistor R2 is six times that of the resistor R3 , and the resistance value of the resistor R2 is twelve times that of the resistor R4 .

[0054] Specifically, in this embodiment, the second resistance branch 2 includes a resistor R10, a resistor R11, a resistor R12 and a resistor R13 connected in series in sequence, the resistor R10 is electrically connected to the positive output terminal of the operational amplifier A3, and the second resistance branch 2 is electrically connected to four fifth switches, which are respectively a fifth switch S50, a fifth switch S51, a fifth switch S52 and a fifth switch S53.

[0055] Specifically, in this embodiment, the third resistance branch 3 includes a resistor R20, a resistor R21, a resistor R22 and a resistor R23 connected in series in sequence, the resistor R20 is electrically connected to the negative output terminal of the operational amplifier A3, and the third resistance branch 3 is electrically connected to four sixth switches, which are respectively a sixth switch S60, a sixth switch S61, a sixth switch S62 and a sixth switch S63.

[0056] Specifically, in this embodiment, the resistance value of the resistor R10 is the same as the resistance value of the resistor R20, the resistance value of the resistor R11 is the same as the resistance value of the resistor R21, the resistance value of the resistor R12 is the same as the resistance value of the resistor R22, and the resistance value of the resistor R13 is the same as the resistance value of the resistor R23;

[0057] The resistance value of the resistor R13 is twice the resistance value of the resistor R12 , and the resistance value of the resistor R13 is four times the resistance value of the resistor R11 and the resistance value of the resistor R10 .

[0058] Specifically, in this embodiment, the third switch S30, the fourth switch S40, the fifth switch S50 and the sixth switch S60 are turned on or off at the same time;

[0059] The third switch S31, the fourth switch S41, the fifth switch S51 and the sixth switch S61 are turned on or off at the same time;

[0060] The third switch S32, the fourth switch S42, the fifth switch S52 and the sixth switch S62 are turned on or off at the same time;

[0061] The third switch S33, the fourth switch S43, the fifth switch S53 and the sixth switch S63 are turned on or off at the same time. At the same time, only one of the third switch S30, the third switch S31, the third switch S32 and the fourth switch S33 can be turned on.

[0062] In actual use, a decoding circuit may be provided to control the on and off of the third switch, the fourth switch, the fifth switch and the sixth switch.

[0063] Now, the amplification factor of the present invention is described in combination with the on-off conditions of the third switch, the fourth switch and the fifth switch and the resistance ratio of each resistance branch, as follows:

[0064] When the third switch S30 is turned on, the gains of the two-stage amplifier circuit of the present invention are 1 and 1 respectively, when the third switch S31 is turned on, the gains of the two-stage amplifier circuit of the present invention are 4 and 2 respectively, when the third switch S32 is turned on, the gains of the two-stage amplifier circuit of the present invention are 8 and 4 respectively, and when the third switch S33 is turned on, the gains of the two-stage amplifier circuit of the present invention are 16 and 8 respectively. Since the overall gain of the present invention is obtained by multiplying the gains of the two-stage amplifier circuits, the present invention realizes dynamic control of the overall amplification factor at four gears of 1, 8, 32, and 128.

[0065] In a certain implementation, the number of resistors and the resistance value record in the first resistor branch 1, the number of resistors and the resistance value ratio in the second resistor branch 2, and the number of resistors and the resistance value ratio in the third resistor branch 3 can be adjusted according to the needs, so as to achieve the adjustment of the amplification factor of different gears of the amplifier. In addition, the number of all third switches, the number of all fourth switches, the number of all fifth switches, and the number of all sixth switches need to be the same.

[0066] For traditional PGA, there are three classic structures, including three op amp structure, capacitor-coupled instrumentation amplifier and current feedback structure. Among them, the advantages of the three op amp structure are high gain, high bandwidth, high input impedance and high common-mode rejection ratio, but it has the limitations of high power consumption, high noise, large area and large offset. The advantages of the capacitor-coupled instrumentation amplifier are good stability, low offset, high phase margin (phase distortion is not easy to occur at high frequency), but it has the limitations of limited gain and low input impedance. The advantages of the current feedback structure are high input impedance and high common-mode rejection ratio, but it has the limitations of narrow linear range, limited gain accuracy and high noise. Therefore, the existing three op amp structure has limitations in terms of high noise, power consumption and area. At present, it is necessary to make the gain amplifier achieve high precision, wide bandwidth and high integration while maintaining high gain.

[0067] Based on the above considerations, the operational amplifier A1 of the present application has the same structure as the operational amplifier A2, and the circuit is as follows: Figure 3 As shown, they all include a MOS tube MP1, the source of the MOS tube MP1 is electrically connected to the source of the MOS tube MP3, the source of the MOS tube MP4, the source of the MOS tube MP7, the source of the MOS tube MP9 and the source of the MOS tube MP11, respectively, for inputting a working power supply;

[0068] The drain of the MOS transistor MP1 is electrically connected to the source of the MOS transistor MP2, and the gate of the MOS transistor MP1 is electrically connected to the gate of the MOS transistor MP4, the drain of the MOS transistor MP2, and the drain of the MOS transistor NP3 respectively;

[0069] The gate of the MOS transistor MP3 is electrically connected to the gate of the MOS transistor MP2, the source of the MOS transistor MP3 and the drain of the MOS transistor NP5 respectively;

[0070] The drain of the MOS transistor MP4 is electrically connected to the source of the MOS transistor MP5 and the source of the MOS transistor MP6, respectively; the gate of the MOS transistor MP5 is the positive input terminal of the operational amplifier A1; the gate of the MOS transistor MP6 is the negative input terminal of the operational amplifier A1; the drain of the MOS transistor MP5 is electrically connected to the source of the MOS transistor NP7 and the drain of the MOS transistor NP8, respectively; the drain of the MOS transistor MP6 is electrically connected to the source of the MOS transistor NP9 and the drain of the MOS transistor NP10, respectively; the gate of the MOS transistor NP9 is electrically connected to the gate of the MOS transistor NP7, the gate of the MOS transistor NP5, the gate of the MOS transistor NP3, the gate of the MOS transistor NP1, and the drain of the MOS transistor NP1, respectively; the drain of the MOS transistor NP1 is used for inputting the bias current Ibias;

[0071] The source of the MOS transistor NP1 is electrically connected to the drain of the MOS transistor NP2, the gate of the MOS transistor NP2, the gate of the MOS transistor NP4, the gate of the MOS transistor NP6, the gate of the MOS transistor NP8, the gate of the MOS transistor NP10 and the gate of the MOS transistor NP11 respectively; the drain of the MOS transistor NP4 is electrically connected to the source of the MOS transistor NP3; the drain of the MOS transistor NP6 is electrically connected to the source of the MOS transistor NP5; the source of the MOS transistor NP2, the source of the MOS transistor NP4, the source of the MOS transistor NP6, the source of the MOS transistor NP8, the source of the MOS transistor NP10 and the source of the MOS transistor NP11 are all grounded;

[0072] The drain of the MOS transistor MP7 is electrically connected to the source of the MOS transistor MP8, the drain of the MOS transistor MP9 is electrically connected to the source of the MOS transistor MP10, the gate of the MOS transistor MP7 is electrically connected to the gate of the MOS transistor MP9, the drain of the MOS transistor MP8 and the drain of the MOS transistor NP7, the gate of the MOS transistor MP8 is electrically connected to the gate of the MOS transistor MP10 and the drain of the MOS transistor MP3, the drain of the MOS transistor MP10 is electrically connected to the drain of the MOS transistor NP9, the gate of the MOS transistor MP11 is electrically connected to one end of the resistor R30, the other end of the resistor R30 is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is electrically connected to the drain of the MOS transistor MP11 and the drain of the MOS transistor NP11, and is the output end of the operational amplifier A1.

[0073] for Figure 3 In the circuit shown, MOS transistors MP1 to MP11 and MOS transistors NP1 to MOS transistors NP11 form a first-stage amplifier circuit;

[0074] The working power supply is connected to the source of MOS tubes MP1, MP3, MP4, MP7, MP9 and MP11 to ensure that the threshold voltage required for the above MOS tubes to be turned on is met;

[0075] MOS tube MP3, MOS tube NP1 and MOS tube NP2 adopt diode connection method and play the role of small signal resistor in the circuit;

[0076] The bias current Ibias provides 10μA bias current for MOS tubes NP1-NP10. In the first-stage amplifier circuit, MOS tubes NP1-NP6 act as current sources with relatively ideal conditions to provide stable current input for the amplifier tubes. The gate of MP1 transistor is connected to the gate of MP4 transistor, and the drain of MOS tube MP4 is connected to the source of MOS tubes MP5 and MP6, providing stable bias current for MOS tubes MP5 and MP6.

[0077] The gate of MOS tube MP5 is connected to the inverting input signal Vin, and the gate of MOS tube MP6 is connected to the positive input signal Vip, and the two form a first-stage differential amplifier circuit. The output signal of MOS tube MP5 is connected to the drain of MOS tube NP8 and the source of NP7, and the output signal of MOS tube MP6 is connected to the drain of MOS tube NP10 and the source of MOS tube NP9. MOS tube MP7-MOS tube MP10 and MOS tube NP7-MOS tube NP10 are combined into a common source and common gate structure. The common source stage provides voltage gain, and the common gate stage provides current gain. The multiplication of the two can effectively increase the total gain of the circuit, and the parasitic capacitance of the common source stage and the common gate stage can offset each other, thereby reducing the total parasitic capacitance and widening the bandwidth of the operational amplifier;

[0078] The common source amplifier circuit formed by the MOS tube MP11 is the second-stage amplifier circuit, and the resistor R1 and the capacitor C1 form an RC bias circuit, which effectively mitigates the influence caused by the Miller effect.

[0079] Figure 3 When the circuit is actually used, the signal is input as a differential pair to suppress temperature drift and common mode signals. Figure 4 In the middle of the circuit is a current mirror structure that can slow down the Miller effect and increase the gain-bandwidth product. The last stage selects a common-source amplifier circuit with a current source as a load to improve the gain amplification effect. This can not only utilize the high output resistance of the MOS tube itself, but also save redundant layout area and increase the integration of the circuit compared with the traditional common-source amplifier circuit with a resistor as a load because the load itself is used as part of the circuit bias.

[0080] In addition, in order to reduce the impact of the low main pole of the operational amplifier A1 on the bandwidth, in this embodiment, the output resistance at the connection can be reduced by adjusting the size of the MOS tube, providing a wider range of input swing for the first-stage operational amplifier to meet the needs of high-frequency application scenarios. In addition, on the basis of ensuring that the operational amplifier meets the frequency band requirements, constraining the gain bandwidth of the operational amplifier realizes the constraint of the operational amplifier establishment speed, and realizes the establishment of the signal in a shorter time.

[0081] right Figure 3 The circuit shown is simulated, and the specific results are as follows Figure 4 As shown, Figure 4 The upper curve in the figure is the amplitude-frequency response curve, and the lower curve is the phase-frequency response curve. Figure 4 It can be obtained that the maximum open-loop gain of operational amplifier A1 and amplifier A2 is 105.9604dB, the bandwidth is 24.6799Hz, and the cut-off frequency is about 4.9MHz.

[0082] In this embodiment, the circuit of the operational amplifier A3 is as follows: Figure 5 As shown, it includes a MOS transistor PM1, and the source of the MOS transistor PM1 is electrically connected to the source of the MOS transistor PM3, the source of the MOS transistor PM5, the source of the MOS transistor PM6, the source of the MOS transistor PM8, the source of the MOS transistor PM11, the source of the MOS transistor PM13, the source of the MOS transistor PM14, and the source of the MOS transistor PM15 respectively;

[0083] The drain of MOS transistor PM1 is electrically connected to the source of MOS transistor PM2, the drain of MOS transistor PM3 is electrically connected to the source of MOS transistor PM4, the gate of MOS transistor PM1 is electrically connected to the drain of MOS transistor PM2, the drain of MOS transistor NM2, the gate of MOS transistor PM6, the gate of MOS transistor PM8, the gate of MOS transistor PM11, the gate of MOS transistor PM14 and the gate of MOS transistor PM15 respectively, for inputting bias voltage Vb1; the gate of MOS transistor PM3 is electrically connected to the gate of MOS transistor PM4, the gate of MOS transistor PM2, the drain of MOS transistor PM4 and the drain of MOS transistor NM6 respectively, for inputting bias voltage Vb1. voltage Vb2, the gate of MOS tube NM6 is electrically connected to the gate of MOS tube NM1, the drain of MOS tube NM1, the gate of MOS tube NM2, the gate of MOS tube NM8 and the gate of MOS tube NM11 respectively, the drain of MOS tube NM1 is used to input bias current I-bias, the source of MOS tube NM1 is electrically connected to the drain of MOS tube NM3, the gate of MOS tube NM3, the gate of MOS tube NM4 and the gate of MOS tube NM5 respectively, the drain of MOS tube NM5 is electrically connected to the source of MOS tube NM6, and the source of MOS tube NM5, the source of MOS tube NM4 and the source of MOS tube NM5 are all grounded;

[0084] The gate of the MOS transistor PM5 is electrically connected to one end of the resistor R31, the drain of the MOS transistor PM7 and the drain of the MOS transistor NM8 respectively. The other end of the resistor R31 is electrically connected to the drain of the MOS transistor PM5 and the drain of the MOS transistor NM7 respectively through the capacitor C2. The drain of the MOS transistor PM5 is the positive output end of the operational amplifier A3. The gate of the MOS transistor NM7 is used to input the bias voltage Vb4. The source of the MOS transistor NM7 is grounded.

[0085] The source of the MOS transistor PM6 is electrically connected to the source of the MOS transistor PM7, the drain of the MOS transistor PM8 is electrically connected to the source of the MOS transistor PM9 and the source of the MOS transistor PM10 respectively, the gate of the MOS transistor PM9 is the positive input terminal of the operational amplifier A3, the gate of the MOS transistor PM10 is the negative input terminal of the operational amplifier A3, the drain of the MOS transistor PM9 is electrically connected to the source of the MOS transistor NM8 and the drain of the MOS transistor NM9 respectively, the drain of the MOS transistor PM10 is electrically connected to the source of the MOS transistor NM11 and the drain of the MOS transistor NM10 respectively, the gate of the MOS transistor NM9 is electrically connected to the gate of the MOS transistor NM10 and the gate of the MOS transistor NM13 respectively, and the source of the MOS transistor NM9, the source of the MOS transistor NM10 and the source of the MOS transistor NM13 are all grounded;

[0086] The drain of the MOS transistor PM11 is electrically connected to the source of the MOS transistor PM12, the gate of the MOS transistor PM12 is used to input the bias voltage Vb2, the drain of the MOS transistor PM12 is electrically connected to the drain of the MOS transistor NM11, one end of the resistor R32 and the gate of the MOS transistor PM13 respectively, the other end of the resistor R32 is electrically connected to the drain of the MOS transistor PM13 and the drain of the MOS transistor NM12 respectively through the capacitor C3, the drain of the MOS transistor PM13 is the negative output end of the operational amplifier A3, the gate of the MOS transistor NM12 is used to input the bias voltage Vb4, and the source of the MOS transistor NM12 is grounded;

[0087] The drain of the MOS transistor PM14 is electrically connected to the source of the MOS transistor PM16 and the source of the MOS transistor PM17 respectively, the drain of the MOS transistor PM15 is electrically connected to the source of the MOS transistor PM18 and the source of the MOS transistor PM19 respectively, the gate of the MOS transistor PM16 and the gate of the MOS transistor PM19 are respectively used to input the reference voltage Vref, the gate of the MOS transistor PM17 is electrically connected to the drain of the MOS transistor PM5, the MOS transistor PM18 is electrically connected to the drain of the MOS transistor PM13, the drain of the MOS transistor PM16 and the drain of the MOS transistor P19 are both grounded, and the drain of the MOS transistor PM17 and the drain of the MOS transistor PM18 are both electrically connected to the drain of the MOS transistor NM13 and the gate of the MOS transistor NM13.

[0088] for Figure 5 In the circuit shown, MOS tubes PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12, PM13, NM7, NM8, NM9, NM10, NM11, and NM12 together constitute a two-stage operational amplifier; MOS tubes PM14, PM15, PM16, PM17, PM18, PM19, and NM13 together constitute a common-mode feedback.

[0089] In actual use, the common-mode input level signal received by the front end of the pressure sensor often changes slightly. In order to ensure the stability of the subsequent sampling circuit, a stable common-mode level needs to be provided. In the design of PGA, operational amplifier A3 pays special attention to circuit stability. Based on this, on the basis of ensuring the stability of the differential input of operational amplifier A3, in order to reduce the noise of operational amplifier A3 and improve the common-mode rejection ratio, a common-mode feedback with a specific structure is introduced into operational amplifier A3 to eliminate the common-mode change of the input signal;

[0090] In addition, in order to reduce unnecessary errors at the front end of the pressure sensor and achieve higher accuracy requirements, the folded common source and common gate structure used in the circuit 5 effectively solves the problem of increasing the signal swing of the stacked differential pair. In addition, the folded common source and common gate structure reduces the size and power consumption of the MOS tube while achieving extremely high accuracy. A constant current source slightly larger than the tail current source is connected in parallel next to the differential pair to ensure that the transconductance of the differential pair is greater than zero, so that the gain of the amplifier is always positive.

[0091] Combining the above two paragraphs, Figure 5 The circuit achieves a good power supply rejection ratio in a wide frequency band by reducing current noise, increasing input impedance and reducing the load effect on the sensor, further improving the amplification performance of the circuit and enabling the pressure sensor to obtain extremely high accuracy.

[0092] right Figure 5 The circuit is simulated for frequency characteristics, and the simulation results are as follows Figure 6 As shown, Figure 6 The ordinate in the upper figure is the amplitude, and the ordinate in the lower figure is the phase. Figure 6 You can get it in Figure 5 The maximum open-loop gain of the circuit is 111.3491dB, the bandwidth is 12.8229Hz, and the cut-off frequency is about 4.9MHz;

[0093] In addition, the common-mode feedback stability results obtained by simulation are as follows: the main pole wp1 = 2.39807KHz, the phase is -45.0°, the loop gain is 78.153dB, the gain-bandwidth product GBW = 26.8722MHz, and the phase margin PM = 73°. The common-mode feedback of this circuit meets the index requirements.

[0094] The gain amplifier of the present invention is subjected to parameter simulation, and the simulation results are as follows: Figure 7 As shown, from Figure 7 It can be obtained that when the input differential mode AC small signal AV = 10mV, the measured output voltage is 1.27835V when the frequency is 1KHz, indicating that the magnification is 128 and the error is 0.128%. When the output voltage is 319.79mV, it means that the magnification is 32 and the error is 0.0656%. When the output voltage is 79.972mV, the magnification is 8 and the error is 0.125%. When the output voltage is 9.99869mV, the magnification is 1 and the error is 0.0131%.

[0095] Embodiment 2

[0096] This embodiment provides a pressure sensor, including a programmable gain amplifier in the first embodiment.

[0097] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A programmable gain amplifier, characterized in that: It includes an operational amplifier A1, an operational amplifier A2, an operational amplifier A3, a first resistance branch, a second resistance branch, and a third resistance branch; The first connection end of the first resistance branch is electrically connected to the positive input terminal of the operational amplifier A3 through a first switch, and the second connection end of the first resistance branch is electrically connected to the negative input terminal of the operational amplifier A3 through a second switch; The first N intermediate nodes of the first resistance branch are respectively electrically connected to a third switch, and the output terminals of all the third switches are electrically connected to the negative input terminal of the operational amplifier A1; the last N intermediate nodes of the first resistance branch are respectively electrically connected to a fourth switch, and the output terminals of all the fourth switches are electrically connected to the positive input terminal of the operational amplifier A2; along the direction from the first connection terminal of the first resistance branch to the second connection terminal of the first resistance branch, the output terminal of the operational amplifier A1 is electrically connected to the input terminal of the first third switch, and the output terminal of the operational amplifier A2 is electrically connected to the input terminal of the last fourth switch; N is a positive integer; The first connection end of the second resistance branch is electrically connected to the positive output end of the operational amplifier A3, and the nodes of the second resistance branch other than the first connection end are electrically connected to fifth switches, and the output ends of all the fifth switches are electrically connected to the positive input end of the operational amplifier A3. The first connection end of the third resistance branch is electrically connected to the negative output end of the operational amplifier A3, and the nodes of the third resistance branch other than the first connection end are electrically connected to the sixth switch, and the output ends of all the sixth switches are electrically connected to the negative input end of the operational amplifier A3.

2. A programmable gain amplifier according to claim 1, characterized in that: The first resistance branch includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8 and a resistor R9 connected in series in sequence; The resistor R1 is electrically connected to the positive input terminal of the operational amplifier A3 through a first switch, and the resistor R9 is electrically connected to the negative input terminal of the operational amplifier A3 through a second switch; The first four intermediate nodes of the first resistance branch are electrically connected to third switches, respectively. The four third switches are a third switch S30, a third switch S31, a third switch S32, and a fourth switch S33. The last four intermediate nodes of the first resistance branch are electrically connected to fourth switches respectively. The four fourth switches are a fourth switch S40, a fourth switch S41, a fourth switch S42 and a fourth switch S43.

3. A programmable gain amplifier according to claim 2, characterized in that: The resistance value of the resistor R2 is the same as the resistance value of the resistor R8, the resistance value of the resistor R3 is the same as the resistance value of the resistor R7, and the resistance value of the resistor R4 is the same as the resistance value of the resistor R6; The resistance of the resistor R2 is six times that of the resistor R3 , and the resistance of the resistor R2 is twelve times that of the resistor R4 .

4. A programmable gain amplifier according to claim 2, characterized in that: The second resistance branch includes a resistor R10, a resistor R11, a resistor R12, and a resistor R13 connected in series in sequence. The resistor R10 is electrically connected to the positive output terminal of the operational amplifier A3. The second resistance branch is electrically connected to four fifth switches, which are respectively a fifth switch S50, a fifth switch S51, a fifth switch S52, and a fifth switch S53.

5. A programmable gain amplifier according to claim 4, characterized in that: The third resistance branch includes a resistor R20, a resistor R21, a resistor R22, and a resistor R23 connected in series in sequence. The resistor R20 is electrically connected to the negative output terminal of the operational amplifier A3. The third resistance branch is electrically connected to four sixth switches, namely a sixth switch S60, a sixth switch S61, a sixth switch S62, and a sixth switch S63.

6. A programmable gain amplifier according to claim 5, characterized in that: The resistance value of the resistor R10 is the same as the resistance value of the resistor R20, the resistance value of the resistor R11 is the same as the resistance value of the resistor R21, the resistance value of the resistor R12 is the same as the resistance value of the resistor R22, and the resistance value of the resistor R13 is the same as the resistance value of the resistor R23; The resistance of the resistor R13 is twice that of the resistor R12 , and the resistance of the resistor R13 is four times that of the resistor R11 and the resistor R10 .

7. The programmable gain amplifier according to claim 5, wherein: The third switch S30, the fourth switch S40, the fifth switch S50 and the sixth switch S60 are turned on or off at the same time; The third switch S31, the fourth switch S41, the fifth switch S51 and the sixth switch S61 are turned on or off at the same time; The third switch S32, the fourth switch S42, the fifth switch S52 and the sixth switch S62 are turned on or off at the same time; The third switch S33 , the fourth switch S43 , the fifth switch S53 and the sixth switch S63 are turned on or off at the same time.

8. A programmable gain amplifier according to any one of claims 1 to 7, characterized in that: The operational amplifiers A1 and A2 have the same circuit structure, both including a MOS transistor MP1. The source of the MOS transistor MP1 is electrically connected to the source of the MOS transistors MP3, MP4, MP7, MP9, and MP11, respectively, for inputting a working power supply. The drain of the MOS transistor MP1 is electrically connected to the source of the MOS transistor MP2, and the gate of the MOS transistor MP1 is electrically connected to the gate of the MOS transistor MP4, the drain of the MOS transistor MP2, and the drain of the MOS transistor NP3 respectively; The gate of the MOS transistor MP3 is electrically connected to the gate of the MOS transistor MP2, the source of the MOS transistor MP3, and the drain of the MOS transistor NP5 respectively; The drain of the MOS transistor MP4 is electrically connected to the source of the MOS transistor MP5 and the source of the MOS transistor MP6, respectively. The gate of the MOS transistor MP5 is the positive input terminal of the operational amplifier A1, and the gate of the MOS transistor MP6 is the negative input terminal of the operational amplifier A1. The drain of the MOS transistor MP5 is electrically connected to the source of the MOS transistor NP7 and the drain of the MOS transistor NP8, respectively. The drain of the MOS transistor MP6 is electrically connected to the source of the MOS transistor NP9 and the drain of the MOS transistor NP10, respectively. The gate of the MOS transistor NP9 is electrically connected to the gate of the MOS transistor NP7, the gate of the MOS transistor NP5, the gate of the MOS transistor NP3, the gate of the MOS transistor NP1, and the drain of the MOS transistor NP1, respectively. The drain of the MOS transistor NP1 is used to input the bias current Ibias. The source of MOS transistor NP1 is electrically connected to the drain of MOS transistor NP2, the gate of MOS transistor NP2, the gate of MOS transistor NP4, the gate of MOS transistor NP6, the gate of MOS transistor NP8, the gate of MOS transistor NP10, and the gate of MOS transistor NP11, respectively. The drain of MOS transistor NP4 is electrically connected to the source of MOS transistor NP3, the drain of MOS transistor NP6 is electrically connected to the source of MOS transistor NP5, and the source of MOS transistor NP2, the source of MOS transistor NP4, the source of MOS transistor NP6, the source of MOS transistor NP8, the source of MOS transistor NP10, and the source of MOS transistor NP11 are all grounded. The drain of the MOS transistor MP7 is electrically connected to the source of the MOS transistor MP8, the drain of the MOS transistor MP9 is electrically connected to the source of the MOS transistor MP10, the gate of the MOS transistor MP7 is electrically connected to the gate of the MOS transistor MP9, the drain of the MOS transistor MP8, and the drain of the MOS transistor NP7, respectively, the gate of the MOS transistor MP8 is electrically connected to the gate of the MOS transistor MP10 and the drain of the MOS transistor MP3, respectively, the drain of the MOS transistor MP10 is electrically connected to the drain of the MOS transistor NP9, the gate of the MOS transistor MP11 is electrically connected to one end of the resistor R30, the other end of the resistor R30 is electrically connected to one end of the capacitor C1, and the other end of the capacitor C1 is electrically connected to the drain of the MOS transistor MP11 and the drain of the MOS transistor NP11, respectively, and serves as the output end of the operational amplifier A1.

9. A programmable gain amplifier according to any one of claims 1 to 7, characterized in that: The operational amplifier A3 includes a MOS transistor PM1, the source of which is electrically connected to the source of the MOS transistor PM3, the source of the MOS transistor PM5, the source of the MOS transistor PM6, the source of the MOS transistor PM8, the source of the MOS transistor PM11, the source of the MOS transistor PM13, the source of the MOS transistor PM14, and the source of the MOS transistor PM15 respectively; The drain of MOS transistor PM1 is electrically connected to the source of MOS transistor PM2, the drain of MOS transistor PM3 is electrically connected to the source of MOS transistor PM4, the gate of MOS transistor PM1 is electrically connected to the drain of MOS transistor PM2, the drain of MOS transistor NM2, the gate of MOS transistor PM6, the gate of MOS transistor PM8, the gate of MOS transistor PM11, the gate of MOS transistor PM14, and the gate of MOS transistor PM15, respectively, for inputting bias voltage Vb1; the gate of MOS transistor PM3 is electrically connected to the gate of MOS transistor PM4, the gate of MOS transistor PM2, the drain of MOS transistor PM4, and the drain of MOS transistor NM6, respectively, for inputting bias voltage Vb1. voltage Vb2, the gate of MOS transistor NM6 is electrically connected to the gate of MOS transistor NM1, the drain of MOS transistor NM1, the gate of MOS transistor NM2, the gate of MOS transistor NM8, and the gate of MOS transistor NM11, respectively; the drain of MOS transistor NM1 is used to input bias current I-bias; the source of MOS transistor NM1 is electrically connected to the drain of MOS transistor NM3, the gate of MOS transistor NM3, the gate of MOS transistor NM4, and the gate of MOS transistor NM5, respectively; the drain of MOS transistor NM5 is electrically connected to the source of MOS transistor NM6; the source of MOS transistor NM5, the source of MOS transistor NM4, and the source of MOS transistor NM5 are all grounded; The gate of MOS transistor PM5 is electrically connected to one end of resistor R31, the drain of MOS transistor PM7, and the drain of MOS transistor NM8, respectively. The other end of resistor R31 is electrically connected to the drain of MOS transistor PM5 and the drain of MOS transistor NM7, respectively, through capacitor C2. The drain of MOS transistor PM5 is the positive output terminal of operational amplifier A3. The gate of MOS transistor NM7 is used to input bias voltage Vb4. The source of MOS transistor NM7 is grounded. The source of MOS transistor PM6 is electrically connected to the source of MOS transistor PM7. The drain of MOS transistor PM8 is electrically connected to the source of MOS transistor PM9 and the source of MOS transistor PM10, respectively. The gate of MOS transistor PM9 is the positive input terminal of operational amplifier A3. The gate of MOS transistor PM10 is the negative input terminal of operational amplifier A3. The drain of MOS transistor PM9 is electrically connected to the source of MOS transistor NM8 and the drain of MOS transistor NM9, respectively. The drain of MOS transistor PM10 is electrically connected to the source of MOS transistor NM11 and the drain of MOS transistor NM10, respectively. The gate of MOS transistor NM9 is electrically connected to the gate of MOS transistor NM10 and the gate of MOS transistor NM13, respectively. The source of MOS transistor NM9, the source of MOS transistor NM10, and the source of MOS transistor NM13 are all grounded. The drain of the MOS transistor PM11 is electrically connected to the source of the MOS transistor PM12. The gate of the MOS transistor PM12 is used to input a bias voltage Vb2. The drain of the MOS transistor PM12 is electrically connected to the drain of the MOS transistor NM11, one end of the resistor R32, and the gate of the MOS transistor PM13, respectively. The other end of the resistor R32 is electrically connected to the drain of the MOS transistor PM13 and the drain of the MOS transistor NM12, respectively, through the capacitor C3. The drain of the MOS transistor PM13 is the negative output terminal of the operational amplifier A3. The gate of the MOS transistor NM12 is used to input a bias voltage Vb4. The source of the MOS transistor NM12 is grounded. The drain of the MOS transistor PM14 is electrically connected to the source of the MOS transistor PM16 and the source of the MOS transistor PM17, respectively. The drain of the MOS transistor PM15 is electrically connected to the source of the MOS transistor PM18 and the source of the MOS transistor PM19, respectively. The gates of the MOS transistor PM16 and the gates of the MOS transistor PM19 are respectively used to input a reference voltage Vref. The gate of the MOS transistor PM17 is electrically connected to the drain of the MOS transistor PM5. The MOS transistor PM18 is electrically connected to the drain of the MOS transistor PM13. The drain of the MOS transistor PM16 and the drain of the MOS transistor P19 are both grounded. The drains of the MOS transistor PM17 and the drains of the MOS transistor PM18 are both electrically connected to the drain of the MOS transistor NM13 and the gate of the MOS transistor NM13.

10. A pressure sensor, characterized in that: A programmable gain amplifier comprising any one of claims 1-9.

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