Comparison circuit, semiconductor device, electronic component, and electronic apparatus

Abstract

Provided is a comparison circuit capable of directly inputting a negative voltage to be compared. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The comparison circuit compares a negative voltage with a negative reference voltage, and outputs a first output voltage from a first output terminal according to a comparison result. A negative voltage is input to the first input terminal. A positive reference voltage is input to the second input terminal. The positive reference voltage is set in a comparison manner. The differential pair includes a first n-channel transistor and a second n-channel transistor each including a back gate. The first input terminal is electrically connected to the back gate of the first n-channel transistor. The second input terminal is electrically connected to the gate of the second n-channel transistor.

Description

[0001] This application is a divisional application of an application filed on May 22, 2018, entered the Chinese national phase on November 20, 2019, with Chinese application number 201880033269.6 and invention name “Comparison circuit, semiconductor device, electronic component and electronic device”. Technical Field

[0002] One embodiment of the present invention disclosed in the specification, drawings, and claims of this application (hereinafter referred to as the specification, etc.) relates to a semiconductor device, its operation method, its use method, its manufacturing method, etc. Note that one embodiment of the present invention is not limited to the above technical field. Background Art

[0003] Semiconductor devices using negative voltages are known. For example, in order to reduce threshold leakage current, the substrate bias voltage of an n-channel MOS transistor is a negative voltage, and the substrate bias voltage of a p-channel MOS transistor is a positive voltage (for example, Patent Document 1). In flash memory, negative voltages are used depending on the operation (for example, Patent Document 2).

[0004] Negative voltage can be generated by a charge pump circuit. Patent documents 2 and 3 disclose technologies for generating negative voltage with high precision. In Patent documents 2 and 3, the negative voltage output from the charge pump circuit is converted into a positive voltage, and the difference between the positive voltage and the positive reference voltage is detected by a comparison circuit, and the operation of the charge pump circuit is controlled according to the detection result.

[0005] In this specification and the like, a ground voltage (GND) is regarded as 0 V, and positive voltage and negative voltage are defined with reference to the ground voltage.

[0006] A transistor including a metal oxide in a channel formation region (hereinafter, such a transistor is also referred to as an oxide semiconductor transistor or an OS transistor) is known. Various semiconductor devices are manufactured by a hybrid CMOS process of an OS transistor and a Si transistor (for example, Non-Patent Document 1). As shown in Non-Patent Document 1, an OS transistor can be stacked on a Si transistor.

[0007] Si transistors can control the threshold voltage (hereinafter sometimes referred to as Vt) by introducing impurities. However, reliable technology for controlling the threshold voltage of OS transistors has not yet been established. For example, in Patent Document 4, the threshold voltage of an OS transistor including a first gate electrode (also referred to as a gate or front gate) and a second gate electrode (also referred to as a back gate) is controlled by controlling the voltage of the second gate electrode. The threshold voltage of the OS transistor of an n-channel transistor drifts toward the positive side when a negative voltage is input to the second gate electrode.

[0008] [References]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 11-191611

[0011] [Patent Document 2] Japanese Patent Application Publication No. 7-231647

[0012] [Patent Document 3] Japanese Patent Application Publication No. 11-150230

[0013] [Patent Document 4] Japanese Patent Application Publication No. 2012-069932

[0014] [Non-patent document 1] T.Onuki et al., "Embedded Memory and ARM Cortex-M0 CoreUsing 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FETIntegrated with 65-nm Si CMOS," Symp.VLSI Circuits Dig.Tech.Papers, pp.124-125, Jun.2016. Summary of the invention

[0015] An object of one embodiment of the present invention is to provide a comparison circuit capable of directly inputting a negative voltage to be compared, generating a highly accurate negative voltage, and reducing power consumption.

[0016] Note that one embodiment of the present invention does not need to achieve all of the above-mentioned purposes. The recording of multiple purposes does not hinder the existence of each other's purposes. Other purposes can be naturally known from the records of this specification, etc., and such purposes may become the purpose of one embodiment of the present invention.

[0017] (1) One embodiment of the present invention is a comparison circuit including a first input terminal, a second input terminal, a first output terminal, and a differential input circuit. The comparison circuit compares a negative voltage with a negative reference voltage and outputs a first output voltage from the first output terminal according to the comparison result. A negative voltage is input to the first input terminal. A positive reference voltage is input to the second input terminal. The positive reference voltage is set in a comparison manner. The differential input circuit includes a differential pair of a first n-channel transistor and a second n-channel transistor. The first n-channel transistor and the second n-channel transistor both include a gate and a back gate. A first bias voltage is input to the gate of the first n-channel transistor. The back gate of the first n-channel transistor is electrically connected to the first input terminal. The gate of the second n-channel transistor is electrically connected to the second input terminal. A second bias voltage is input to the back gate of the second n-channel transistor.

[0018] (2) In the above embodiment (1), the channel formation regions of the first n-channel transistor and the second n-channel transistor include a metal oxide.

[0019] (3) The comparison circuit according to the above embodiment (1) or (2) is a dynamic comparison circuit. The differential input circuit includes a latch circuit electrically connected to the differential pair.

[0020] (4) One embodiment of the present invention is a semiconductor device, comprising: a step-down charge pump circuit; a drive circuit; and a comparison circuit according to any one of the above embodiments (1) to (3). An output terminal of the step-down charge pump is electrically connected to a first input terminal of the comparison circuit. A first output voltage is input from the comparison circuit to the drive circuit. The drive circuit generates a clock signal for driving the step-down charge pump based on the first output voltage.

[0021] According to one embodiment of the present invention, a comparison circuit can be provided that can directly input a negative voltage to be compared, can generate a high-precision negative voltage, and can reduce power consumption.

[0022] In one embodiment of the present invention, it is not necessary to obtain all the above effects. The description of multiple effects does not prevent the existence of other effects. In one embodiment of the present invention, purposes other than the above purposes, effects other than the above effects, and novel features can be naturally known from the description in this specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A and Figure 1B is a circuit diagram showing a structural example of a comparison circuit, Figure 1C is a diagram schematically showing drain current-gate voltage characteristics of a transistor.

[0024] Figure 2 is a circuit diagram showing a structural example of a comparison circuit.

[0025] Figure 3A and Figure 3B is a circuit diagram showing a structural example of a comparison circuit.

[0026] FIG. 4A to FIG. 4C is a circuit diagram showing a structural example of a comparison circuit.

[0027] Figure 5 is a circuit diagram showing a structural example of a comparison circuit.

[0028] Figure 6 is a block diagram showing a structural example of a negative voltage supply device.

[0029] Figure 7is a circuit diagram showing a structural example of a charge pump circuit.

[0030] FIG. 8A to FIG. 8C is a circuit diagram showing a structural example of a charge pump circuit.

[0031] Fig.9A is a circuit diagram showing a structural example of a negative voltage holding circuit, Fig. 9B is the truth table of the driving circuit.

[0032] Fig.10 is a timing chart showing an operation example of the negative voltage supply device.

[0033] Fig.11 is a block diagram showing a structural example of a negative voltage supply device.

[0034] Fig.12 is a circuit diagram showing a structural example of a negative voltage holding circuit.

[0035] Fig.13A and Fig. 13B is a circuit diagram showing a structural example of a negative voltage holding circuit.

[0036] Fig.14A is a block diagram showing a structural example of a storage device, Fig. 14B is a circuit diagram showing a structural example of a memory cell.

[0037] FIG. 15A to FIG. 15F is a circuit diagram showing a structural example of a memory cell.

[0038] Fig.16A is a circuit diagram showing a structural example of a memory cell, Fig. 16B is a timing chart showing an example of the operation of the memory cell.

[0039] Fig.17A is a circuit diagram showing a structural example of a memory cell, Fig. 17B is a timing chart showing an example of the operation of the memory cell.

[0040] Fig.18 is a block diagram showing a structural example of a microcontroller unit.

[0041] Fig.19 is a circuit diagram showing a structural example of a flip-flop.

[0042] Fig. 20 is a block diagram showing a structural example of FPGA.

[0043] Fig.21A is a circuit diagram showing a structural example of a wiring switch, Fig.21B is a circuit diagram showing a structural example of a configuration memory.

[0044] Fig.22A is a block diagram showing a structural example of an imaging device, Fig. 22B is a circuit diagram showing a structural example of a pixel.

[0045] Fig.23A and Fig. 23B It is a three-dimensional schematic diagram of an electronic component.

[0046] FIG. 24A to FIG. 24D is a diagram showing a structural example of an electronic device.

[0047] Fig.25 is a cross-sectional view showing an example of a laminated structure of a circuit portion of an electronic component.

[0048] Fig.26A and Fig.26B is a cross-sectional view showing a structural example of an OS transistor. DETAILED DESCRIPTION

[0049] The following describes an embodiment of the present invention. Note that an embodiment of the present invention is not limited to the following description. A person skilled in the art can easily understand that the present invention can be transformed into various forms without departing from its purpose and scope. Therefore, an embodiment of the present invention should not be interpreted as being limited to the content of the embodiment shown below.

[0050] The multiple embodiments shown below can be appropriately combined. When multiple structural examples (including manufacturing method examples, working method examples, etc.) are shown in one embodiment, the multiple structural examples can be appropriately combined, and can also be appropriately combined with one or more structural examples described in other embodiments.

[0051] In this specification and the like, ordinal numbers such as “first”, “second”, and “third” may be used to avoid confusion among components; however, the ordinal numbers do not limit the number of the components or their order.

[0052] The same elements, elements having the same function, elements formed using the same material, elements formed at the same time, and the like in the drawings are sometimes denoted by the same reference numerals, and duplicate descriptions are sometimes omitted.

[0053] When it is necessary to distinguish a plurality of components represented by the same symbol, “_1”, “_2”, “[n]”, “[m, n]”, etc. may be appended to the symbol.

[0054] In this specification, for example, the power supply voltage VDD may be simply referred to as “voltage VDD” or “VDD.” The same applies to other components (eg, signals, voltages, circuits, elements, electrodes, and wirings).

[0055] In the drawings, the size, thickness of a layer, and area are sometimes exaggerated for the sake of clarity. Therefore, the size, thickness of a layer, or area is not necessarily limited to the dimensions shown in the drawings. The drawings are schematic diagrams showing ideal examples, so the embodiments of the present invention are not limited to the shapes or values ​​shown in the drawings. For example, the signal, voltage, or current unevenness caused by noise or timing deviation may be included.

[0056] In this specification, for the sake of convenience, words and phrases such as "upper", "above", "lower", and "below" that indicate configuration are sometimes used to describe the positional relationship of components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, there is no limitation on the words and phrases used in this specification, and appropriate descriptions can be made according to the circumstances.

[0057] In addition, the transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. Depending on the type of transistor or the potential level supplied to each terminal, one of the two input / output terminals is used as a source and the other is used as a drain. Therefore, in this specification, "source" and "drain" can be interchanged. In this specification, the two terminals other than the gate are sometimes referred to as the first terminal and the second terminal.

[0058] A node may be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit structure or a device structure, etc. In addition, a terminal, a wiring, etc. may be referred to as a node.

[0059] In this specification, "film" and "layer" may be interchanged depending on the situation or condition. For example, "conductive layer" may be interchanged with "conductive film". For example, "insulating film" may be interchanged with "insulating layer".

[0060] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, and means a circuit including a semiconductor element (e.g., a transistor, a diode) and a device including the circuit. A semiconductor device also means all devices that can work by utilizing semiconductor characteristics. For example, an integrated circuit and a chip including an integrated circuit are examples of semiconductor devices. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device are sometimes semiconductor devices themselves, or sometimes include a semiconductor device.

[0061] [Implementation Method 1]

[0062] In this embodiment, a comparison circuit to which a negative voltage to be compared can be directly input and a semiconductor device including the comparison circuit are described.

[0063] Comparison Circuit

[0064] Here, a configuration example of a comparison circuit using a differential amplifier circuit is described.

[0065] Figure 1A An example of a comparison circuit is shown. Figure 1A The comparison circuit 10 shown includes terminals INN, INP, and OCM. The terminals INN, INP, and OCM are an inverting input terminal, a non-inverting input terminal, and an output terminal, respectively.

[0066] Voltages Vdda and Vssa are input to the comparison circuit 10. Voltage Vdda is a high-level power supply voltage. Voltage Vssa is a low-level power supply voltage, for example, 0 V (GND: ground voltage).

[0067] The comparison circuit 10 has a function of comparing the negative voltage Vnin with the negative reference voltage Vnref and outputting a voltage Vcmp corresponding to the comparison result from the terminal OCM. The negative voltage Vnin is input to the terminal INP. The positive reference voltage Vpref is input to the terminal INN instead of the negative reference voltage Vnref. The positive reference voltage Vpref is equivalent to the negative reference voltage Vnref converted into a positive voltage. The value of the positive reference voltage Vpref is set in such a way that the comparison circuit 10 can perform the above-mentioned comparison.

[0068] Figure 1B 2 shows a circuit configuration example of the comparison circuit 10. The comparison circuit 10 is configured by a differential circuit, and includes a differential pair 14, a current source 17, and a load circuit 18.

[0069] The differential pair 14 includes transistors MO11 and MO12. Both transistors MO11 and MO12 are OS transistors including back gates. The back gate of transistor MO11 is electrically connected to terminal INP, and voltage Vdda is input to the gate. The gate of transistor MO12 is electrically connected to terminal INN, and voltage Vssa is input to the back gate.

[0070] Here, the connection node between the transistor MO11 and the load circuit 18 is called a node X11, the connection node between the transistor MO12 and the load circuit 18 is called a node X12, and the connection node between the transistor MO11 and the transistor MO12 is called a node X13. The current source 17 supplies a current Iss to the node X13. The load circuit 18 supplies loads Rd1 and Rd2 to the nodes X11 and X12, respectively.

[0071] Note that, unless otherwise specified, in the drawings, an n-channel transistor including a back gate is an OS transistor, and a p-channel transistor and an n-channel transistor without a back gate are Si transistors.

[0072] The voltages of nodes X12 and X11 depend on the difference between the drain current (Imo1) of transistor MO11 and the drain current (Imo2) of transistor MO12. In the example where terminal OCM is electrically connected to node X12 Figure 1B when Imo1 > Imo2, the voltage Vcmp is at a high level ("H"), and when Imo1 < Imo2, the voltage Vcmp is at a low level ("L").

[0073] (Example of setting the positive reference voltage Vpref)

[0074] The difference between the current Imo1 and the current Imo2 flowing through the differential pair 14 can be converted into the voltage difference between terminals INP and INN. Therefore, the positive reference voltage Vpref can be set according to this voltage difference. Specifically, when the voltages of terminal INP, the gate voltage of transistor MO11, and the back-gate voltage of transistor MO12 are Vnref, Vdda, and Vssa respectively, estimate the voltage difference between terminals INP and INN when the difference between Imo1 and Imo2 is 0 amperes. The value of the positive reference voltage Vpref can be set according to the estimated voltage difference.

[0075] By setting the positive reference voltage Vpref in this way, when Vnin > Vnref, terminal OCM outputs a voltage Vcmp of "H", and when Vnin < Vnref, terminal OCM outputs a voltage Vcmp of "L".

[0076] Refer to Figure 1C to explain the operating principle of the comparison circuit 10. Figure 1C Schematically shows the drain current-gate voltage (Id-Vg) characteristics of transistor MO11. Curve 9A is the Id-Vg curve when Vnin > Vnref. Curve 9B is the Id-Vg curve when Vnin < Vnref.

[0077] When Vnin > Vnref, Imo1 > Imo2, so the voltage Vcmp is "H".

[0078] The reduction of the back-gate voltage causes the Vt of transistor MO11 to drift towards the positive side. That is, the reduction of the negative voltage Vnin makes the current Imo1 smaller. When Vnin < Vnref, Imo1 < Imo2, so the voltage Vcmp is "L".

[0079] Next, a modified example of the differential pair will be described. In the Figure 1A example, the voltages Vdda and Vssa are used as the bias voltages of the differential pair 14, but the bias voltages are not limited to them. By using the voltages Vdda and Vssa as the bias voltages of the differential pair 14, the types of voltages used in the comparison circuit 10 can be reduced.

[0080] Alternatively, the back gate of transistor MO12 may be electrically connected to the terminal INP, and a bias voltage such as the input voltage Vssa may be input to the gate.

[0081] Figure 2 The comparison circuit 11 shown includes a differential pair 15 instead of the differential pair 14. The differential pair 15 includes transistors MO13 and MO14. The terminal INN is electrically connected to the gate of the transistor MO13. The terminal INP is electrically connected to the gate of the transistor MO14. The back gate of the transistor MO13 is input with a bias voltage (here, Vdda). The back gate of the transistor MO14 is input with a bias voltage (here, Vssa).

[0082] The back gate of the transistor MO14 may also be electrically connected to the terminal INP, and a bias voltage (eg, Vssa) may be input to the gate.

[0083] The comparison circuit 10 does not have a complicated circuit structure, and can directly input a negative voltage to be compared. By replacing the negative reference voltage with a positive reference voltage, the comparison circuit 10 is only input with 0V or a positive voltage in addition to the negative voltage (Vnin) to be compared, so that the operation of the comparison circuit 10 can be stabilized. The comparison circuit 11 is the same.

[0084] <Comparison Circuits 20 to 25>

[0085] Next, a specific example of the circuit configuration of the comparison circuit will be described.

[0086] Figure 3A The illustrated comparison circuit 20 includes terminals INN, INP, OCM, a differential input circuit 30 , and an output circuit 40 .

[0087] The differential input circuit 30 is a first-stage differential amplifier circuit and includes a differential pair 34 and transistors MN1 , MP1 , and MP2 .

[0088] The differential pair 34 has the same circuit structure as the differential pair 14 and includes transistors MO1 and MO2. The connection node between the transistors MO1 and MP1 is referred to as a node X1. The connection node between the transistors MO2 and MP2 is referred to as a node X2.

[0089] The terminal INP is electrically connected to the back gate of the transistor MO1. The terminal INN is electrically connected to the gate of the transistor MO2. The voltage Vdda is input to the gate of the transistor MO1. The voltage Vssa is input to the back gate of the transistor MO2.

[0090] The transistor MN1 is used as a current source. The gate of the transistor MN1 is input with the voltage Vb1. The voltage Vb1 is a positive voltage.

[0091] The current mirror circuit is composed of transistors MP1 and MP2. The current mirror circuit is used as a load circuit. The load circuit can also be composed of transistors MP1 and MP2 connected in diode configuration. Alternatively, two resistors can be provided instead of transistors MP1 and MP2.

[0092] The output circuit 40 is electrically connected to node X2. The output circuit 40 is composed of a two-stage CMOS inverter circuit. The CMOS inverter circuit is composed of Si transistors.

[0093] Figure 3B The illustrated comparison circuit 21 is a modified example of the comparison circuit 20. The output circuit 41 is composed of a one-stage CMOS inverter circuit. The input node of the CMOS inverter circuit is electrically connected to node X1.

[0094] Figure 4A The illustrated comparison circuit 22 is a modified example of the comparison circuit 20. The output circuit 42 of the comparison circuit 22 is composed of a two-stage source follower circuit. Figure 4B The illustrated comparison circuit 23 is a modified example of the comparison circuit 22. The output circuit 43 of the comparison circuit 23 is composed of a one-stage source follower circuit. The input node of the source follower circuit is electrically connected to node X1.

[0095] Figure 4C The illustrated comparison circuit 24 is a modified example of the comparison circuit 21 and includes a differential input circuit 31. The differential input circuit 31 is a modified example of the differential input circuit 30 and includes a transistor MO3 instead of the transistor MN1. The gate of the transistor MO3 is input with the voltage Vb1, and the back gate is electrically connected to the gate. Note that the back gate of the transistor MO3 can also be input with a bias voltage (e.g., the voltage Vssa), and the back gate can also be electrically connected to the drain.

[0096] The above comparison circuits 20 to 24 output a voltage Vcmp of "H" when Vnin > Vnref, and output a voltage Vcmp of "L" when Vnin < Vnref. The relationship between the magnitude relationship between Vnin and Vnref and the level of the voltage Vcmp is appropriately changed according to the circuit structure of the output circuit, etc.

[0097] In the comparison circuit 20, the gate of the transistor MO1 can also be electrically connected to the terminal INP, and the back gate of the transistor MO1 can be input with a bias voltage (e.g., Vdda). The back gate of the transistor MO2 can also be electrically connected to the terminal INN, and the gate of the transistor MO2 can be input with a bias voltage (e.g., Vssa). The same applies to the comparison circuits 21 to 24.

[0098] "Dynamic Comparison Circuit"

[0099] Refer to Figure 5 Describe a structural example of a dynamic comparison circuit. Figure 5 The comparison circuit 25 shown includes a differential input circuit 32, an output circuit 45, terminals INN, INP, OCM, and a terminal OCMB. The comparison circuit 25 receives inputs of voltages Vdda, Vssa, and a clock signal CLK (hereinafter referred to as signal CLK).

[0100] The comparison circuit 25 compares the negative voltage Vnin with the negative reference voltage Vnref and outputs the voltage Vcmp and the voltage VcmpB corresponding to the comparison result from the terminals OCM and OCMB. The negative voltage Vnin and the positive reference voltage Vpref are input to the terminals INN and INP, respectively. The setting method of the positive reference voltage Vpref is the same as that of the comparison circuit 10 described above.

[0101] Currents Imo5 and Imo6 in the accompanying drawings represent drain currents of transistors MO5 and MO6, respectively.

[0102] In the comparison circuit 25 , a negative voltage (Vnin) to be compared can be input to the terminal INN, and a voltage of 0 V or less can be used.

[0103] The differential input circuit 32 includes transistors MO5, MO6, transistors MN5, MN6, MN7, MP5, MP6, MP7, MP8.

[0104] The differential pair of the differential input circuit 32 has the same circuit structure as the differential pair 34, and includes transistors MO5 and MO6. The transistor MN7 is used as a current source. The signal CLK is input to the gate of the transistor MN7.

[0105] Here, the connection node of transistors MN5 and MP5 is called node X5. The connection node of transistors MN6 and MP6 is called node X6. The latch circuit is composed of transistors MN5, MP5, MN6, and MP6. The latch circuit sets the voltage levels of nodes X5 and X6 according to the magnitude relationship of currents Imo5 and Imo6.

[0106] The transistors MP7 and MP8 are reset transistors. The on / off of the transistors MP7 and MP8 is controlled by the signal CLK. When the transistors MP7 and MP8 are on, the voltages of the nodes X5 and X6 are fixed to Vdda ("H").

[0107] The output circuit 45 includes inverter circuits 38 and 39. Input terminals of the inverter circuits 38 and 39 are electrically connected to nodes X5 and X6, respectively. Output terminals of the inverter circuits 38 and 39 are electrically connected to terminals OCM and OCMB, respectively.

[0108] During the period when the signal CLK is "L", the comparison circuit 25 performs precharging. Since the transistors MP7 and MP8 are in the on state, the nodes X5 and X6 are fixed at "H", and the terminals OCM and OCMB are fixed at "L".

[0109] During the period when the signal CLK is "H", the comparison circuit 25 performs evaluation. When a difference occurs between the currents Imo5 and Imo6, a difference in driving ability occurs between the two inverter circuits included in the latch circuit, and thus a voltage difference occurs between the nodes X5 and X6.

[0110] When Vnin > Vnref, the current Imo5 > the current Imo6. Therefore, the voltage of the node X5 is lower than the voltage of the node X6, and the terminals OCM and OCMB become "H" and "L", respectively. On the other hand, when Vnin < Vnref, the current Imo5 < the current Imo6. Therefore, the voltage of the node X5 is higher than the voltage of the node X6, and the terminals OCM and OCMB become "L" and "H", respectively.

[0111] Since Figure 3A the differential pair in the comparison circuit 20 shown is formed by two OS transistors including back gates, the voltage Vssa can be a ground voltage. Therefore, it is not necessary to input a negative voltage to the source of the transistor MN1.

[0112] When a negative voltage is input to the source of an n-channel Si transistor, a parasitic diode (pn junction diode) between the p-type well and the source region is applied with a forward bias voltage. Therefore, a large reverse current flows from the substrate to the source region. To prevent the large reverse current, a triple-well structure in which an n-channel transistor is surrounded by an n-type well is usually employed (for example, refer to FIGS. 3b of Patent Document 3 and Figure 6 ). However, the circuit area increases due to the n-channel transistor of the triple-well structure.

[0113] The comparison circuit 20 can be formed without using an n-channel Si transistor of the triple-well structure, so the circuit area can be reduced. The same applies to the comparison circuits 21 to 25.

[0114] As described above, by adopting a differential pair formed by two n-channel transistors including back gates, the comparison circuit of the present embodiment can be supplied with a negative voltage to be compared, can use a reference voltage obtained by converting a negative reference voltage into a positive voltage, and can set the low-level side power supply voltage to 0V (ground voltage) without having a complex circuit structure. Therefore, the comparison circuit of the present embodiment can achieve high-precision comparison between a negative voltage and a negative reference voltage and stable operation.

[0115] [Embodiment 2]

[0116] In this embodiment, a semiconductor device including the comparison circuit described in Embodiment 1 is described. As an example, a device for supplying a negative voltage to the semiconductor device is described.

[0117] 《Negative voltage supply device 100》

[0118] Figure 6 is a block diagram showing a structural example of a negative voltage supply device. Figure 6 The negative voltage supply device 100 shown generates a negative voltage inside it and outputs the generated negative voltage to a plurality of power supply terminals. The negative voltage supply device 100 includes a control circuit 111, a charge pump circuit 112, a bias voltage generating circuit 114, an output voltage regulator 120, and a plurality of terminals OB. The terminal OB is an output terminal for negative voltage. In this example, the number of the terminals OB is 4, but is not limited thereto.

[0119] In order to distinguish the four terminals OB, reference numerals [1] to [4] are used. When it is necessary to specify any one of the multiple terminals OB, for example, the terminal OB is recorded as terminal OB [1]. "Terminal OB" refers to any terminal OB. The same applies to other components.

[0120] The negative voltage supply device 100 is input with voltages Vdda, Vddd, GND, a positive reference voltage Vpref, a clock signal CK1, and a signal WAKE. In addition, the voltage GND is 0V (ground voltage) and is used as a low-level side power supply voltage of the negative voltage supply device 100. The voltage Vddd is a high-level side power supply voltage and is smaller than the voltage Vdda. The voltage Vddd is used in the control circuit 111.

[0121] <Control Circuit 111>

[0122] The signal WAKE is used as an enable signal of the negative voltage supply device 100. The control circuit 111 controls the charge pump circuit 112 and the output voltage regulator 120 according to the signal WAKE. Here, the control circuit 111 is used as a gated clock buffer. The control circuit 111 generates a gated clock signal GCK1 (hereinafter referred to as the clock signal GCK1) from the clock signal CK1 according to the signal WAKE. The low level voltage and the high level voltage of the clock signal CK1 are GND and Vdda, respectively.

[0123] The clock signal GCK1 is input to the charge pump circuit 112 and the output voltage regulator 120 .

[0124] <Charge Pump Circuit 112>

[0125] The charge pump circuit 112 is used as a negative voltage generating circuit. Figure 7The circuit structure example of the charge pump circuit 112 is shown, which is a four-stage buck type charge pump circuit. The charge pump circuit 112 includes terminals IN_cp, OUT_cp, 2 inverter circuits, 4 OS transistors and 4 capacitors. When the clock signal GCK1 is in an active state, the charge pump circuit 112 generates a negative voltage Vcp from the voltage GND input to the terminal IN_cp, and outputs the negative voltage Vcp from the terminal OUT_cp.

[0126] exist Figure 7 In the example of FIG. 1 , four transistors are provided in the charge transfer path between the terminal IN_cp and the terminal OUT_cp, but the number of transistors is not limited thereto. In addition, the transistor provided in the charge transfer path is not limited to the OS transistor. FIG. 8A to FIG. 8C Another example of a step-down charge pump circuit that can be used as the charge pump circuit 112 is shown.

[0127] Fig. 8A The charge pump circuit 113A includes two inverter circuits, four n-channel Si transistors, and four capacitors. Figure 8B The charge pump circuit 113B includes three n-channel Si transistors and one OS transistor. Figure 8C The charge pump circuit 113C includes 2 inverter circuits, 4 p-channel Si transistors and 4 capacitors.

[0128] <Bias Voltage Generating Circuit 114>

[0129] The bias voltage generating circuit 114 generates a voltage Vb1. The voltage Vb1 is input to the output voltage regulator 120. Alternatively, the voltage Vb1 may be input from the outside without providing the bias voltage generating circuit 114.

[0130] <Output Voltage Regulator 120>

[0131] The output voltage regulator 120 is provided to stably output a negative voltage from each terminal OB. The output voltage regulator 120 includes four negative voltage holding circuits 122. The negative voltage holding circuit 122 includes a charge pump circuit 123, a drive circuit 127, and a monitoring circuit 128. The negative voltage holding circuit 122[j] (j is an integer from 1 to 4) controls the output voltage of the terminal OB[j]. Fig.9A A circuit configuration example of the negative voltage holding circuit 122 is shown.

[0132] <Negative Voltage Holding Circuit 122>

[0133] The charge pump circuit 123 includes transistors MO21 and MO22 and capacitors C21 and C22. The charge pump circuit 123 steps down the voltage Vcp to generate a voltage Vob. The voltage Vob is held by the capacitor C22. The voltage Vob is output from the terminal OB.

[0134] The capacitance of capacitor C22 is preferably greater than that of capacitor C21. For example, the capacitance of capacitor C22 is 2 to 10 times that of capacitor C21. Depending on the capacitance required for capacitor C21, capacitor C21 can be formed by parasitic capacitance of transistor MO21 or parasitic capacitance between transistor MO21 and wiring.

[0135] The band gap of metal oxide semiconductors is above 2.5 eV, so the off-state current of OS transistors is extremely small. For example, the off-state current per channel width of 1 μm at room temperature (25°C) with a voltage of 3.5 V between the source and the drain can be less than 1×10 -20 A. Less than 1×10 -22 A. or less than 1×10 -24 A. That is, the on / off ratio of the drain current can be greater than or equal to 20 digits and less than or equal to 150 digits.

[0136] Metal oxide semiconductors are semiconductors with a large energy gap, where electrons are not easily excited and the effective mass of holes is large. Therefore, avalanche breakdown is less likely to occur in OS transistors than in Si transistors. Since hot carrier degradation caused by avalanche breakdown is suppressed, the insulation withstand voltage between the source and drain of OS transistors is high.

[0137] Examples of metal oxides that can be used in the channel formation region include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In addition, the oxide containing indium and zinc may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0138] The gate of transistor MO22 is applied with a negative voltage, so the cut-off current of transistor MO22 can be effectively reduced by electrically connecting the back gate of transistor MO22 to the gate. This is because the threshold voltage of transistor MO22 drifts toward the positive side by electrically connecting the back gate of transistor MO22 to the gate. Here, the cut-off current refers to the drain current when the gate-source voltage of the transistor is 0V.

[0139] Therefore, the structure in which the transistors MO21 and MO22 are OS transistors including back gates helps to stably supply a negative voltage for a long time.

[0140] Since the OS transistor can be stacked on the Si transistor, the transistors MO21 and MO22 of the OS transistor contribute to the miniaturization of the negative voltage supply device 100 .

[0141] The monitoring circuit 128 monitors the voltage Vob of the terminal OB. The monitoring circuit 128 is formed of a comparison circuit using a differential amplifier circuit. Fig.9A The comparison circuit shown is the comparison circuit 20 (refer to Figure 3A ) is a variation of the above. Here, the output circuit includes a CMOS inverter circuit.

[0142] The terminal INP is electrically connected to the terminal OB. The positive reference voltage Vpref is input to the terminal INN. The terminal OCM is electrically connected to the input terminal of the driving circuit 127. The signal MON is an output of the terminal OCM.

[0143] The output voltage of the negative voltage supply device 100 is set to the negative voltage VBG. The monitoring circuit 128 compares the voltage Vob with the negative voltage VBG as a reference. The value of the positive reference voltage Vpref is set so that the monitoring circuit 128 can perform the comparison.

[0144] Here, the monitoring circuit 128 monitors the drop of the voltage Vob. When the voltage Vob is higher than the negative voltage VBG, the monitoring circuit 128 outputs the signal MON of "L". When the voltage Vob is lower than the negative voltage VBG, the monitoring circuit 128 outputs the signal MON of "H".

[0145] It is also possible to use a plurality of positive reference voltages according to the deviation of characteristics (e.g., bias voltage) among the plurality of monitoring circuits 128. For example, two positive reference voltages Vpref1 and Vpref2 of different values ​​are input to the negative voltage supply device 100. The monitoring circuits 128[1] and 128[2] are input with the positive reference voltage Vpref1. The monitoring circuits 128[3] and 128[4] are input with the positive reference voltage Vpref2.

[0146] The driving circuit 127 performs a logic operation on the signal MON and the clock signal GCK1 to generate a clock signal GCK2 for driving the charge pump circuit 123. The driving circuit 127 has the following circuit structure: when the signal MON is "L", the clock signal GCK2 is active; during other periods, the clock signal GCK2 is inactive. Fig. 9B An example of a truth table of the driving circuit 127 is shown.

[0147] 《Working Examples》

[0148] Reference Fig.10 An operation example of the negative voltage supply device 100 will be described. Fig.101 is a timing chart showing an example of the operation of the negative voltage supply device 100. t0 etc. indicate time. Here, at time t0, the output voltage Vcp of the charge pump circuit 112 and the voltages Vob[1] to Vob[4] of the terminals OB[1] to OB[4] are 0 V (GND).

[0149] Fig.10 The period Tc1 in φc1 is one cycle period of the operation of the negative voltage supply device 100. The signal WAKE is used as a chip enable signal of the negative voltage supply device 100. While the signal WAKE is "H", the negative voltage supply device 100 is in an active state.

[0150] While the signal WAKE is "H", the clock signal GCK1 outputted from the control circuit 111 is active, so the charge pump circuit 112 performs a voltage step-down operation. Here, the output voltage Vcp of the charge pump circuit 112 is saturated at the negative voltage VBG between time t0 and time t1.

[0151] At time t0, since voltage Vob[1] is GND, monitoring circuit 128[1] outputs signal MON[1] at "L". Signals MON[2] to MON[4] are also "L". Therefore, drive circuits 127[1] to 127[4] respectively output active clock signals GCK2[1] to GCK2[4].

[0152] Since the charge pump circuit 123[1] performs a step-down operation, the voltage Vob[1] decreases. The charge pump circuits 123[2] to 123[4] also perform a step-down operation.

[0153] The deviation of the electrical characteristics (e.g., threshold voltage) of transistors MO21 and MO22 between the charge pump circuits 123[1] to 123[4] leads to the difference of the current driving capability between the charge pump circuits 123[1] to 123[4]. Therefore, the timing at which the terminals OB[1] to OB[4] reach the negative voltage VBG is different. In the present embodiment, the monitoring circuits 128[1] to 128[4] independently monitor the voltages of the terminals OB[1] to OB[4], thereby reducing the deviation of the resulting voltages of the terminals OB[1] to OB[4] and making these voltages substantially the same as the negative voltage VBG.

[0154] For example, the negative voltage holding circuit 122[1] is described. When the voltage Vob[1] is detected to have reached the negative voltage VBG, the monitoring circuit 128[1] outputs the "H" signal MON[1] to the driving circuit 127[1]. In response to the input of the "H" signal MON[1], the driving circuit 127[1] fixes the clock signal GCK2 to "H". As a result, the charge pump circuit 123[1] stops the step-down operation, and the voltage Vob[1] is set to approximately the negative voltage VBG.

[0155] Since transistor MO22[1] is an OS transistor with extremely small off-state current, capacitor C22[1] can maintain negative voltage VBG for a long time even if clock signal GCK2 is in an inactive state.

[0156] Negative voltage holding circuits 122 [ 2 ] to 122 [ 4 ] also operate in the same manner, and voltages Vob [ 2 ] to Vob [ 4 ] are set to substantially negative voltage VBG.

[0157] Between time t1 and time t2, since the signal WAKE is "L", the negative voltage supply device 100 is in an inactive state. Here, the standby power of the negative voltage supply device 100 is reduced by performing clock gating to fix the clock signal CK1 to "L".

[0158] Since the negative voltage holding circuit 122 has excellent holding characteristics, the period during which the signal WAKE is "L" can be extended. Therefore, during this period, power gating can be performed to stop supplying the power supply voltage (Vddd, Vdda) to the negative voltage supply device 100. By performing power gating, the power consumption of the negative voltage supply device 100 can be further reduced.

[0159] Fig.10 An example of power gating during the period when the signal WAKE is "L" is shown. At time t2, the supply of voltages Vddd and Vdda begins, the signal WAKE changes to "H", and the clock signal CK1 becomes active. The operation of the negative voltage supply device 100 from time t2 to time t3 is the same as the operation from time t0 to time t1. Fig.10 In the embodiment, the voltages Vob[1] to Vob[4] from time t1 to time t3 do not exceed the negative voltage VBG. When the monitoring circuits 128[1] to 128[4] become active, the terminals OCM[1] to OCM[4] change from "L" to "H". Therefore, the charge pump circuits 123[1] to 123[4] are in the standby state.

[0160] Since the negative voltage holding circuit 122 has the function of controlling the voltage drop of the terminal OB and the function of holding the voltage of the terminal OB, a set negative voltage can be outputted stably from the terminal OB for a long period of time.

[0161] 《Negative Voltage Supply Device 101》

[0162] Reference Fig.11 , Fig.12 , Fig.13A and Fig. 13B Another structural example of the negative voltage supply device is described. In this structural example, a dynamic comparison circuit is used for the negative voltage monitoring circuit.

[0163] Fig.11 The negative voltage supply device 101 shown includes a control circuit 141 , a charge pump circuit 142 , a frequency dividing circuit 143 , an output voltage regulator 150 and four terminals OB. The output voltage regulator 150 includes four negative voltage holding circuits 152 .

[0164] The negative voltage supply device 101 is input with voltages Vdda, Vddd, GND, a positive reference voltage Vpref, a clock signal CK1 and a signal WAKE.

[0165] The control circuit 141 has the same function as the control circuit 111. The control circuit 141 generates a clock signal GCK1 based on the signal WAKE.

[0166] The charge pump circuit 142 has the same circuit structure as the charge pump circuit 112 (see Figure 7 The charge pump circuit 142 performs a voltage reduction operation according to the clock signal GCK1 and outputs a voltage Vcp.

[0167] The frequency dividing circuit 143 divides the frequency of the clock signal GCK1 to generate a clock signal GCK3 . The clock signal GCK3 is input to the four negative voltage holding circuits 152 .

[0168] Fig.12 15 shows a circuit configuration example of the negative voltage holding circuit 152. The negative voltage holding circuit 152 includes a charge pump circuit 153, a drive circuit 154, and a monitor circuit 155.

[0169] The charge pump circuit 153 has the same circuit structure as the charge pump circuit 123, and includes transistors MO25, MO26, and capacitors C25, C26.

[0170] The driving circuit 154 has the same function as the driving circuit 127 (see Fig. 9B ). The driving circuit 154 performs a logic operation on the signal MON and the clock signal GCK3, and generates a clock signal GCK4 for driving the charge pump circuit 153. When the signal MON is "L", the clock signal GCK4 is in an active state. When the signal MON is not "L", the clock signal GCK4 is in an inactive state.

[0171] The monitoring circuit 155 includes a comparison circuit 25 (see Figure 5 The clock signal GCK3 is input to the monitoring circuit 155. The terminal INP is electrically connected to the terminal OB, and the positive reference voltage Vpref is input to the terminal INN. The terminal OCMB is electrically connected to the input terminal of the driving circuit 154.

[0172] Here, the monitoring circuit 155 monitors the drop of the voltage Vob. When the voltage Vob is greater than the negative voltage VBG, the monitoring circuit 155 outputs the signal MON of "L". When the voltage Vob is less than the negative voltage VBG, the monitoring circuit 155 outputs the signal MON of "H".

[0173] The negative voltage supply device 101 performs the same operation as the negative voltage supply device 100 (see Fig.10 Compared with the negative voltage supply device 100 , the negative voltage supply device 101 can reduce power consumption (ie, dynamic power consumption) during the period when the signal WAKE is “H”.

[0174] During the period when the signal WAKE is "H", regardless of the clock signal GCK2, current always flows through the monitoring circuit 128 of the negative voltage supply device 100. In contrast, during the period when the clock signal GCK3 is "L", the output OCMB of the monitoring circuit 155 is fixed to "L". Therefore, the current consumption of the monitoring circuit 155 can be lower than the current consumption of the monitoring circuit 128.

[0175] By providing a monitoring circuit 155 for each terminal OB, a negative voltage can be stably output from each terminal OB. However, as the number of terminals OB increases, the influence on the current consumption of the monitoring circuit 155 also increases. Therefore, reducing the current consumption of the monitoring circuit 155 is effective in reducing the overall dynamic power consumption of the negative voltage supply device 101.

[0176] In order to reduce dynamic power consumption, the clock signal is set to a low speed. If the clock signal GCK1 is set to a low speed, it takes a long time until the voltage Vcp reaches the negative voltage VBG. In other words, the time when the signal WAKE is "H" becomes longer. Therefore, by only setting the clock signal GCK3 to a low speed, the dynamic power consumption of the negative voltage supply device 101 can be efficiently reduced.

[0177] <Other Configuration Examples of Monitoring Circuit>

[0178] Since the monitoring circuit 155 is composed of a dynamic comparison circuit, when the same amount of current flows through the two OS transistors of the differential pair, the signal MON at the terminal OCM may become unstable. Fig.13A and Fig. 13B The following describes measures to stabilize the signal MON.

[0179] Fig.13A An example is shown in which the positive reference voltage of the dynamic comparison circuit is switched according to the signal MON. Fig. 13B An example is shown in which the power supply to the differential input circuit of the dynamic comparison circuit is controlled according to the signal MON.

[0180] (Monitoring circuit 161)

[0181] Fig.13A The monitoring circuit 161 shown includes a comparison circuit 171 , a latch circuit 173 , and a selection circuit 175 .

[0182] The comparison circuit 171 is constituted by the comparison circuit 25. The differential pair of the comparison circuit 171 is constituted by transistors MO7 and MO8. The currents Imo7 and Imo8 are drain currents of the transistors MO7 and MO8, respectively.

[0183] In synchronization with the rising of the clock signal GCK3, the data of the latch circuit 173 is updated by the output of the comparison circuit 171. The output signal of the latch circuit 173 is the signal MON. For example, the latch circuit 173 may include a delay flip-flop (DFF) circuit.

[0184] The selection circuit 175 selects a voltage to be input to the terminal INN of the comparison circuit 171 from the positive reference voltage Vpref and the voltage GND. The signal MON and the signal WAKE are input to the selection circuit 175. The signal WAKE is used as a reset signal (RESET) of the selection circuit 175. In addition, a signal other than the signal WAKE may be used as a reset signal.

[0185] The following describes an operation example of the monitoring circuit 161. When the signal WAKE changes from "L" to "H", the selection circuit 175 is reset and the positive reference voltage Vpref is supplied to the terminal INN. When the clock signal GCK3 is active, the comparison circuit 171 compares the voltage Vob of the terminal OB with the negative voltage VBG. When the voltage Vob is higher than the negative voltage VBG, the signal MON is "L". When the signal MON is "L", the selection circuit 175 inputs the positive reference voltage Vpref to the terminal INN.

[0186] When the voltage Vob becomes lower than the negative voltage VBG and the clock signal GCK3 is "H", the terminal OCMB outputs an "H" signal. At this time, the current Imo7 can become equal to the current Imo8, so that the output of the terminal OCMB may oscillate. If the selection circuit 175 detects the rise of the signal MON for a predetermined number of times (1 time or more), the voltage GND is supplied to the terminal INN. Then, the current Imo8 decreases, and a difference is generated between the current Imo7 and the current Imo8, so that the output of the terminal OCMB is stable. When the clock signal GCK3 is "H", the terminal OCMB can stably output the "H" signal.

[0187] In this example, the voltage GND is input to the terminal INN, but there is no restriction on the signal as long as there is a difference between the currents Imo7 and Imo8 when the signal MON is "H". A positive voltage lower than the voltage Vpref may be input to the terminal INN. Using the voltage GND does not increase the number of voltages to be used.

[0188] (Monitoring circuit 162)

[0189] Fig. 13B The monitoring circuit 162 shown includes a comparison circuit 172 and a selection circuit 177. The comparison circuit 172 is constituted by the comparison circuit 25. Similar to the monitoring circuit 161, the monitoring circuit 162 may also be provided with a latch circuit 173.

[0190] The selection circuit 177 controls the supply of the high-level power supply voltage to the differential input circuit 172A of the comparison circuit 172. The signals MON and WAKE are input to the selection circuit 177. The signal WAKE is used as a reset signal for the selection circuit 177. As the reset signal, a signal other than the signal WAKE may be used.

[0191] When the signal WAKE changes from "L" to "H", the selection circuit 177 is reset and the voltage Vdda is supplied to the differential input circuit 172A. When the clock signal GCK3 is in an active state, the comparison circuit 172 compares the voltage Vob of the terminal OB with the negative voltage VBG. If the selection circuit 177 detects the rise of the signal MON a predetermined number of times (one or more times), the voltage GND is supplied to the differential input circuit 172A. As a result, the two inverter circuits of the differential input circuit 172A are in an inactive state, so the output of the comparison circuit 172 does not oscillate.

[0192] The negative voltage supply device of this embodiment is suitable for use in negative voltage power supply circuits of various semiconductor devices. Examples of semiconductor devices that use this negative voltage supply device as a power supply circuit include various semiconductor devices whose substrate bias voltage is a negative voltage (e.g., DRAM, image sensor), semiconductor devices driven by a negative voltage (e.g., storage devices such as flash memory), and semiconductor devices having an OS transistor with a back gate. In Embodiment 3, a structural example of a semiconductor device including this negative voltage supply device is described.

[0193] [Implementation method 3]

[0194] Storage Device

[0195] Here, as a semiconductor device using an OS transistor, a memory device in which a data holding portion includes an OS transistor will be described.

[0196] Fig.14A The memory device 200 shown includes a negative voltage supply device 210 , a control circuit 215 , a memory cell array 220 , and a peripheral circuit 221 . The peripheral circuit 221 includes a row circuit 223 , a column circuit 224 , and an input / output circuit 225 .

[0197] The memory cell array 220 includes a memory cell 230, a read word line RWL, a write word line WWL, a read bit line RBL, a write bit line WBL, a source line SL, and a wiring BGL. In addition, the read word line RWL and the write word line WWL are sometimes referred to as word lines RWL and word lines WWL, respectively. The read bit line RBL and the write bit line WBL are sometimes referred to as bit lines RBL and bit lines WBL.

[0198] The control circuit 215 controls the entire storage device 200 to write data WDA and read data RDA. The control circuit 215 processes external command signals (eg, chip enable signal, write enable signal) and generates control signals for the peripheral circuit 221.

[0199] The negative voltage supply device described in Embodiment 2 is used as the negative voltage supply device 210. The negative voltage supply device 210 includes N terminals OB[1] to OB[N] (N is an integer greater than or equal to 2). The terminals OB[1] to OB[N] output a negative voltage Vbg1. The memory cell array 220 is divided into N blocks. The wiring BGL of each block is electrically connected to the terminal OB.

[0200] The row circuit 223 has a function of selecting a row to be accessed. For example, the row circuit 223 includes a row decoder and a word line driver. The column circuit 224 has a function of precharging the bit lines WBL and RBL, a function of writing data to the bit line WBL, a function of amplifying the data of the bit line RBL, and a function of reading data from the bit line RBL. The input / output circuit 225 has a function of holding the written data and a function of holding the read data.

[0201] The configuration of the peripheral circuit 221 is appropriately changed according to the configuration of the memory cell array 220 , the reading method, the writing method, and the like.

[0202] <Storage Unit 230>

[0203] Fig. 14B 1 shows an example of a circuit structure of a memory cell 230. The memory cell 230 in this example is a 2-transistor type (2T) gain cell. The memory cell 230 includes transistors MW1, MR1 and a capacitor CS1. The transistors MW1 and MR1 are a write transistor and a read transistor, respectively. The back gates of the transistors MW1 and MR1 are electrically connected to the wiring BGL.

[0204] Since the read transistor is an OS transistor, the memory cell 230 does not consume power when retaining data. Therefore, the memory cell 230 is a low-power memory cell capable of retaining data for a long time. The memory device 200 can be used as a non-volatile memory device. The OS transistor and the capacitor can be stacked on the Si transistor. Therefore, the memory cell array 220 can be stacked on the peripheral circuit 221, thereby improving the integration of the memory cell array 220.

[0205] Reference FIG. 15A to FIG. 15F Describe other structural examples of storage units.

[0206] <Storage Units 231 to 235>

[0207] Fig.15A The memory cell 231 shown is a 3T-type gain cell, which includes transistors MW2, MR2, MS2 and capacitor CS2. Transistors MW2, MR2 and MS2 are respectively a write transistor, a read transistor and a select transistor. The back gates of transistors MW2, MR2 and MS2 are electrically connected to wiring BGL. The memory cell 231 is electrically connected to word lines RWL, WWL, bit lines RBL, WBL, capacitor line CDL and power line PL2. For example, capacitor line CDL and power line PL2 are input with voltage GND (low-level side power supply voltage).

[0208] Fig. 15B as well as Fig. 15C Other structural examples of 2T-type gain cells are shown. Fig. 15B In the memory cell 232 shown, an n-channel Si transistor is used as a read transistor. Fig. 15C In the illustrated memory cell 233, a p-channel Si transistor is used as a readout transistor.

[0209] Fig.15D as well as Fig.15E Other structural examples of 3T-type gain cells are shown. Fig.15D In the memory cell 234 shown, an n-channel Si transistor is used as a read transistor and a select transistor. Fig.15E In the memory cell 235 shown, a p-channel Si transistor is used as a read transistor and a select transistor. Fig.15E In the example, the voltage Vddd (high-level side power supply voltage) is input to the power supply line PL2.

[0210] In the above-mentioned gain unit, a bit line serving as both the read bit line RBL and the write bit line WBL may be provided.

[0211] <Storage Unit 236>

[0212] Fig.15FAn example of a 1T1C (capacitor) type memory cell is shown. Fig.15F The memory cell 236 shown is electrically connected to the word line WL, the bit line BL, the capacitor line CDL, and the wiring BGL. The memory cell 236 includes a transistor MW3 and a capacitor CS3. The back gate of the transistor MW3 is electrically connected to the wiring BGL.

[0213] <Storage Unit 237>

[0214] Fig.16A The illustrated memory cell 237 includes a memory cell 240 and a backup circuit 241. The memory cell 240 has the same circuit structure as a standard 6T-type SRAM cell.

[0215] Backup circuit 241 is a circuit for backing up the data of nodes Q and Qb included in storage unit 240, and is composed of two 1T1C type cells. Nodes SN1 and SN2 are holding nodes. The gain unit composed of transistor MW5 and capacitor CS5 backs up the data of node Q. The gain unit composed of transistor MW6 and capacitor CS6 backs up the data of node Qb.

[0216] Since the transistors MW5 and MW6 are OS transistors, the memory cell 240 can be stacked on the backup circuit 241. Therefore, the area cost of the memory cell 237 caused by the additional provision of the backup circuit 241 can be reduced. The area cost can be zero.

[0217] The memory cell 240 is electrically connected to power lines V_VDM, V_VSM, word lines WL, and bit line pairs (BL, BLB). Power lines V_VDM and V_VSM are power lines for Vddd and GND, respectively. The backup circuit 241 is electrically connected to wirings OGL, BGL, and power line PL3. Power line PL3 is input with voltage GND.

[0218] The memory cell 237 in the normal state operates as an SRAM cell. Fig. 16B The following describes an operation example of the memory cell 237. If the memory cell 237 is not accessed for a certain period of time, the supply of voltages Vddd and GND to the power lines V_VDM and V_VSM is stopped. Before the supply of voltage Vddd is stopped, data of nodes Q and Qb are written to the backup circuit 241. Fig. 16B In the figure, t1, t2, etc. represent time.

[0219] (Regular work)

[0220] Before time t1, the memory cell 237 is in a normal working state (writing state or reading state). The memory cell 237 works in the same manner as a single-port SRAM. At time t1, nodes Q, Qb, SN1, and SN2 are "H", "L", "L", and "H", respectively.

[0221] (Backup)

[0222] At t1, the wiring OGL changes to "H", thereby starting the backup operation, and transistors MW5 and MW6 are turned on. The voltage of the node SN1 rises from GND to Vddd. The voltage of the node SN2 decreases from Vddd to GND. At t2, the wiring OGL changes to "L", and the backup operation ends. The data of the node Q at t1 and the data of the node Qb at t1 are written to the nodes SN1 and SN2, respectively.

[0223] (Power Gating)

[0224] At t2, power gating starts. The voltage of the power line V_VDM changes from Vddd to GND. The voltage difference between the power line V_VDM and the power line V_VSM decreases, and thus the memory cell 240 becomes inactive. Although the data in the memory cell 240 disappears, the backup circuit 241 continues to retain the data. During the power gating period, the bit lines BL and BLB are in a floating state.

[0225] (recover)

[0226] The restore operation is an operation of restoring the data of the memory cell 240 using the data held by the backup circuit 241. In the restore operation, the memory cell 240 is used as a sense amplifier for detecting the data of the nodes Q and Qb.

[0227] First, the nodes Q and Qb are reset. At t3, the voltage of the bit line pair (BL and BLB) is precharged to the voltage Vpr2. In addition, the word line WL is in the selected state. Therefore, the power lines V_VDM and V_VSM are precharged to the voltage Vpr2, and the voltages of the nodes Q and Qb are fixed to Vpr2.

[0228] At t4, the wiring OGL becomes "H", thereby turning on the transistors MW5 and MW6. The charge of the capacitor CS5 is distributed to the node Q and the node SN1. The charge of the capacitor CS6 is distributed to the node Qb and the node SN2. As a result, a voltage difference is generated between the node Q and the node Qb.

[0229] At t5, the supply of voltages VDM and GND is started again. The memory cell 240 becomes active and the voltage difference between nodes Q and Qb is amplified. Finally, the voltage of nodes Q and SN1 becomes Vddd, and the voltage of nodes Qb and SN2 becomes GND. That is, the states of nodes Q and Qb are restored to the states at t1 (i.e., "H" and "L"), respectively.

[0230] <Storage Unit 238>

[0231] Fig.17AThe illustrated memory cell 238 is a modified example of the memory cell 237, and includes a backup circuit 242 instead of the backup circuit 241. The backup circuit 242 is formed of a 1T1C type memory cell, and includes a node SN3, a transistor MW7, and a capacitor CS7.

[0232] Fig. 17B 2 is a timing chart showing an example of the operation of the storage unit 238. The storage unit 238 operates in the same manner as the storage unit 237. Fig. 17B The description can be cited Fig. 16B Description.

[0233] Backup circuit 242 only backs up the data of node Q, but can restore the data of nodes Q and Qb using the data held by node SN3. This is because nodes Q and Qb are precharged to Vpr2, so a potential difference can be generated between nodes Q and Qb by using the charge of capacitor CS7.

[0234] In this specification, a memory device including an OS transistor as a data storage unit of a memory cell may be referred to as an OS-memory device. Examples of OS-memory devices include DOSRAM (registered trademark), NOSRAM (registered trademark), and OS-SRAM.

[0235] DOSRAM is the abbreviation of Dynamic Oxide Semiconductor RAM (dynamic oxide semiconductor random access memory), which refers to a storage unit including 1T1C type (refer to Fig.15F ) RAM. NOSRAM is the abbreviation of Nonvolatile Oxide Semiconductor RAM (non-volatile oxide semiconductor random access memory), which refers to a RAM including a gain unit (refer to Fig.14A , FIG. 15A to FIG. 15D ) RAM. OS-SRAM is an SRAM cell that includes a backup circuit (see Fig.16A , Fig.17A ) of RAM.

[0236] Next, a processing device is described as an example of a semiconductor device. Here, a microcontroller unit (MCU) and an FPGA are exemplified.

[0237] MCU

[0238] Fig.18 The MCU 250 is a semiconductor device capable of clock gating and power gating.

[0239] The MCU 250 is input with voltages Vddd, Vdda, and GND. The MCU 250 includes a power management unit (PMU) 260, a negative voltage supply device 261, a bus 262, power switches 264 and 265, a level converter (LS) and a buffer circuit 267, a processor core 270 (hereinafter referred to as the core 270), and a storage device 280. Data and the like are transmitted between the PMU 260, the core 270, and the storage device 280 via the bus 262.

[0240] In order to reduce the power consumption of a semiconductor device, a circuit that does not need to work is stopped by using power gating or clock gating. A flip-flop is one of the sequential circuits (storage circuits that maintain their states) included in a semiconductor device in many cases. Therefore, by reducing the power consumption of the flip-flop, the power consumption of the semiconductor device including the flip-flop can be effectively reduced. Generally speaking, when the power supply is stopped, the state of the flip-flop is eliminated (the data held therein disappears). Therefore, in order to perform power gating on a semiconductor device, it is necessary to back up the state of the flip-flop.

[0241] The core 270 includes a plurality of flip-flops 271. The flip-flops 271 are provided in various registers of the core 270. The flip-flops 271 include a backup circuit 272 and a scan flip-flop 273. In other words, the flip-flop 271 is a scan flip-flop including a backup circuit.

[0242] In order to back up the data of the flip-flop 271 during clock gating and power gating, a backup circuit 272 is provided in the flip-flop 271. The backup circuit 272 includes a plurality of OS transistors having back gates. Since the backup circuit 272 does not include Si transistors, the backup circuit 272 can be stacked on a logic unit composed of Si transistors. Fig.19 An example of a circuit structure of the flip-flop 271 is shown.

[0243] The scan flip-flop 273 includes nodes D1 , Q1 , SD, SE, RT, CK10 , and a clock buffer circuit 273A.

[0244] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK10 is an input node for clock signal GCLK10. Clock signal GCLK10 is input to clock buffer circuit 272A. The analog switches in scan trigger 273 are electrically connected to nodes CK11 and CKB11 of clock buffer circuit 273A, respectively. Node RT is an input node for reset signal.

[0245] When the signal SCE is "L", the data of the node D1 is input to the scan flip-flop 273. When the signal SCE is "H", the data of the node SD is input to the scan flip-flop 273.

[0246] The circuit structure of the scan trigger 273 is not limited to Fig.19 Circuit structure. Scan triggers prepared in a standard circuit library can be used.

[0247] The backup circuit 272 includes nodes SD_IN, SN11, transistors MO11 to MO13, capacitor C11, and node SN11. The on / off of transistors MO11 and MO13 is controlled by signals BKH, and the on / off of transistor MO12 is controlled by signals RCH. The back gates of transistors MO11 to MO13 are electrically connected to wiring BGL2 in the CPU core 330. Negative voltage Vbg2 is input to wiring BGL1.

[0248] The node SD_IN is an input node of scan test data and is electrically connected to the node Q1 of the other scan flip-flop 273. The node SN11 is a holding node of the backup circuit 340.

[0249] Since the off-state current of the OS transistor is extremely small, the voltage drop of the node SN11 can be suppressed, and almost no power is consumed when retaining data, so the backup circuit 272 can retain data for a long time, that is, it has non-volatility. Therefore, during the period when the CPU core 330 is in the power-gated state, the data can be retained in the backup circuit 340.

[0250] The storage device 280 includes a control circuit 281, a peripheral circuit 282, and a memory cell array 283. As the storage device 280, the above-mentioned OS-storage device can be used.

[0251] The negative voltage supply device of Embodiment 2 is used as the negative voltage supply device 261. The negative voltage supply device 261 generates negative voltages Vbg1 and Vbg2 from the voltage GND. The negative voltage supply device 261 includes a plurality of terminals OB1 for outputting Vbg1 and a plurality of terminals OB2 for outputting Vb2. The negative voltages Vbg1 and Vbg2 are input to the memory device 280 and the core 270, respectively.

[0252] The MCU 250 receives input of a clock signal, an interrupt request signal, and the like from the outside. The external clock signal is input to the PMU 260 , and the interrupt request signal is input to the PMU 260 and the core 270 .

[0253] The PMU 260 has the function of controlling clock gating and power gating. The PMU 260 generates a gated clock signal GCK10 (hereinafter referred to as GCLK10) from an external clock signal. The clock signal GCLK10 is input to the core 270 and the storage device 280. The PMU 260 generates various control signals. The control signals include control signals of the power switches 264 and 265, control signals of the backup circuit 272, and control signals (e.g., reset signals) of the scan flip-flop 273.

[0254] The control signal of the backup circuit 272 is input to the LS and buffer circuit 267. The LS and buffer circuit 267 has a function of converting the level of the control signal and a function of holding the control signal of the converted level. The control signal held by the LS and buffer circuit 267 is input to the backup circuit 272.

[0255] The power switch 264 controls the supply of the voltage Vddd to the core 270. The power switch 265 controls the supply of the voltages Vddd and Vdda to the memory device 280. In the case where the core 270 includes a plurality of power domains, a power switch corresponding to each power domain is provided as the power switch 264. The above also applies to the power switch 265. In addition to the voltages Vddd and Vdda, a plurality of positive voltages are input to the memory device 280 according to the circuit structure. The positive voltage input to the memory device 280 is a voltage for precharging the bit line, a reference voltage for data reading, and the like.

[0256] The signal SLEEP is output from the core 270 to the PMU 260. The signal SLEEP is a trigger signal for switching the core 270 to the sleep mode (standby mode). When the signal SLEEP is input to the PMU 260, the PMU 260 outputs a control signal for switching from the active mode to the sleep mode to the functional circuit to be controlled. The switching from the active mode to the sleep mode can be performed by inputting an interrupt request signal.

[0257] First, in order to switch the core 270 from the active mode to the sleep mode, the PMU 260 stops supplying the clock signal to the core 270. Next, the data in the scan flip-flop 273 is written to the backup circuit 272. Specifically, the backup circuit 272 is input with a signal BKH of "H" during a predetermined clock cycle.

[0258] For example, by inputting an interrupt request signal, a process for restoring the core 270 from the sleep mode to the active mode is executed. According to the interrupt request signal, the PMU 260 outputs a control signal for switching from the sleep mode to the active mode to the functional circuit to be controlled. The PMU 260 controls the power switches 264 and 265 to restart the supply of potential to the core 270 and the storage device 280. Next, the data held by the backup circuit 272 is restored to the scan flip-flop 273. Specifically, the "H" signal BCH is input to the backup circuit 272 during a predetermined clock cycle, and the "H" signal SCE is input to the scan flip-flop 273. Finally, the clock signal GCLK10 is restarted to be supplied to the core 270 and the storage device 280.

[0259] The PMU 260 performs clock gating and power gating of the memory device 280 in the same manner as the core 270 .

[0260] In addition, a timer circuit for measuring time may be provided in the PMU 260 , and power gating of the core 270 and the memory device 280 may be performed based on the measured time.

[0261] FPGA

[0262] Fig. 20 An example of FPGA is shown. Fig. 20 The FPGA 400 shown includes a negative voltage supply device 405, a logic array 410, an input / output unit (I / O) 411, and peripheral circuits. One or more of the above-mentioned OS-storage devices may be incorporated into the FPGA 400.

[0263] I / O 411 is an input and output interface of logic array 410. The peripheral circuit includes a functional circuit for driving logic array 410 and I / O 411. For example, the peripheral circuit includes a clock generator 412, a configuration controller 413, a context controller 414, a row driver 415, and a column driver 416. FPGA 400 is input with Vddd, Vdda, and GND.

[0264] The negative voltage supply device 405 is the negative voltage supply device of Embodiment 2. The negative voltage supply device 405 generates a negative voltage Vbg4 from the voltage GND and includes a plurality of terminals OB for the negative voltage Vbg4. The FPGA 400 includes an OS transistor in a configuration data storage unit. The negative voltage Vbg4 is input to the back gate of the OS transistor.

[0265] The logic array 410 includes a routing switch array (RSA) 421 and a logic element (LE) 425. Here, the LE 425 is a logic circuit with 4 inputs and 1 output. The RSA 421 includes a plurality of routing switches (RS: routing switch) 422. Each RS 422 controls the connection between two LEs 422. Multiple LEs 425 arranged on the same column can also be connected to each other to form a register chain.

[0266] LE425 includes multiple configuration memories (CFM) 426. The circuit structure of LE425 is determined by the configuration data stored in CFM426. CFM426 is a configuration memory corresponding to multiple contexts capable of storing configuration data groups. In addition, RS422 includes a memory corresponding to multiple contexts, and the connection between LE425 is determined by the configuration data stored in RS422.

[0267] By switching the loaded configuration data group, the circuit structure of FPGA400 can be quickly changed. The switching of the configuration data group can be performed by context controller 414. Row driver 415 and column driver 416 are circuits used to drive RS422 and CFM426. Configuration controller 413 has the function of controlling row driver 415 and column driver 416.

[0268] Here, a circuit structure example of the logic array 410 of two contexts is described. The two contexts are called "CNTXT0" and "CNTXT1". The context signal used to select CNTXT0 is called "ctx[0]" and the context signal used to select CNTXT1 is called "ctx[1]".

[0269] <Wiring switch (RS)>

[0270] RSA421 includes multiple RS422. Fig.21A The structure example of RS422 is shown. RS422 is a programmable wiring switch, wherein terminal IN2 is electrically connected to the output terminal of LE425, and terminal OUT2 is electrically connected to the input terminal of other LE425. In RS422, two switch circuits 423 (hereinafter, referred to as SW423) are electrically connected in parallel between terminal IN2 and terminal OUT2. Note that when the number of contexts is greater than 2, the same number of SW423 as the number of contexts can be electrically connected in parallel between terminal IN2 and terminal OUT.

[0271] SW423 has the same circuit structure as the 3T-type gain cell. The back gate of the OS transistor of SW423 is electrically connected to the wiring BGL2. Negative voltage Vbg4 is input to the wiring BGL2.

[0272] SW423[0] and SW423[1] are connected to the common bit line BL. The column driver 416 writes the configuration data to the bit line BL. SW423[i] (i is 0 or 1) is electrically connected to the word line WL[i] and the wiring CXL[i]. The wiring CXL[i] is a wiring for context signals. When CNTXT0 is selected, the selection transistor of SW423[0] is turned on according to ctx[0], and the selection transistor of SW423[1] is turned off by ctx[1]. On the other hand, when CNTXT1 is selected, the selection transistor of SW423[0] is turned off, and the selection transistor of SW423[1] is turned on.

[0273] <Configuration Memory (CFM)>

[0274] Fig.21B 4 shows an example of the structure of the CFM 426. The CFM 426 includes two memory cells 428 and two transistors ME.

[0275] The memory cells 428[0] and 428[1] are electrically connected to a common bit line pair (BL, BLB). Configuration data and inverted data are written to the bit line BL and the bit line BLB, respectively. The memory cell 428[i] is electrically connected to the word line WL[i] and the wiring CXL[i]. The transistor ME[i] controls the conduction state between the terminal OUT3 and the output terminal of the memory cell 428[i].

[0276] The memory cell 428[i] is composed of two gain cells. One gain cell stores data of the bit line BL, and the other stores data of the bit line BLB. The back gate of the OS transistor of the memory cell 428[i] is electrically connected to the wiring BGL4.

[0277] When CNTXT0 is selected, transistor ME[0] is turned on according to ctx[0], and the configuration data stored in memory cell 428[0] is output from terminal OUT3. When CNTXT1 is selected, transistor ME11[1] is turned on according to ctx[1], and the configuration data stored in memory cell 428[1] is output.

[0278] <<Camera Equipment>>

[0279] In this embodiment, an imaging device is described as an example of a semiconductor device. Fig.22A The camera device 440 shown includes a negative voltage supply device 441, a control circuit 442, a pixel array 443, and a peripheral circuit 444. The peripheral circuit 444 includes a row driver 445 and a column driver 446. The pixel array 443 includes a plurality of pixels 448 arranged in a row and column matrix. The pixel 448 is a camera device, which has a function of converting light into electric charge and a function of storing electric charge, etc.

[0280] Voltages Vddd, Vdda, and GND are input to the imaging device 440. The negative voltage supply device of Embodiment 2 is used as the negative voltage supply device 441. The negative voltage supply device 441 generates a negative voltage Vbg5 from the voltage GND, and includes a plurality of terminals OB for the negative voltage Vbg5.

[0281] Fig. 22B An example of pixel 448 is shown. Pixel 448 includes a photodiode PD1, transistors MI1 to MI4, a capacitor C40, and a node FN40. Node FN40 is used as a data holding node. Capacitor C40 is a storage capacitor for holding the voltage of node FN40. Transistor MI1 is called a reset transistor. Transistor MI1 has a function of resetting the voltage of node FN40. Transistor MI2 is called an exposure transistor for controlling exposure work. Transistor MI2 is a transfer transistor for controlling the conduction state between node FN40 and photodiode PD1. By using transistor MI2, the timing of the exposure work can be controlled, so that imaging can be performed in a global shutter manner. Transistor MI3 is called an amplification transistor. Transistor MI3 has a function of generating an on-state current corresponding to the voltage of node FN40. Transistor MI4 is called a selection transistor. Transistor MI4 is a transfer transistor for controlling the conduction state between transistor MI3 and the output terminal of pixel 448.

[0282] The back gates of transistors MI1 and MI2 are electrically connected to wiring BGL5. Negative voltage Vbg5 is input to wiring BGL5, thereby reducing off-state currents of transistors MI1 and MI2. Therefore, the voltage variation of node FN40 can be further suppressed, and high-precision imaging can be performed.

[0283] As the photodiode PD1, a pn junction or pi junction diode element in a silicon substrate or a pin diode element using an amorphous silicon film (amorphous silicon film, microcrystalline silicon film) can be used. Note that other photoelectric conversion elements can also be used instead of the photodiode in pixel 448. For example, a diode-connected transistor can also be used. In addition, silicon, germanium, selenium, etc. can also be used to form a variable resistor that utilizes a photoelectric effect. In addition, a photoelectric conversion element containing selenium that utilizes the phenomenon of so-called avalanche multiplication can also be used. In this photoelectric conversion element, a highly sensitive sensor with a large amount of electron amplification relative to the amount of incident light can be obtained. As a selenium-based material, amorphous selenium or crystalline selenium can be used. For example, crystalline selenium can be obtained by performing a heat treatment after forming amorphous selenium. When the particle size of the crystalline selenium is smaller than the pixel pitch, the characteristic deviation between each pixel 448 can be reduced.

[0284] Electronic components

[0285] Next, refer to Fig.23A and Fig. 23B An electronic component including the semiconductor device described above is described.

[0286] Fig.23A The electronic component 7000 shown is a packaged IC chip, which includes leads and a circuit portion. Fig.23A In the embodiment, a quad flat package (QFP) is used as the package of the electronic component 7000, but the implementation of the package is not limited to this.

[0287] Electronic component 7000 is mounted on, for example, printed circuit board 7002. A plurality of such IC chips are combined on printed circuit board 7002 and electrically connected to each other, thereby forming a circuit board (circuit board 7004) on which electronic components are mounted.

[0288] The circuit portion of the electronic component 7000 has a laminated structure. The circuit portion includes at least three layers 7031 to 7033. The layer 7031 includes a Si transistor formed from a Si wafer. The layers 7032 and 7033 include an OS transistor and a capacitor, respectively. The layer 7033 may be provided between the layers 7031 and 7032.

[0289] Fig. 23B 7400 is a schematic diagram of an electronic component 7400. The electronic component 7400 is a camera module, which includes an image sensor chip 7451. The image sensor chip 7451 includes a camera device 440 (see Fig.22A ). The image sensor chip 7451 includes at least layers 7031 to 7033 and a layer 7034. The layer 7034 includes a photoelectric conversion element.

[0290] The electronic component 7400 includes a package substrate 7411 fixed with an image sensor chip 7451, a lens cover 7421, and a lens 7435. In order to show the internal structure of the electronic component 7400, Fig. 23B The lens cover 7421 and a portion of the lens 7435 are omitted.

[0291] A signal processing circuit and the like are provided between the package substrate 7411 and the image sensor chip 7451. The electronic component 7400 is a system in package (SiP).

[0292] The land 7441 is electrically connected to the electrode pad 7461. The electrode pad 7461 is electrically connected to the image sensor chip 7451 or the IC chip 7490 through the wire 7471. The IC chip 7490 may also include the above-mentioned OS-storage device.

[0293] <<Electronic equipment>>

[0294] Reference Fig.24A and Fig.24D An embodiment of an electronic device including the above-described electronic component will be described.

[0295] Fig.24A A structural example of a tablet information terminal is shown. Fig.24A The information terminal 2010 shown includes a housing 2011, a display unit 2012, an illuminance sensor 2013, a camera 2015, and operation buttons 2016. A storage device and a processing device are incorporated into the housing 2011, and these devices are formed by the electronic component 7000. The electronic component 7000 can also be used for a controller of the display unit 2012. The electronic component 7440 is used for the camera 2015.

[0296] The display unit 2012 includes a display system incorporating a touch sensor. When a touch pen 2017 (or electronic pen), a finger, or the like touches the screen of the information terminal 2010, the information terminal 2010 can be operated. The information terminal 2010 has functions such as audio calls, video calls using the camera 2015, e-mail, notebook, Internet access, and music playback.

[0297] Fig. 24B A configuration example of a personal computer (PC) is shown. Fig. 24B The PC 2030 includes a housing 2031, a display unit 2032, an illumination sensor 2034, a camera 2035, and a keyboard 2036. The keyboard 2036 may also have a structure that is detachable from the housing 3031. When the keyboard 2036 is installed in the housing 2033, the PC 2030 can be used as a notebook PC. When the keyboard 2036 is detachable from the housing 2031, the PC 3030 can be used as a tablet PC.

[0298] A storage device, a processing device, a controller of the display unit 2032, and the like are incorporated in the housing 3011. As these devices, an electronic component 7000 is used. As the camera 2035, an electronic component 2440 is used.

[0299] Fig.24C The robot 2100 shown includes an illumination sensor 2101 , a microphone 2102 , an upper camera 2103 , a speaker 2104 , a display unit 2105 , a lower camera 2106 , an obstacle sensor 2107 , a moving mechanism 2108 , a processing device 2110 , and a storage device 2111 .

[0300] The electronic component 7000 can be used in the processing device 2110, the storage device 2111, the controller of the display unit 2105, etc. The electronic component 7440 is used in the upper camera 2103 and the lower camera 2106.

[0301] Various information is displayed on the display unit 2105. The robot 2100 can display information that the user wants to see on the display unit 2105. The display unit 2105 may also be equipped with a touch panel.

[0302] By using the microphone 2102 and the speaker 2104, voice communication between the user and the robot 2100 can be achieved.

[0303] The upper camera 2103 and the lower camera 2106 capture images of the surroundings of the robot 2100. For example, based on the information of the user captured by the upper camera 2103, a sound emitted by the robot 2100 from the speaker 2104 is selected.

[0304] The robot 2100 can move using a moving mechanism 2108. The obstacle sensor 2107 can sense whether there is an obstacle in the moving direction of the robot 2100. The robot 2100 can recognize the surrounding environment using the upper camera 2103, the lower camera 2106, and the obstacle sensor 2107, and can move safely and independently.

[0305] Fig.24D The flying object 2120 shown includes a processing device 2121, a storage device 2122, a camera 2123, and a propeller 2124. The electronic component 7000 is used in the processing device 2121, the storage device 2122, etc. The electronic component 7400 is included in the camera 2123.

[0306] Fig.24D The car 2140 shown includes various sensors such as infrared radar, millimeter wave radar, and laser radar. The car 2140 analyzes the image captured by the camera 2141 to determine the traffic information around it, such as the presence of guardrails 2150 or pedestrians, so that it can perform automatic driving. The camera 2141 is assembled with an electronic component 7400. In addition, the electronic circuit (for example, a processing device, a storage device) of the car 2140 is assembled with the above-mentioned electronic component 7000.

[0307] <<Circuit section of electronic components>>

[0308] Reference Fig.25 The laminated structure of the circuit portion of the electronic component 7000 is described. As an example, Fig.25 The storage unit 237 (see Fig.16A ) cross-sectional structure. Fig.25 Transistor MW5, capacitor CS5, and transistor MT5 are shown. Transistor MT5 is a transfer transistor formed of a single crystal silicon wafer 5500 and electrically connected to the bit line BL. Fig.25It is a cross-sectional view for explaining an example of a stacked structure of an IC chip, and is not a cross-sectional view of the IC chip taken along a specific line.

[0309] The transistor MT5, the transistor MW5, and the capacitor CS5 are formed in the layer 7031, the layer 7032, and the layer 7033, respectively. A plurality of wiring layers are provided between the layers 7031 and 7032. The wiring layers include word lines WL and the like. The transistor MW5 has the same structure as the OS transistor 5003 (see FIG. 1 ) described later. Fig.26B )Same structure.

[0310] 《Structural Example of OS Transistor》

[0311] Next, refer to Fig.26A and Fig.26B A structural example of an OS transistor is described. Fig.26A and Fig.26B The left side of shows the cross-sectional structure of the OS transistor in the channel length direction. Fig.26A and Fig.26B The right side of shows the cross-sectional structure of the OS transistor in the channel width direction.

[0312] Fig.26A The OS transistor 5001 shown is formed on an insulating surface, here, on an insulating layer 5001. Here, the OS transistor 5001 is formed on an insulating layer 5021. The OS transistor 5001 is covered by insulating layers 5028 and 5029. The OS transistor 5001 includes insulating layers 5022 to 5027, 5030 to 5032, metal oxide layers 5011 to 5013, and conductive layers 5050 to 5054.

[0313] The insulating layer, metal oxide layer, conductor, etc. in the drawings may each have a single layer structure or a stacked layer structure. These layers may be formed using various deposition methods such as sputtering, molecular beam epitaxy (MBE), pulsed laser ablation (PLA), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Examples of CVD methods include plasma CVD, thermal CVD, and organometallic CVD.

[0314] The metal oxide layers 5011 to 5013 are collectively referred to as oxide layers 5010. Fig.26A As shown, the oxide layer 5010 includes a portion in which a metal oxide layer 5011, a metal oxide layer 5012, and a metal oxide layer 5013 are sequentially stacked. When the OS transistor 5001 is turned on, a channel is mainly formed in the metal oxide layer 5012 of the oxide layer 5010.

[0315] The gate electrode of the OS transistor 5001 is formed using a conductive layer 5050. A pair of electrodes used as a source electrode and a drain electrode of the OS transistor 5001 are formed using conductive layers 5051 and 5052. The conductive layers 5050 to 5052 are covered with insulating layers 5030 to 5032 as barrier layers. The back gate electrode of the OS transistor 5001 is formed using a stack of conductive layers 5053 and 5054.

[0316] The gate insulating layer on the gate side is formed using an insulating layer 5027. The gate insulating layer on the back gate side is formed using a stack of insulating layers 5024 to 5026. An insulating layer 5028 is an interlayer insulating layer. An insulating layer 5029 is a barrier layer.

[0317] The metal oxide layer 5013 covers the stacked body of the metal oxide layers 5011 and 5012 and the conductive layers 5051 and 5052. The insulating layer 5027 covers the metal oxide layer 5013. The conductive layers 5051 and 5052 have a region overlapping with the conductive layer 5050 via the metal oxide layer 5013 and the insulating layer 5027.

[0318] Examples of conductive materials used for the conductive layers 5050 to 5054 include: semiconductors represented by polycrystalline silicon doped with impurity elements such as phosphorus; silicides such as nickel silicide; metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; and metal nitrides containing the above metals as components (tantalum nitride, titanium nitride, molybdenum nitride, and tungsten nitride). In addition, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon oxide may also be used.

[0319] For example, the conductive layer 5050 is a single layer of tantalum nitride or tungsten. Alternatively, when the conductive layer 5050 is a two-layer structure or a three-layer structure, the following combinations can be used: aluminum and titanium; titanium nitride and titanium; titanium nitride and tungsten; tantalum nitride and tungsten; tungsten nitride and tungsten; titanium, aluminum and titanium; titanium nitride, aluminum and titanium; titanium nitride, aluminum and titanium. The first-mentioned conductor is used for the layer on the insulating layer 5027 side.

[0320] The conductive layers 5051 and 5052 have the same layer structure. For example, when the conductive layer 5051 is a single layer, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing these metals as a main component can be used. When the conductive layer 5051 is a two-layer structure or a three-layer structure, the following combinations can be used: titanium and aluminum; tungsten and aluminum; tungsten and copper; copper-magnesium-aluminum alloy and copper; titanium and copper; titanium or titanium nitride, aluminum or copper, and titanium or titanium nitride; molybdenum or molybdenum nitride, aluminum or copper, and molybdenum or molybdenum nitride. Among them, the first-mentioned conductor is used for the layer on the insulating layer 5027 side.

[0321] For example, it is preferable that the conductive layer 5053 is a conductive layer having a barrier property against hydrogen (for example, a tantalum nitride layer), and the conductive layer 5054 is a conductive layer (for example, a tungsten layer) having a higher conductivity than the conductive layer 5053. With this structure, the stack of the conductive layers 5053 and 5054 is used as wiring and has a function of suppressing the diffusion of hydrogen into the oxide layer 5010.

[0322] Examples of insulating materials used for the insulating layers 5021 to 5032 include aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate. The insulating layers 5021 to 5032 are each formed using a single-layer structure or a stacked-layer structure of these insulating materials. The layers used for the insulating layers 5021 to 5032 may include a plurality of insulating materials.

[0323] In this specification and the like, an oxynitride refers to a compound containing a larger amount of oxygen than nitrogen, and a nitrogen oxide refers to a compound containing a larger amount of nitrogen than oxygen.

[0324] In the OS transistor 5001, the oxide layer 5010 is preferably surrounded by an insulating layer having barrier properties to oxygen and hydrogen (hereinafter, such insulating layer is referred to as a barrier layer). By adopting this structure, the release of oxygen from the oxide layer 5010 can be suppressed and the intrusion of hydrogen into the oxide layer 5010 can be suppressed, thereby improving the reliability and electrical characteristics of the OS transistor 5001.

[0325] For example, the insulating layer 5029 may be used as a barrier layer, and at least one of the insulating layers 5021, 5022, and 5024 may be used as a barrier layer. The barrier layer may be formed using materials such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and silicon nitride. Another barrier layer may be provided between the oxide layer 5010 and the conductive layer 5050. Alternatively, a metal oxide layer having barrier properties to oxygen and hydrogen may be provided as the metal oxide layer 5013.

[0326] The insulating layer 5030 is preferably a barrier layer that prevents oxidation of the conductive layer 5050. When the insulating layer 5030 has a barrier property against oxygen, oxidation of the conductive layer 5050 by oxygen released from the insulating layer 5028 or the like can be suppressed. For example, the insulating layer 5030 can be formed using a metal oxide such as aluminum oxide.

[0327] Fig.26AAlthough an example of a three-layer structure of the oxide layer 5010 is shown, one embodiment of the present invention is not limited thereto. For example, the oxide layer 5010 may be a two-layer structure without the metal oxide layer 5011 or 5013, or may be composed of one layer of the metal oxide layer 5011 and 5012. In addition, the oxide layer 5010 may also be composed of four or more metal oxide layers.

[0328] Fig.26B The OS transistor 5003 is different from the OS transistor 5001 in the structures of the gate electrode and the oxide layer.

[0329] The gate electrode (5050) of the OS transistor 5003 is covered by insulating layers 5033 and 5034. The OS transistor 5003 includes an oxide layer 5009 formed of metal oxide layers 5011 and 5012. Low resistance regions 5011a and 5011b are provided in the metal oxide layer 5011, and low resistance regions 5012a and 5012b are provided in the metal oxide layer 5012 instead of the conductive layers 5051 and 5052. The low resistance regions 5011a, 5011b, 5012a, and 5012b can be formed by selectively adding impurity elements (e.g., hydrogen and nitrogen) to the oxide layer 5009.

[0330] By adding an impurity element to the metal oxide layer, oxygen vacancies are formed in the region to which the impurity element is added, and the impurity element invades the oxygen vacancies. Therefore, the carrier density increases, thereby reducing the resistance of the region.

[0331] 《Metal Oxides》

[0332] The channel formation region of the OS transistor preferably includes a cloud-aligned composite metal oxide semiconductor (CAC-OS).

[0333] CAC-OS has a conductive function in a part of the material and an insulating function in another part of the material, and as a whole, CAC-OS has a semiconductor function. When CAC-OS or CAC metal oxide is used for the active layer of a transistor, the conductive function allows electrons (or holes) used as carriers to flow, and the insulating function prevents electrons used as carriers from flowing. Through the complementary effects of the conductive function and the insulating function, CAC-OS can have a switching function (on / off function). In CAC-OS, each function can be maximized by separating each function.

[0334] CAC-OS includes a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Sometimes the conductive region and the insulating region in the material are separated at the nanoparticle level. Sometimes the conductive region and the insulating region are unevenly distributed in the material. Sometimes the conductive region is observed to have blurred edges and connected in a cloud shape.

[0335] In CAC-OS, the conductive region and the insulating region may have a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, and may be dispersed in the material.

[0336] CAC-OS includes components with different band gaps. For example, CAC-OS includes a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, carriers mainly flow through the component with a narrow gap. The component with a narrow gap complements the component with a wide gap, and carriers flow through the component with a wide gap in conjunction with the component with a narrow gap. Therefore, when the above-mentioned CAC-OS is used in the channel formation region of a transistor, a high current driving force and a high field effect mobility of the OS transistor can be achieved.

[0337] Metal oxide semiconductors are classified into single crystal metal oxide semiconductors and non-single crystal metal oxide semiconductors according to their crystallinity. Examples of non-single crystal metal oxide semiconductors include c-axis aligned crystalline metal oxide semiconductor (CAAC-OS), polycrystalline metal oxide semiconductors, nanocrystalline metal oxide semiconductors (nc-OS), and amorphous-like metal oxide semiconductors (a-like OS).

[0338] The channel formation region of the OS transistor preferably includes a metal oxide having a crystalline portion, such as CAAC-OS or nc-OS.

[0339] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction, and the crystal structure has distortion. Distortion refers to the part where the lattice arrangement direction changes between the region where multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0340] In nc-OS, tiny regions (e.g., regions above 1 nm and below 10 nm, especially regions above 1 nm and below 3 nm) have periodic atomic arrangements. There is no regularity in the crystal orientation between different nanocrystals in nc-OS. Therefore, the orientation of the entire film cannot be observed. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0341] a-like OS has a structure between nc-OS and amorphous metal oxide semiconductor. a-like OS contains voids or low-density regions. a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0342] In this specification and the like, CAC represents a function or material of a metal oxide semiconductor, and CAAC represents a crystal structure of a metal oxide semiconductor.

[0343] Explanation of symbols

[0344] 9A, 9B: Curves, 10, 11, 20, 21, 22, 23, 24, 25, 171, 172: Comparison circuit, 14, 15, 34: Differential pair, 17: Current source, 18: Load circuit, 30, 31, 32, 33, 172A: Differential input circuit, 35, 40, 41, 42, 43, 45: Output circuit, 38, 39: Inverter circuit, 100, 101: Negative voltage supply device, 111, 141: Control circuit , 112, 117A, 117B, 117C, 123, 142, 153: charge pump circuit, 114: bias voltage generating circuit, 120, 150: output voltage regulator, 122, 152: negative voltage holding circuit, 127, 154: drive circuit, 128, 155, 161, 162: monitoring circuit, 143: frequency division circuit, 171, 172: comparison circuit, 173: latch circuit, 175, 177: selection circuit,

[0345] 200, 211, 280: storage device, 210, 261: negative voltage supply device, 215, 281: control circuit, 220, 283: storage cell array, 221, 282: peripheral circuit, 223: row circuit, 224: column circuit, 225: input and output circuit, 230, 231, 232, 233, 234, 235, 236, 237, 238, 240: storage unit, 241, 242, 272: backup circuit, 250: microcontroller unit (MCU), 260: power management unit (PMU), 262: bus, 264, 265: power switch, 265: power switch, 267: level converter (LS) and buffer circuit, 270: processor core, 271: trigger, 272A, 273B: clock buffer circuit, 273: scan trigger, 330: CPU core,

[0346] 340: backup circuit, 400: FPGA, 405: negative voltage supply device, 410: logic array, 411: input output unit (I / O), 412: clock generator, 413: configuration controller, 414: context controller, 415: row driver, 416: column driver, 421: wiring switch array (RSA), 422: wiring switch (RS), 423: switch circuit (SW), 425: logic element (LE), 426: configuration memory (CFM), 428: storage unit, 440: camera device, 441: negative voltage supply device, 442: control circuit, 443: pixel array, 444: peripheral circuit, 445: row driver, 446: column driver, 448: pixel, 2010: information terminal, 2011, 2031, 3011, 3031: housing, 2012, 2032, 2105: display unit, 2013, 2034, 2101: illumination sensor, 2015, 203 5, 2123, 2141: camera, 2016: operation button, 2017: touch pen, 2030, 3030: PC, 2036: keyboard, 2100: robot, 2102: microphone, 2103: upper camera, 2104: speaker, 2106: lower camera, 2107: obstacle sensor, 2108: moving mechanism, 2110, 2121: processing device, 2111, 2122: storage device, 2120: flying object, 212 1: Processing device, 2124: Propeller, 2140, 2980: Car, 2150: Guardrail, 5001, 5003: OS transistor, 5009, 5010: Oxide layer, 5011, 5012, 5013: Metal oxide layer, 5011a, 5011b, 5012a, 5012b: Low resistance region, 5021, 5022, 5024, 5027, 5028, 5029, 5030, 5033, 5034: Insulation layer,

[0347] 5050, 5051, 5052, 5053, 5054: conductive layer, 5500: single crystal silicon wafer, 7400: electronic component, 7411: packaging substrate, 7421: lens cover, 7435: lens, 7440: electronic component, 7441: connection pad, 7451: image sensor chip, 7461: electrode pad, 7471: wire, 7490: IC chip,

[0348] BGL, BGL1, BGL2, BGL4, BGL5, CXL, OGL: wiring, BL, BLB: bit line, CK10, CK11, D1, FN40, Q, Qb, Q1, RT, SD, SD_IN, SE, SN1, SN2, SN3, SN11, X1, X2, X5, X6, X11, X12, X13: node, CDL: capacitor line, C11, C21, C22, C25, C40, CS1, CS3, CS5, CS6, CS7: capacitor, IN2, INN, INP, IN_cp, OB, OB1, OB2, OCM, OCMB, OUT2, OUT_cp, O UT3: terminal, MI1, MI2, MI3, MI4, MN1, MN5, MN6, MN7, MO1, MO2, MO3, MO5, MO7, MO11, MO12, MO13, MO14, MO21, MO22, MO25, MP1, MP2, MP5, MP6, MP7, MR1, MT5, MW1, MW2, MW3, MW5, MW6, MW7: transistor, PL2, PL3, V_VDM, V_VSM: power line, RBL: read bit line, RWL: read word line, Rd1, Rd2: load, SL: source line, WBL: write bit line, WL: word line, WWL: write word line.

[0349] This application is based on Japanese Patent Application No. 2017-107964 filed with the Japan Patent Office on May 31, 2017, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device comprising: Comparison circuit, comprising: A differential input circuit includes a first transistor and a second transistor, The first transistor and the second transistor each include a first gate and a second gate, A first input terminal of the comparison circuit is electrically connected to one of the first gate and the second gate of the first transistor, A second input terminal of the comparison circuit is electrically connected to the first gate of the second transistor, an output terminal of the comparison circuit is electrically connected to one of a source and a drain of the second transistor, A first power supply line is electrically connected to the other of the first gate and the second gate of the first transistor, And, a second power supply line is electrically connected to the second gate of the second transistor.

2. A semiconductor device comprising: Comparison circuit, including: A differential input circuit comprising a first transistor and a second transistor; in, The first transistor and the second transistor each include a first gate and a second gate, A first input terminal of the comparison circuit is electrically connected to one of the first gate and the second gate of the first transistor; A second input terminal of the comparison circuit is electrically connected to the first gate of the second transistor; An output terminal of the comparison circuit is electrically connected to one of a source and a drain of the second transistor; a first power supply line electrically connected to the other of the first gate and the second gate of the first transistor; A second power supply line is electrically connected to the second gate of the second transistor, Also, a first power supply voltage supplied to the first power supply line and a second power supply voltage supplied to the second power supply line are different from each other.

3. The semiconductor device according to claim 1 or 2, in, A reference voltage is input to the first input terminal, Also, a negative voltage is input to the second input terminal. 4 . The semiconductor device according to claim 1 , wherein a channel formation region of each of the first transistor and the second transistor includes a metal oxide.

5. The semiconductor device according to claim 1 or 2, in, The comparison circuit is a dynamic comparison circuit. Furthermore, the differential input circuit includes a latch circuit.

6. The semiconductor device according to claim 2, wherein the first power supply voltage is higher than the second power supply voltage.

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