Device and method for high-precision measurement of time interval by stepping delay chain based on FPGA (Field Programmable Gate Array)
By introducing a combination of adjustable delay unit and fixed delay unit in the FPGA delay chain, combined with the delay checksum latch module, the problem of low measurement stability and accuracy of delay chain in the prior art is solved, and the problem of low measurement stability and accuracy of delay chain is realized. Time interval measurements with high accuracy and high linearity are performed.
Patent Information
- Application Number
- CN202411290548.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-13
AI Technical Summary
The existing FPGA-based delay chain measurement methods are easily affected by process and environmental factors, resulting in reduced stability and accuracy of time measurement, and inability to effectively quantify errors, and the linearity between the measurement time and the number of delay chain units is not high.
Design a step-by-step delay chain based on FPGA, including a cascading N-level delay unit, each stage unit includes an adjustable delay unit and a fixed delay unit, and each stage is delayed through the delay verification module. The unit performs checksum adjustment, uses the latch module to latch the delay signal, calculates the time interval through the decoding module, and uses the time interval counter to perform accurate measurement.
The delay accuracy and linearity of the delay chain are improved, the stability and reliability of the measurement are ensured, and high-precision time interval measurement is achieved through the adjustment of the adjustable delay unit.
Smart Images
Figure CN119135134A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of signal processing, and in particular to a method and a device for measuring time intervals with high precision using a step-by-step delay chain based on FPGA. Background Art
[0002] With the rapid development of digital communication, chip design, time synchronization, measurement and other fields, higher and higher requirements are put forward for the accuracy of time interval measurement. The traditional FPGA-based delay chain interpolation method for measuring time intervals is easily affected by many factors, such as different device processes, environmental changes (temperature, voltage), etc., which reduces the stability and measurement accuracy of the delay chain time measurement. In addition, the existing delay chain measurement method cannot quantify the error, and the linearity between the measurement time and the number of delay chain units is not high. Summary of the invention
[0003] The main purpose of the present invention is to provide a device and method for measuring time intervals of a step-by-step delay chain based on FPGA, which can regularly calibrate the delay time accuracy of each level of the delay chain.
[0004] The technical solution adopted by the present invention is:
[0005] Provided is a device for measuring time intervals with high precision using a step-by-step delay chain based on FPGA, comprising:
[0006] A delay chain module is used to build a delay chain based on FPGA, which includes N-level cascaded delay units, where each level of delay unit includes an adjustable delay unit and a fixed delay unit;
[0007] The delay verification module is used for the delay verification module, which is used to perform step delay verification on the N-level delay unit through the calibration signal, specifically comparing it with the theoretical delay time, and if it does not meet the preset tolerance, adjusting the delay time of the adjustable delay unit of the corresponding level;
[0008] A latch module, used to latch the output state of the delay signal of each delay unit when the signal to be measured is measured;
[0009] The decoding module is used to perform tap processing on the latched N-level output states and calculate the delay time interval of the signal to be measured according to the delay time of each level of delay unit.
[0010] According to the above technical solution, the delay verification module specifically measures the delay time of the verification signal passing through each level of delay unit of the delay chain module through a time interval counter.
[0011] According to the above technical solution, the latch module includes N D flip-flops, and when the D flip-flops generate a latch signal, the output state of each level of delay signal is latched.
[0012] The present invention also provides a method for verifying a time interval of a step-by-step delay chain based on FPGA with high precision, comprising the following steps:
[0013] S1. Building a delay chain based on FPGA, the delay chain includes N-level cascaded delay units, wherein each level of delay unit includes an adjustable delay unit and a fixed delay unit;
[0014] S2. Perform step delay calibration on the N-stage delay units through calibration signals. Specifically, compare the delay time of each stage delay unit with the theoretical delay time through the calibration signal. If it does not meet the preset tolerance, adjust the delay time of the adjustable delay unit of the corresponding stage until it meets the preset tolerance.
[0015] Following the above technical solution, step S2 specifically includes the following steps:
[0016] a. Access the verification signal generated by the signal source;
[0017] b. Set the delay chain level n to be checked. The initial level is 0. After checking the current delay unit, the set value is increased by 1.
[0018] c. Set the adjustable delay time of the adjustable delay unit of the current delay unit, compare the delay time of the check signal through each delay unit with the theoretical delay time, and when it does not meet the tolerance standard, adjust the adjustable delay time according to the deviation;
[0019] d. After adjustment, continue to determine whether the deviation between the measured delay time and the theoretical delay time meets the tolerance standard. If not, repeat steps c and d; if it meets the tolerance standard, record the adjustable delay time of the current delay unit and execute step e;
[0020] e. Determine the delay chain level n of the current verification. If the delay chain level n is less than N, repeat steps b, c, d, and e; if the delay chain level n is N, the verification is completed and step f is executed;
[0021] f. End verification and cache N-level adjustable delay time.
[0022] Following the above technical solution, step d specifically uses a time interval counter to measure the time difference between the input verification signal and the output delay signal.
[0023] The present invention also provides a method for high-precision time interval measurement of a step-by-step delay chain based on FPGA, comprising the following steps:
[0024] Verify the delay chain according to the verification method of the above technical solution;
[0025] In the test task, N-level latches are set for the N-level delay unit. When the latch signal arrives, the state value of the signal to be tested passing through the current N-level step-by-step delay chain is latched;
[0026] The state values of the N-stage step-by-step delay chain are tapped, and then the time interval of the signal to be measured is calculated based on the delay time of the corresponding delay unit.
[0027] The beneficial effect of the present invention is that in addition to setting a fixed delay unit (with a fixed delay time) in each level of delay unit, the present invention also sets an adjustable delay unit (with an adjustable delay time). During calibration, the delay time of the adjustable delay unit can be adjusted to ensure high linearity of the number of delay units and the delay time, thereby improving the delay accuracy of the delay chain.
[0028] Furthermore, measuring the delay time of the calibration signal passing through each level of the delay unit of the delay chain module by a relatively high-precision counter is more conducive to improving the accuracy of calibration.
[0029] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0031] Figure 1 It is a structural schematic diagram of a device for measuring time intervals with high precision based on a step-by-step delay chain of an FPGA according to an embodiment of the present invention;
[0032] Figure 2 It is a flow chart of a verification method for high-precision measurement of time intervals of a step-by-step delay chain based on FPGA according to an embodiment of the present invention. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0034] It should be noted that the illustrations provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout type may also be more complicated.
[0035] In the present invention, it is also necessary to explain that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.
[0036] like Figure 1 As shown, the device for measuring time intervals with high precision based on a step-by-step delay chain of FPGA in an embodiment of the present invention comprises a delay chain module, a delay check module, a latch module and a decoding module.
[0037] Among them, the delay chain module is used to build a delay chain based on FPGA, and the delay chain includes N cascaded delay units, wherein each delay unit includes an adjustable delay unit and a fixed delay unit.
[0038] The delay verification module is used to perform step delay verification on N-level delay units through calibration signals. Specifically, the delay time of the verification signal passing through each level of the delay unit in the delay chain module is measured and compared with the theoretical delay time. If it does not meet the preset tolerance, the delay time of the adjustable delay unit of the corresponding level is adjusted.
[0039] The latch module is used to latch the output state of the delay signal of each level of delay unit when the signal to be measured is measured.
[0040] The decoding module is used to perform tap processing on the latched N-level output states, and calculate the delay time interval of the signal to be measured according to the delay time of each level of delay unit.
[0041] Furthermore, the delay verification module can specifically measure the delay time of the verification signal passing through each level of the delay unit of the delay chain module through a time interval counter.
[0042] Furthermore, the latch module includes N D flip-flops, and when the D flip-flops generate a latch signal, the output state of each level of delay signal is latched.
[0043] It can be seen that the step-by-step delay chain of this embodiment has a simple structure and is easy to implement; and the device can ensure the stability and reliability of the measurement system based on the adjustability of the delay unit and the delay verification module. After verification, the latch state of the time interval is decoded based on the latch module and the decoding module to obtain the delay time of the specific measurement signal.
[0044] Specifically, Figure 1 As shown in the figure, the delay chain module is composed of N-level delay units cascaded, and a single delay unit is composed of the delay cell (i.e., adjustable delay unit) and carry4 cell (i.e., fixed delay unit) of the FPGA, and processes the signal to be tested through N-level delay; the latch module is composed of N D flip-flops, and latches the output state of each level of delay signal when the latch signal is triggered; the decoding module performs tap processing on the latched N-level delay chain state, and calculates the time interval of the signal to be tested based on the delay characteristics of the delay unit; the delay verification module calibrates the verification signal and the delay signal based on the time interval counter (specifically, whether the offset time of the verification signal and the delay signal passing through each level of the delay chain meets the expected value, and whether the error meets the fault tolerance), and adjusts the delay time of each level of the delay unit. If the adjustment is performed, the range to be adjusted is generally within the adjustable range of the adjustable delay unit. If it exceeds the adjustable range, the delay chain can only be rebuilt, that is, the delay time of the fixed delay unit can be changed again.
[0045] It can be seen that this embodiment ensures the high linearity of the number of delay units and the delay time through the fixed delay of the carry4 cell and the adjustable delay of the delay cell. The delay verification module is used to perform delay verification, and the adjustable delay unit is adjusted, so that the delay time of each level of delay unit can be flexibly adjusted according to different application requirements, thereby improving the fault tolerance of the hardware environment. Through the adjustment of the adjustable delay unit, the resolution of a single delay unit can reach a high precision of 100ps.
[0046] The FPGA-based step-by-step delay chain high-precision measurement time interval verification method of the embodiment of the present invention comprises the following steps:
[0047] S1. Building a delay chain based on FPGA, the delay chain includes N-level cascaded delay units, wherein each level of delay unit includes an adjustable delay unit and a fixed delay unit;
[0048] S2. Perform step delay calibration on the N-stage delay units through calibration signals. Specifically, compare the delay time of each stage delay unit with the theoretical delay time through the calibration signal. If it does not meet the preset tolerance, adjust the delay time of the adjustable delay unit of the corresponding stage until it meets the preset tolerance.
[0049] Specifically, Figure 2As shown, step S2 specifically includes the following steps:
[0050] a. Access the verification signal generated by the signal source;
[0051] b. Set the delay chain level n (an integer greater than or equal to 0 and less than or equal to N) to be checked. The initial level is 0. After checking the current level delay unit, the set value is increased by 1.
[0052] c. Set the adjustable delay time of the adjustable delay unit of the current delay unit, compare the delay time of the check signal through each delay unit with the theoretical delay time, and when it does not meet the tolerance standard, adjust the adjustable delay time according to the deviation;
[0053] d. After adjustment, continue to determine whether the deviation between the measured delay time and the theoretical delay time meets the tolerance standard. If not, repeat steps c and d; if it meets the tolerance standard, record the adjustable delay time of the current delay unit and execute step e;
[0054] e. Determine the delay chain level n of the current verification. If the delay chain level n is less than N, repeat steps b, c, d, and e; if the delay chain level n is N, the verification is completed and step f is executed;
[0055] f. End verification and cache N-level adjustable delay time.
[0056] Specifically, in step c, the adjustable delay time of the current delay unit can be set, the initial adjustable delay is 0ps, and when the verification level is reset, the adjustable delay is also reset to 0ps; when the delay time of the delay unit does not meet the tolerance, the adjustable delay time is adjusted according to the deviation;
[0057] In step d, a time interval counter may be used to measure the time difference between the input verification signal and the output delay signal.
[0058] By applying the device and verification method of the above embodiment to a specific signal measurement environment, a method for high-precision time interval measurement of a step-by-step delay chain based on FPGA can be implemented, which mainly includes the following steps:
[0059] 1) Verify the delay chain according to the verification method of the above embodiment;
[0060] 2) In a specific test task, set N-level latches for the N-level delay unit. When the latch signal arrives, latch the state value of the signal to be tested through the current N-level step-by-step delay chain;
[0061] 3) The state values of the N-stage step-by-step delay chain are tapped, and then the time interval of the signal to be measured is calculated based on the delay time of the corresponding delay unit.
[0062] In summary, in addition to setting a fixed delay unit (with a fixed delay time) in each level of delay unit, the present invention also sets an adjustable delay unit (with an adjustable delay time). During calibration, the delay time of the adjustable delay unit can be adjusted to ensure high linearity of the number of delay units and the delay time, thereby improving the delay accuracy of the delay chain.
[0063] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, and two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.
[0064] The order of execution of each step in the above embodiment does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.
[0065] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.
Claims
1. A device for measuring time intervals with high precision using a step-by-step delay chain based on FPGA, characterized in that: include: A delay chain module is used to build a delay chain based on FPGA, which includes N-level cascaded delay units, where each level of delay unit includes an adjustable delay unit and a fixed delay unit; The delay verification module is used to perform step delay verification on the N-stage delay unit through the calibration signal, specifically measuring the delay time of the verification signal passing through each stage of the delay unit of the delay chain module, and comparing it with the theoretical delay time. If it does not meet the preset tolerance, the delay time of the adjustable delay unit of the corresponding stage is adjusted; A latch module, used to latch the output state of the delay signal of each delay unit when the signal to be measured is measured; The decoding module is used to perform tap processing on the latched N-level output states and calculate the delay time interval of the signal to be measured according to the delay time of each level of delay unit.
2. The device for measuring time intervals with high precision based on FPGA step-by-step delay chain according to claim 1, characterized in that: The delay verification module specifically measures the delay time of the verification signal passing through each level of delay unit of the delay chain module through a time interval counter.
3. The device for measuring time intervals with high precision based on FPGA step-by-step delay chain according to claim 1, characterized in that: The latch module includes N D flip-flops, and when the D flip-flops generate a latch signal, the output state of each level of delay signal is latched.
4. A method for verifying time intervals of a step-by-step delay chain based on FPGA with high precision, characterized in that: The following steps are involved: S1. Building a delay chain based on FPGA, the delay chain includes N-level cascaded delay units, wherein each level of delay unit includes an adjustable delay unit and a fixed delay unit; S2. Perform step delay calibration on the N-stage delay units through calibration signals. Specifically, compare the delay time of each stage delay unit with the theoretical delay time through the calibration signal. If it does not meet the preset tolerance, adjust the delay time of the adjustable delay unit of the corresponding stage until it meets the preset tolerance.
5. The method for verifying the high-precision measurement time interval of a step-by-step delay chain based on FPGA according to claim 4 is characterized in that: Step S2 specifically includes the following steps: a. Access the verification signal generated by the signal source; b. Set the delay chain level n to be checked. The initial level is 0. After checking the current delay unit, the set value is increased by 1. c. Set the adjustable delay time of the adjustable delay unit of the current delay unit, compare the delay time of the check signal through each delay unit with the theoretical delay time, and when it does not meet the tolerance standard, adjust the adjustable delay time according to the deviation; d. After adjustment, continue to determine whether the deviation between the measured delay time and the theoretical delay time meets the tolerance standard. If not, repeat steps c and d; if it meets the tolerance standard, record the adjustable delay time of the current delay unit and execute step e; e. Determine the delay chain level n of the current verification. If the delay chain level n is less than N, repeat steps b, c, d, and e; if the delay chain level n is N, the verification is completed and step f is executed; f. End verification and cache N-level adjustable delay time.
6. The method for verifying the high-precision time interval measurement of the step-by-step delay chain based on FPGA according to claim 5, characterized in that: Step d specifically uses a time interval counter to measure the time difference between the input verification signal and the output delay signal.
7. A method for high-precision time interval measurement based on FPGA step-by-step delay chain, characterized in that: The following steps are involved: Performing a delay chain calibration according to the calibration method of claim 4 or 5; In the test task, N-level latches are set for the N-level delay unit. When the latch signal arrives, the state value of the signal to be tested passing through the current N-level step-by-step delay chain is latched; The state values of the N-stage step-by-step delay chain are tapped, and then the time interval of the signal to be measured is calculated based on the delay time of the corresponding delay unit.