Sampling circuit

Abstract

The invention discloses a sampling circuit, which comprises a differential amplification circuit, a current suppression module and a voltage regulation module, the differential amplification circuit comprises a current source, an amplification module and a load module, the amplification module comprises a first end and a second end, the first end of the amplification module serves as an input end, and the second end of the amplification module serves as an output end; the voltage regulation module is connected with a first common connection end between the amplification module and the load module, and the voltage regulation module is also connected with a second end of the amplification module; the voltage adjusting module is used for adjusting the voltage of the second end of the amplification module to be matched with the voltage of the first end; the current suppression module is connected with a second common connection end between the amplification module and the load module, and the current suppression module is also connected with a current source; the current suppression module suppresses the current output by the second end of the amplification module in the process that the voltage of the second end of the amplification module is matched with the voltage value of the first end. The sampling circuit provided by the invention can enable the voltage of the output end to have relatively high holding precision.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a sampling circuit. Background Art

[0002] Sampling circuits are widely used in electronic devices and circuits, including charge detection, signal processing and other aspects. In order to improve the effectiveness of the sampling circuit, the output signal of the sampling circuit needs to maintain the minimum value of the input signal.

[0003] At present, in a sampling circuit, in order to make the output signal maintain the minimum value of the input signal, electronic devices such as transistors and capacitors are generally connected to the output end of the sampling circuit, and the output signal of the sampling circuit maintains the minimum value of the input signal through the charging and discharging process of the capacitor. However, when it is necessary to increase the output response speed of the sampling circuit, the output current of the sampling circuit increases, the capacitor is charged, and in the voltage holding stage, the capacitor discharges to increase the output voltage of the sampling circuit, resulting in a low holding accuracy of the output voltage of the sampling circuit. Summary of the invention

[0004] The present invention provides a sampling circuit to solve the problem of low maintaining accuracy of output voltage of the sampling circuit in the prior art.

[0005] According to one aspect of the present invention, a sampling circuit is provided, comprising: a differential amplifier circuit, a current suppression module and a voltage regulation module;

[0006] The differential amplifier circuit includes a current source, an amplifier module and a load module, wherein the amplifier module is connected between the current source and the load module; the amplifier module includes a first end and a second end, wherein the first end of the amplifier module serves as an input end, and the second end of the amplifier module serves as an output end;

[0007] The voltage regulating module is connected to a first common connection terminal between the amplifying module and the load module, and is also connected to a second terminal of the amplifying module; the voltage regulating module is used to adjust the voltage of the second terminal of the amplifying module to match the voltage of the first terminal;

[0008] The current suppression module is connected to the second common connection terminal between the amplification module and the load module, and the current suppression module is also connected to the current source; the current suppression module is used to match the voltage at the second end of the amplification module to the voltage value of the first end, thereby suppressing the current output from the second end of the amplification module.

[0009] Optionally, the current suppression module includes a first transistor, a control end of the first transistor is connected to the second common connection end, a first end of the first transistor is connected to the current source, and a second end of the first transistor is grounded.

[0010] Optionally, the current suppression module further includes a second transistor, a control end of the second transistor is connected to the control end of the first transistor, a first end of the second transistor is connected to the control end of the second transistor and the second common connection end, and a second end of the second transistor is grounded.

[0011] Optionally, the amplification module includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, the control end of the third transistor and the control end of the fourth transistor are connected to the first end of the amplification module, the control end of the fifth transistor and the control end of the sixth transistor are connected to the second end of the amplification module, the first end of the third transistor, the first end of the fourth transistor, the first end of the fifth transistor and the first end of the sixth transistor are connected to the current source, and the second end of the third transistor, the second end of the fourth transistor, the second end of the fifth transistor and the second end of the sixth transistor are connected to the load module.

[0012] Optionally, the load module includes a first current mirror and a second current mirror, the first current mirror is connected to the amplification module and the current suppression module, the first current mirror is used to control the conduction and shutdown of the current suppression module, the second current mirror is connected to the amplification module and the voltage regulation module, the second current mirror is used to control the conduction or shutdown of the voltage regulation module.

[0013] Optionally, the first current mirror includes a seventh transistor and an eighth transistor, the first end of the seventh transistor is connected to the second end of the fourth transistor, the second end of the seventh transistor is grounded, the control end of the seventh transistor is connected to the first end of the seventh transistor and the control end of the eighth transistor, the first end of the eighth transistor is connected to the second end of the fifth transistor, and the second end of the eighth transistor is grounded.

[0014] Optionally, the second current mirror includes a ninth transistor and a tenth transistor, the first end of the ninth transistor is connected to the second end of the third transistor, the second end of the ninth transistor is grounded, the control end of the ninth transistor is connected to the control end of the tenth transistor, the first end of the tenth transistor is connected to the control end of the tenth transistor and the second end of the sixth transistor, and the second end of the tenth transistor is grounded.

[0015] Optionally, the voltage regulating module includes an eleventh transistor and a first capacitor, the control end of the eleventh transistor is connected to the first common connection end, the first end of the eleventh transistor is connected to the second end of the amplification module, the second end of the eleventh transistor is grounded, the first end of the first capacitor is connected to the first end of the eleventh transistor, and the second end of the first capacitor is connected to the second end of the eleventh transistor.

[0016] Optionally, the sampling circuit further includes a power supply, the power supply is connected to the current source, and the power supply is used to provide power.

[0017] Optionally, the sampling circuit further includes a first switch, a first end of the first switch is connected to the power supply, a second end of the first switch is connected to the second end of the amplification module, and the first switch is used to reset the voltage at the second end of the amplification module.

[0018] The technical solution of the embodiment of the present invention provides a sampling circuit, including: a differential amplifier circuit, a current suppression module and a voltage regulation module. The differential amplifier circuit includes a current source, an amplifier module and a load module. The amplifier module includes a first end and a second end. The first end of the amplifier module is used as an input end, and the second end of the amplifier module is used as an output end. The voltage regulation module is used to adjust the voltage of the second end of the amplifier module to match the voltage of the first end. The current suppression module is connected to the second common connection end between the amplifier module and the load module. The current suppression module is also connected to the current source. Since the current suppression module suppresses the current output from the second end of the amplifier module during the process of matching the voltage of the second end of the amplifier module to the voltage value of the first end, the output end current of the sampling circuit is suppressed from increasing during the process of matching the output end voltage of the sampling circuit to the input end voltage, so that the output end voltage of the sampling circuit can be kept stable, the output end voltage maintenance accuracy is improved, and the problem of low output voltage maintenance accuracy of the sampling circuit in the prior art is solved.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a circuit diagram of a sampling circuit provided in the related art;

[0022] Figure 2 is a schematic diagram of a principle of a sampling circuit provided by an embodiment of the present invention;

[0023] Figure 3 is a structural schematic diagram of a sampling circuit provided by an embodiment of the present invention;

[0024] Figure 4 is a circuit diagram of a sampling circuit provided by an embodiment of the present invention;

[0025] Figure 5 is a circuit diagram of another sampling circuit provided by an embodiment of the present invention;

[0026] Figure 6 is a circuit diagram of another sampling circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] In a sampling circuit, in order to make the output signal maintain the minimum value of the input signal, electronic devices such as transistors and capacitors are generally connected to the output end of the sampling circuit. Through the charging and discharging process of the capacitor, the output signal of the sampling circuit can be maintained at the minimum value of the input signal. Figure 1 is a circuit diagram of a sampling circuit provided in the related art, such as Figure 1As shown, the sampling circuit includes an input terminal Vin and an output terminal Vout, and the input terminal Vin is connected to an adjustable power supply V1. When the switch S is closed, the capacitor C is charged by the power supply VCC, and the voltage of the output terminal Vout is equal to the voltage of the power supply VCC. The switch S is closed periodically, which is called a reset switch. When the switch S is open, the working state of the circuit is determined by the input terminal Vin. When the voltage of the input terminal Vin is smaller than the voltage of the power supply VCC, the collector current of the transistor QR1 increases. Since the base currents of the transistors QR3 and QR4 remain unchanged, the collector currents of the transistors QR3 and QR4 will not change. Therefore, the increased collector current of the transistor QR1 can only flow through the base of the transistor QR5, resulting in an increase in the collector current of the transistor QR5. At this time, the capacitor C is discharged through the loop formed by the capacitor C and the transistor QR5, and the voltage of the output terminal Vout decreases. When the voltage of the output terminal Vout drops to the same voltage as the input terminal Vin, the collector currents of the transistors QR1 and QR2 are equal, and the transistor QR1 will not have any excess current flowing to the base of the transistor QR5, causing the transistor QR5 to turn off and the discharge of the capacitor C to end. When the voltage of the input terminal Vin is greater than the voltage of the output terminal Vout, the collector current of the transistor QR1 decreases, and the transistor QR5 will always remain in a closed state, and the voltage of the output terminal Vout will not decrease. When the voltage at the output terminal Vout needs to have a faster response according to the voltage drop change at the input terminal Vin, in order to speed up the response speed, the bias current Ib of the current source I can only be increased, so that the collector current of the transistor QR1 and the transistor QR2 increases, and the voltage response speed of the output terminal Vout is achieved by accelerating the discharge speed of the capacitor C.

[0030] However, when the bias current Ib increases, the collector current of transistor QR2 will increase, and the collector current of transistor QR3 will also increase, causing transistor QR5 to close more quickly. Similarly, due to the increase in the collector current of transistor QR2, the base current of transistor QR2 increases. When the voltage at the output terminal Vout drops to be equal to the voltage at the input terminal Vin, the voltage at the output terminal Vout no longer drops, and the voltage at the output terminal Vout enters the voltage holding stage. At this time, due to the increase in the base current of transistor QR2, a larger current will flow through the base of transistor QR2 to capacitor C, and capacitor C will be charged. Therefore, the voltage at the output terminal Vout rises slowly, resulting in a decrease in the matching accuracy between the voltage at the output terminal Vout and the voltage at the input terminal Vin. The calculation formula for the base current Ib2 of transistor QR2 is as follows:

[0031] Ib2=Ib / 2 / β20

[0032] Among them, β20 is the amplification factor of transistor QR2. If transistors QR1 and QR2 are changed from PNP transistors to PMOS transistors, the above problems can be solved. However, the threshold voltage of the PMOS tube needs to be about 1V, which is larger than the threshold voltage of the transistor. The PMOS tube will sacrifice a certain voltage margin, so it is not suitable for low-voltage circuits. In addition, the process consistency of the MOS tube is worse than that of the transistor, and the amplification factor is not as high as that of the transistor, which will cause the stability of the switch control of the transistor QR5 to deteriorate, and will also affect the voltage matching accuracy between the output terminal Vout of the sampling circuit and the input terminal Vin.

[0033] In order to solve the above problems, an embodiment of the present invention provides a sampling circuit. Figure 2 is a schematic diagram of a sampling circuit provided by an embodiment of the present invention, such as Figure 2 As shown, Figure 2 is Figure 1 Based on the improvement, the collector of transistor QR2 is connected to the base of transistor QR10. When the collector current of transistor QR2 increases, that is, the base current of transistor QR10 increases, so the collector current of transistor QR10 will increase, so that the bias current Ib will pass through transistor QR10, sharing the collector current of transistor QR2, and the base of transistor QR2 is connected to the power supply VR. Transistor QR10 and transistor QR2 form a negative feedback circuit. Through this negative feedback mechanism, the increase of the collector current of transistor QR2 can be suppressed, thereby suppressing the increase of the base current of transistor QR2. It can ensure the accuracy of the voltage at the output end of the sampling circuit while improving the output voltage response speed.

[0034] Figure 3 is a schematic diagram of a sampling circuit provided by an embodiment of the present invention, such as Figure 3As shown, the sampling circuit includes a differential amplifier circuit 110, a current suppression module 120 and a voltage regulation module 130; the differential amplifier circuit 110 includes a current source I, an amplifier module 111 and a load module 112, the amplifier module 111 is connected between the current source I and the load module 112; the amplifier module 111 includes a first end and a second end, the first end of the amplifier module 111 is used as an input end Vin, and the second end of the amplifier module 111 is used as an output end Vout; the voltage regulation module 130 is connected between the amplifier module 111 and the load module 112 A common connection terminal a1, the voltage regulating module 130 is also connected to the second end of the amplifying module 111; the voltage regulating module 130 is used to adjust the voltage of the second end of the amplifying module 111 to match the voltage of the first end; the current suppression module 120 is connected to the second common connection terminal a2 between the amplifying module 111 and the load module 112, and the current suppression module 120 is also connected to the current source I; the current suppression module 120 is used to suppress the current output from the second end of the amplifying module 111 during the process of matching the voltage at the second end of the amplifying module 111 to the voltage value of the first end.

[0035] In this embodiment, the sampling circuit refers to a circuit that receives an input voltage at a certain specified time and maintains the voltage at the output end until the next sampling. The differential amplifier circuit 110 has the characteristics of symmetrical circuit parameters and is widely used in the input stage of the circuit. The current source I can provide a constant current, that is, the bias current provided by the current source I to the differential amplifier circuit 110 is constant. The amplifier module 111 is a module with an amplification function in the differential amplifier circuit 110. For example, the amplifier module 111 may include at least one pair of transistors with the same and symmetrical characteristics. The load module 112 is used as a load in the differential amplifier circuit 110. The load module 112 may include a resistor, a current mirror, etc., which is not limited. The current suppression module 120 is a module that suppresses the current at the second end of the amplifier module 111 (that is, the output end Vout of the sampling circuit). The voltage regulation module 130 is a module that regulates the voltage at the second end of the amplifier module 111.

[0036] Exemplarily, when the voltage at the input terminal Vin of the sampling circuit is less than the voltage at the output terminal Vout, the voltage regulating module 130 discharges, so that the voltage at the output terminal Vout begins to match the voltage at the input terminal Vin (i.e., the voltage at the output terminal Vout decreases). When the voltage at the output terminal Vout decreases to the same voltage as the voltage at the input terminal Vin, the voltage regulating module 130 stops discharging, and the voltage at the output terminal Vout is in a maintained state and stops decreasing. When the voltage at the output terminal Vout matches the voltage at the input terminal Vin by increasing the bias current, the voltage regulating module 130 has a faster discharge speed, and the time required for the voltage at the output terminal Vout to match the voltage at the input terminal Vin is shorter. At this time, the current at the second terminal of the amplification module 111 increases. Since the current suppression module 120 can suppress the increase in the current at the second terminal of the amplification module 111, the voltage fluctuation can be reduced when the voltage at the output terminal Vout is in a maintained state. If there is no current suppression module 120 to suppress the current at the second end of the amplifying module 111, when the current at the second end of the amplifying module 111 increases, the current at the second end of the amplifying module 111 charges the voltage regulating module 130. When the voltage at the output end Vout is in a holding state, the voltage regulating module 130 discharges to increase the voltage at the output end Vout, resulting in poor holding accuracy of the voltage at the output end Vout. Therefore, by providing the current suppression module 130, the sampling circuit can improve the voltage holding accuracy while improving the response speed.

[0037] The technical solution of this embodiment provides a sampling circuit, including: a differential amplifier circuit, a current suppression module and a voltage regulation module. The differential amplifier circuit includes a current source, an amplifier module and a load module. The amplifier module includes a first end and a second end. The first end of the amplifier module is used as an input end, and the second end of the amplifier module is used as an output end. The voltage regulation module is used to adjust the voltage of the second end of the amplifier module to match the voltage of the first end. The current suppression module is connected to the second common connection end between the amplifier module and the load module. The current suppression module is also connected to the current source. Since the current suppression module suppresses the current output from the second end of the amplifier module during the process of matching the voltage of the second end of the amplifier module to the voltage value of the first end, the output end current of the sampling circuit is suppressed from increasing during the process of matching the voltage of the output end of the sampling circuit to the voltage of the input end, so that the output end voltage of the sampling circuit can be kept stable, the output end voltage maintenance accuracy is improved, and the problem of low output voltage maintenance accuracy of the sampling circuit in the prior art is solved.

[0038] Figure 4 is a circuit diagram of a sampling circuit provided by an embodiment of the present invention, such as Figure 4As shown, the amplification module 111 includes a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5 and a sixth transistor Q6, the control end of the third transistor Q3 and the control end of the fourth transistor Q4 are connected to the first end of the amplification module 111, the control end of the fifth transistor Q5 and the control end of the sixth transistor Q6 are connected to the second end of the amplification module 111, the first end of the third transistor Q3, the first end of the fourth transistor Q4, the first end of the fifth transistor Q5 and the first end of the sixth transistor Q6 are connected to the current source I, and the second end of the third transistor Q3, the second end of the fourth transistor Q4, the second end of the fifth transistor Q5 and the second end of the sixth transistor Q6 are connected to the load module 112.

[0039] In this embodiment, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5 and the sixth transistor Q6 have the same structure and characteristics, and any one of the third transistor Q3 and the fourth transistor Q4 is symmetrically connected to any one of the fifth transistor Q5 and the sixth transistor Q6.

[0040] Continue to refer Figure 4 The load module 112 includes a first current mirror and a second current mirror. The first current mirror is connected to the amplification module 111 and the current suppression module 120. The first current mirror is used to control the on and off of the current suppression module 120. The second current mirror is connected to the amplification module 111 and the voltage regulation module 130. The second current mirror is used to control the on or off of the voltage regulation module 130. The first current mirror and the second current mirror can accurately copy the current without being affected by external environment such as temperature. Therefore, by using the current mirror as the load of the differential amplifier circuit, the problem of being easily affected by external environment when using a resistor as a load can be overcome.

[0041] Specifically, the first current mirror includes a seventh transistor Q7 and an eighth transistor Q8, wherein the first end of the seventh transistor Q7 is connected to the second end of the fourth transistor Q4, the second end of the seventh transistor Q7 is grounded, the control end of the seventh transistor Q7 is connected to the first end of the seventh transistor Q7 and the control end of the eighth transistor Q8, the first end of the eighth transistor Q8 is connected to the second end of the fifth transistor Q5, and the second end of the eighth transistor Q8 is grounded. The second current mirror includes a ninth transistor Q9 and a tenth transistor Q10, wherein the first end of the ninth transistor Q9 is connected to the second end of the third transistor Q3, the second end of the ninth transistor Q9 is grounded, the control end of the ninth transistor Q9 is connected to the control end of the tenth transistor Q10, the first end of the tenth transistor Q10 is connected to the control end of the tenth transistor Q10 and the second end of the sixth transistor Q6, and the second end of the tenth transistor Q10 is grounded.

[0042] In this embodiment, when the voltage at the input terminal Vin of the sampling circuit is less than the voltage at the output terminal Vout, the currents of the third transistor Q3 and the fourth transistor Q4 are greater than the currents of the fifth transistor Q5 and the sixth transistor Q6, the currents of the ninth transistor Q9 and the tenth transistor Q10 in the second current mirror are smaller, the second current mirror controls the voltage regulating module 130 to be turned on, the voltage regulating module 130 is discharged, the voltage at the output terminal Vout begins to drop, when the voltage at the output terminal Vout begins to drop, the currents of the seventh transistor Q7 and the eighth transistor Q8 in the first current mirror are larger, and the first current mirror controls the current suppression module 120 to be turned off. When the voltage at the output terminal Vout drops to the same voltage as the input terminal Vin, the currents of the third transistor Q3 and the fourth transistor Q4 decrease, the currents of the fifth transistor Q5 and the sixth transistor Q6 increase, the currents of the ninth transistor Q9 and the tenth transistor Q10 in the second current mirror increase, the second current mirror controls the voltage regulating module 130 to be turned off, the voltage at the output terminal Vout no longer drops, and is in a holding state. As the currents of the third transistor Q3 and the fourth transistor Q4 decrease, the currents of the seventh transistor Q7 and the eighth transistor Q8 in the first current mirror decrease accordingly, and the first current mirror controls the current suppression module 120 to be turned on.

[0043] Continue to refer Figure 4 The voltage regulating module 130 includes an eleventh transistor Q11 and a first capacitor C1, the control end of the eleventh transistor Q11 is connected to the first common connection end a1, the first end of the eleventh transistor Q11 is connected to the second end of the amplification module 111, the second end of the eleventh transistor Q11 is grounded, the first end of the first capacitor C1 is connected to the first end of the eleventh transistor Q11, and the second end of the first capacitor C1 is connected to the second end of the eleventh transistor Q11.

[0044] In this embodiment, when the voltage regulating module 130 is turned on, the eleventh transistor Q11 is turned on, the first capacitor C1 and the eleventh transistor Q11 form a loop, and the first capacitor C1 discharges through the loop formed by the first capacitor C1 and the eleventh transistor Q11, so that the voltage of the output terminal Vout decreases.

[0045] Continue to refer Figure 4 The current suppression module 120 includes a first transistor Q1, a control end of the first transistor Q1 is connected to the second common connection end a2, a first end of the first transistor Q1 is connected to the current source I, and a second end of the first transistor Q1 is grounded.

[0046] In this embodiment, when the current suppression module 120 is turned off, the first transistor Q1 is turned off, and when the current suppression module 120 is turned on, the first transistor Q1 is turned on. In the process of the voltage of the output terminal Vout decreasing, due to the decrease in the current of the third transistor Q3 and the fourth transistor Q4, the current of the seventh transistor Q7 and the eighth transistor Q8 in the first current mirror decreases accordingly, and part of the current of the fifth transistor Q5 and the sixth transistor Q6 will flow into the control end of the first transistor Q1. At this time, the current of the first transistor Q1 increases, and the bias current generated by the current source I flows into the first transistor Q1. The first transistor Q1 shares the current of the bias current flowing into the fifth transistor Q5 and the sixth transistor Q6. The first transistor Q1 and the fifth transistor Q5 (or the sixth transistor Q6) form a negative feedback circuit, and the increase of the current at the second end of the amplification module 111 is suppressed by this negative feedback mechanism. When the output voltage response speed needs to be increased, the current at the second end of the amplifying module 111 is suppressed and increased, and the current at the second end of the amplifying module 111 will no longer charge the first capacitor C1, and when the voltage at the output terminal Vout is in a maintained state, the voltage at the output terminal Vout will no longer be disturbed by the discharge of the first capacitor C1. At the same time, the output voltage response speed and the holding accuracy of the output terminal Vout voltage are improved.

[0047] Exemplarily, the current at the second end (i.e., the collector) of the fifth transistor Q5 is represented by Ic5, the current at the first end (i.e., the collector) of the first transistor Q1 is represented by Ic1, and the current at the control end (i.e., the base) of the first transistor Q1 is represented by Ib1. It can be obtained that Ic1=β1Ib1≈β1Ic5, where β1 is the amplification factor of the first transistor Q1. The current at the second end (i.e., collector) of the fifth transistor Q5 is equal to the current at the second end of the sixth transistor Q6. The current at the second end of the sixth transistor Q6 is represented by Ic6, and the bias current provided by the current source I is represented by Ib. It can be obtained that Ib / 2≥Ic6+Ic5+Ic1=β6Ib6+Ic5+β1Ic5=β6Ib6+(β1+1)β5Ib5, wherein β6 is the amplification factor of the sixth transistor Q6, Ib6 is the current at the control end (i.e., base) of the sixth transistor Q6, β5 is the amplification factor of the fifth transistor Q5, and Ib5 is the current at the control end (i.e., base) of the fifth transistor Q5. Finally, it can be obtained that Ib / 2≥β5(β1+2)Ib5, and it is calculated that Ib5≤Ib / 2 / (β5(β1+2))≈Ib / 2 / (β5β1). Since the collector current Ic5 of the fifth transistor Q5 is equal to the collector current Ic6 of the sixth transistor Q6, the base current Ib5 of the fifth transistor Q5 is equal to the base current Ib6 of the sixth transistor Q6. The current charged by the second end of the amplifier module 111 (i.e., the base of the fifth transistor Q5 and the sixth transistor Q6) for the first capacitor C1 is represented by Icap, and it can be obtained that Icap≈Ib / (β5β1), compared with the charging current Ib2=Ib / 2 / β20 in the above-mentioned related art, where Icap and Ib2 both represent the charging current of the capacitor, β5=β20, and it can be obtained that Ib2 / Icap=1 / (2 / β1). Compared with the circuit in the above-mentioned related art, the differential amplifier circuit in this embodiment adds the fourth transistor Q4, the fifth transistor Q5, the seventh transistor Q7 and the eighth transistor Q8, which results in a smaller driving capability of the eleventh transistor Q11, thereby slowing down the response speed of the sampling circuit. In order to improve the response speed of the output voltage, the bias current Ib should be doubled. Therefore, in fact, Ib2 / Icap=1 / (4 / β1). If the amplification factor β1 of the first transistor Q1 is 120, in the holding phase of the output terminal Vout voltage, the charging current of the first capacitor C1 from the second terminal of the amplification module 111 is about 1 / 30 of the charging current in the above-mentioned related art. Therefore, under the premise of ensuring the response speed, the sampling circuit can achieve a higher voltage holding accuracy.

[0048] Figure 5 is a circuit diagram of another sampling circuit provided by an embodiment of the present invention, such as Figure 5As shown, the current suppression module 120 also includes a second transistor Q2, whose control end is connected to the control end of the first transistor Q1, whose first end is connected to the control end of the second transistor Q2 and the second common connection end a2, and whose second end is grounded.

[0049] In this embodiment, the second transistor Q2 and the first transistor Q1 form a current mirror, and the gain of the negative feedback circuit composed of the fifth transistor Q5 and the first transistor Q1 can be controlled by adjusting the size ratio of the first transistor Q1 and the second transistor Q2 to enhance the stability of the circuit. For example, the larger the size ratio of the first transistor Q1 and the second transistor Q2, the greater the gain of the negative feedback circuit, and the better the stability of the circuit. At the same time, by adding the second transistor Q2, it is also possible to prevent the voltage of the first end (i.e., the emitter) of the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 in the amplification module 111 from being too low to be turned on when the first transistor Q1 is turned on. Reference Figure 4 and Figure 5 The first transistor Q1 can adopt a Darlington connection, which is not limited. Since the Darlington connection is a combination of two transistors in series, the current amplification factor is the product of the amplification factors of the two transistors. Therefore, by adopting the Darlington connection, the charging current of the first capacitor C1 at the second end of the amplification module 111 can be further reduced, thereby improving the voltage holding accuracy of the sampling circuit.

[0050] Figure 6 is a circuit diagram of another sampling circuit provided by an embodiment of the present invention, such as Figure 6 As shown, the sampling circuit also includes a power supply VCC and a first switch S1. The power supply VCC is connected to the current source I. The power supply VCC is used to provide power. The first end of the first switch S1 is connected to the power supply VCC, and the second end of the first switch S1 is connected to the second end of the amplification module 111. The first switch S1 is used to reset the voltage of the second end of the amplification module 111.

[0051] In this embodiment, the input terminal Vin is connected to the adjustable power supply V1, and the sampling circuit can sample the voltage of the preset time period according to the demand. Exemplarily, when the first switch S1 is open, the sampling circuit samples the voltage output by the adjustable power supply V1 through the input terminal Vin. When the first switch S1 is closed, the output terminal Vout of the sampling circuit is connected to the power supply VCC, and the output terminal Vout of the sampling circuit is reset. During the sampling process of the sampling circuit, the voltage of the output terminal Vout can maintain the minimum value of the voltage of the input terminal Vin. When the response speed of the output voltage is increased by increasing the bias current, the current suppression module improves the voltage holding accuracy of the output terminal Vout by suppressing the increase of the current at the second output terminal of the amplification module. The sampling circuit provided in this embodiment not only ensures the response speed of the output voltage, but also improves the voltage holding accuracy of the sampling circuit.

[0052] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0053] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A sampling circuit, It is characterized in that include: Differential amplifier circuit, current suppression module and voltage regulation module; The differential amplifier circuit comprises a current source, an amplifier module and a load module, wherein the amplifier module is connected between the current source and the load module; the amplifier module comprises a first end and a second end, wherein the first end of the amplifier module serves as an input end, and the second end of the differential amplifier serves as an output end; The voltage regulating module is connected to a first common connection terminal between the amplifying module and the load module, and is also connected to a second terminal of the amplifying module; the voltage regulating module is used to adjust the voltage of the second terminal of the amplifying module to match the voltage of the first terminal; The current suppression module is connected to the second common connection terminal between the amplification module and the load module, and the current suppression module is also connected to the current source; the current suppression module is used to match the voltage at the second end of the amplification module to the voltage value of the first end, thereby suppressing the current output from the second end of the amplification module.

2. The sampling circuit according to claim 1, It is characterized in that The current suppression module comprises a third transistor, a control end of the third transistor is connected to the second common connection end, a first end of the third transistor is connected to the current source, and a second end of the third transistor is grounded.

3. The sampling circuit according to claim 2, It is characterized in that The current suppression module further includes a fourth transistor, a control end of the fourth transistor is connected to the control end of the third transistor, a first end of the fourth transistor is connected to the control end of the fourth transistor and the second common connection end, and a second end of the fourth transistor is grounded.

4. The sampling circuit according to claim 1, It is characterized in that The amplification module includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, the control end of the third transistor and the control end of the fourth transistor are connected to the first end of the amplification module, the control end of the fifth transistor and the control end of the sixth transistor are connected to the second end of the amplification module, the first end of the third transistor, the first end of the fourth transistor, the first end of the fifth transistor and the first end of the sixth transistor are connected to the current source, and the second end of the third transistor, the second end of the fourth transistor, the second end of the fifth transistor and the second end of the sixth transistor are connected to the load module.

5. The sampling circuit according to claim 4, It is characterized in that The load module includes a first current mirror and a second current mirror, the first current mirror is connected to the amplification module and the current suppression module, the first current mirror is used to control the conduction and shutdown of the current suppression module, the second current mirror is connected to the amplification module and the voltage regulation module, the second current mirror is used to control the conduction or shutdown of the voltage regulation module.

6. The sampling circuit according to claim 5, It is characterized in that The first current mirror includes a seventh transistor and an eighth transistor, the first end of the seventh transistor is connected to the second end of the fourth transistor, the second end of the seventh transistor is grounded, the control end of the seventh transistor is connected to the first end of the seventh transistor and the control end of the eighth transistor, the first end of the eighth transistor is connected to the second end of the fifth transistor, and the second end of the eighth transistor is grounded.

7. The sampling circuit according to claim 5, It is characterized in that The second current mirror includes a ninth transistor and a tenth transistor, the first end of the ninth transistor is connected to the second end of the third transistor, the second end of the ninth transistor is grounded, the control end of the ninth transistor is connected to the control end of the tenth transistor, the first end of the tenth transistor is connected to the control end of the tenth transistor and the second end of the sixth transistor, and the second end of the tenth transistor is grounded.

8. The sampling circuit according to claim 1, It is characterized in that The voltage regulating module includes an eleventh transistor and a first capacitor, the control end of the eleventh transistor is connected to the first common connection end, the first end of the eleventh transistor is connected to the second end of the amplification module, the second end of the eleventh transistor is grounded, the first end of the first capacitor is connected to the first end of the eleventh transistor, and the second end of the first capacitor is connected to the second end of the eleventh transistor.

9. The sampling circuit according to claim 1, It is characterized in that It also includes a power supply, which is connected to the current source and is used to provide power.

10. The sampling circuit according to claim 9, It is characterized in that It also includes a first switch, a first end of the first switch is connected to the power supply, a second end of the first switch is connected to the second end of the amplifying module, and the first switch is used to reset the voltage of the second end of the amplifying module.

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