Latch-free fail-safe and fault tolerant input / output interface

Abstract

The invention relates to a latch-free fail-safe and fault tolerant input / output interface. An input / output (I / O) interface includes a set of complementary metal oxide semiconductor (CMOS) transistors in a P-type substrate. A first N-type region is in a substrate, a second N-type region is in the substrate, spaced apart from the first N-type region, and the second N-type region is a deep-N well (DNW). The first heavily doped P-type region is arranged between the first N-type region and the second N-type region, and the first heavily doped P-type region is coupled to the ground. A second heavily doped P-type region is in the first N-type region, the second heavily doped P-type region coupled to the output terminal. A first heavily doped N-type region is in the first N-type region, the first heavily doped N-type region coupled to a floating well (FW) terminal. A second heavily doped N-type region is in the second N-type region. A resistor is coupled to the DNW, and the resistor is coupled to the voltage source terminal.

Description

Technical Field

[0001] The present disclosure relates to a latchup-free fail-safe and fault-tolerant input / output (I / O) interface based on a complementary metal oxide semiconductor (CMOS) topology. Background Art

[0002] Scaling down the scale of integrated circuits (ICs) is required for low-cost and low-power applications. Therefore, reducing the size of devices in ICs is a typical way to scale down the scale of ICs. Generally, smaller devices are designed to work at lower voltages. However, some ICs used as interface circuits, such as input / output (I / O) buffers, are coupled to external circuit components that can work at different voltage levels. For example, the interface circuit can work with 3.3V technology, while the external circuit works with 5V technology. The I / O interface is implemented based on a complementary metal oxide semiconductor (CMOS) layout, which includes some parasitic elements in operation. Parasitic elements may cause latches in the CMOS layout, which damage or reduce the efficiency of the IC. Latching is a short circuit or low impedance path between a high voltage level (e.g., coupled to a voltage source) and a low voltage level (e.g., coupled to ground), which causes undesirable current flow in the IC.

[0003] In CMOS layout, latch-up can be generated by parasitic elements between adjacent negative (N-type) or positive (P-type) regions. Latch-up causes current leakage between adjacent regions. One way to reduce latch-up in CMOS layout is to increase the distance between adjacent regions. However, this approach increases the area of ​​the IC, thereby increasing the manufacturing cost. Summary of the invention

[0004] The present disclosure relates to an input / output (I / O) interface implemented based on a complementary metal oxide semiconductor (CMOS) layout, which covers a smaller area than a conventional design. The I / O interface sends and receives data signals to an external circuit. In various embodiments of the present disclosure, the I / O interface sends data signals to an external circuit coupled to a PAD contact through an output driver. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes at least one PMOS coupled between a first voltage source and a pad (PAD). The pull-down driver includes at least one NMOS (hereinafter PMOS and NMOS refer to P-type and N-type metal oxide semiconductor field effect transistors (MOSFETs)) coupled between the pad and a ground node or a second voltage source having a voltage lower than the first voltage source. In an embodiment of the CMOS IO driver layout, the PMOS is formed in an N-type well (N-well) region, and the NMOS is formed in a deep N-well (DNW) region that is laterally spaced apart from the N-well region. This is a standard way to eliminate parasitic SCR paths. By manufacturing in this way, the SCR that was previously to be formed between the PNP of the PMOS and the NPN of the NMOS is blocked by the DNW. By using this layout, a new SCR is formed between the PNP of the PMOS and the DNW used to isolate the NMOS device. In non-fail-safe or non-tolerant IO, the newly formed SCR is inoperative, but in the fail-safe and fail-tolerant operation modes of the I / O interface, this new layout configuration is a potential latch-up prone structure.

[0005] This new SCR circuit includes a parasitic NPN BJT having an emitter terminal formed by a DNW region. In addition, an equivalent SCR circuit includes a parasitic PNP BJT having an emitter and a base terminal formed in an N-well region. When the emitter of the parasitic NP-NBJT is coupled to a zero-volt power supply or a ground node, a latch may be generated. Latching causes current to flow from a first voltage source or pad to a zero-volt power supply or a ground node. In the present disclosure, a resistor is coupled to the emitter terminal of the parasitic NPN BJT to limit the current flow in the equivalent SCR circuit. The addition of the resistor reduces the gain of the parasitic NPN BJT and disconnects the loop generated by the parasitic NPN BJT and the PNP BJT. The resistor is implemented as an on-chip resistor connected to the DNW region. The second terminal of the resistor is connected to a power supply. The resistor frees the I / O interface from latching without increasing the distance between the N-well region and the DNW region, but can reduce the distance between the N-well region and the DNW region. This can reduce silicon area, or can allow the saved space to be utilized by other components of the final device.Thus, the area of ​​the CMOS layout is kept to the smallest possible size, regardless of latch-up effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that the various features are not drawn to scale.

[0007] Figure 1A is a topology of a transmitting circuit according to some embodiments.

[0008] Figure 1B is a topology of a circuit according to the present disclosure.

[0009] Figure 2 This disclosure Figure 1B Schematic circuit of the .

[0010] Figure 3A-3B yes Figure 1B and Figure 2 Cross-sectional diagram of a MOS configuration.

[0011] Figure 4 yes Figure 1B and Figure 2 A top view of the circuit.

[0012] Figure 5 is a flow chart of a method of the present disclosure.

[0013] Figure 6 is a cross-sectional view of a diode configuration of the present disclosure.

[0014] Figure 7 yes Figure 6 Top view of the diode configuration. DETAILED DESCRIPTION

[0015] Figure 1A It is a conventional topology of the transmitting circuit 100. The transmitting circuit 100 includes two MOSFETs coupled to output contacts (pads). Each of the two MOSFETs can drive the output contacts by a control signal. The MOSFET is coupled to an input / output (I / O) domain voltage source (VDDE). The operating voltage of VDDE can be compatible with the operating technology of the MOSFET (e.g., 1.8V, 3.3V, 5V, etc.). Under the conditions of fail-safe and fault-tolerant, the output contacts can operate under two conditions. The IO buffer power supply can be zero, the pad is driven to the buffer power supply voltage or higher by the external chip, or the IO buffer power supply still exists but the pad can be coupled to a high voltage level with a voltage higher than the operating voltage of the IO buffer.

[0016] Circuit 100 includes a first transistor 102 coupled to a voltage source 108 and an output contact (pad) 106, and a second transistor 104 coupled to the output contact (pad) 106 and a reference node 110. In various embodiments, reference node 110 is coupled to electrical ground. In various embodiments, first and second transistors 102, 104 are MOSFETs. First transistor 102 is a PMOS and second transistor 104 is an NMOS. A first control signal PD 112 is applied to a gate terminal of PMOS 102. A second control signal ND 114 is applied to a gate terminal of NMOS 104. A body terminal of transistor 104 is coupled to ground 110, and a body terminal of transistor 102 is coupled to a voltage FW 115. Voltage FW 115 may be a maximum voltage between voltage source 108 and pad 106.

[0017] In some embodiments, the voltage source 108 is an I / O domain voltage source (VDDE). The voltage of the voltage source 108 may correspond to the operation technology of the PMOS 102 and the NMOS 104.

[0018] Figure 1B The invention discloses a circuit 100 for use as a fail-safe, fault-tolerant input / output (IO) interface. The circuit includes a floating n-well (described in more detail below) that generates a latching configuration in use. In order to increase the latching robustness of such an IO, conventional designs increase the physical spacing or distance between the floating n-well and (one or more) other n-wells in the semiconductor substrate (where these components are formed). The spacing helps reduce the gain of the parasitic bipolar junction transistor formed in the equivalent silicon-controlled rectifier (SCR) circuit. The spacing value or distance depends on the maximum voltage difference between the floating n-well and the adjacent n-well. In one example, the distance can be from 6 to 30 microns (μm). Increasing the spacing to avoid latching increases the base region of the lateral parasitic NPN and reduces the gain. The size of the base region depends on the voltage difference (Vac) between the anode and cathode of the parasitic SCR. A larger voltage difference Vac results in a larger spacing of the base region. The spacing typically includes several ground loops (such as greater than 3 or 4) formed between the n-well and the adjacent deep n-well.

[0019] This means that there is more spacing between the geometric features that make up the SCR. For a fail-safe or fail-tolerant IO, the IO pad 106 can be driven to a high voltage by an external chip, so the body terminal of the PMOS also follows the pad, while all other N-wells are at zero voltage or a voltage lower than the pad. These IOs are more susceptible to latch-up, and by increasing the base width of the parasitic bipolar transistor, the layout can be made more robust to latch-up.

[0020] Figure 1BThe first PMOS transistor 102 is coupled to VDDE 108 and the gate is coupled to the first control signal PD 112. The first PMOS transistor 102 is coupled between the pad 106 and VDDE 108. The second NMOS transistor 104 is coupled between the pad 106 and the ground 110. In use, a first parasitic bipolar junction transistor (BJT) 130 and a second BJT 132 are formed in the substrate 400. For ease of understanding, Figure 1B , Figure 2 and Figure 3A-3B are described together. Figure 3A As can be seen in FIG. 4 , substrate 400 is a p-type substrate. A first n-well 402 is adjacent to a second deep n-well (DNW) 404. A p-well 406 is formed in DNW 404. A first PMOS transistor 102 is formed in first n-well 402. A second NMOS transistor 104 is formed in DNW 404. Figure 3A-3B The embodiments in the embodiment relate to a metal oxide semiconductor (MOS) configuration. Subsequently, embodiments involving a diode configuration are described.

[0021] To avoid leakage currents in fail-safe and fail-tolerant IOs, the first n-well 402 of the PMOS transistor 102 is not connected to the power supply. It is dynamically switched between the power supply and the pad 106 by a MOS switch. The higher voltage between the pad and the power supply is connected to the first n-well 402 (called a floating well or FW) through a MOS switch. Similarly, the ESD P diode (connected between the pad and the power supply) is removed and some other ESD protection device is used with respect to ground, or in the case where the power supply is lower than the pad, the first n-well is connected to another ESD rail (called a floating rail) following the pad 106.

[0022] In a fail-safe or fail-tolerant situation, there will be some first n-wells in the layout whose potential is controlled by pad 106, while there will be other n-wells (which constitute devices that are not part of the IO driver or ESD strategy (e.g., level shifters whose bulk is connected to the power supply)) that are at zero voltage or below the voltage of the pad. This creates a potential latch-up configuration within the IO interface.

[0023] The first PMOS transistor 102 includes a plurality of heavily doped P regions 408, 410. The N-well (Nwell) is biased using heavily doped N regions 412, all of which are included in the first N-well 402. The source / drain region of the first PMOS transistor 102 is coupled to a first heavily doped P region 408 of the plurality of heavily doped P regions. The pad 106 is coupled to a second heavily doped P region 410 of the plurality of heavily doped P regions. The voltage FW 115 is coupled to a third heavily doped N region 412 of the plurality of heavily doped N regions in the N-well 402.

[0024] The ground 110 is coupled to a heavily doped P region 414 formed in the substrate 400 in a region 416 between the first n-well 402 and the DNW 404. The region 416 is significantly reduced in the present disclosure by including a resistor 418 (REMITTER). The resistor 418 is coupled to a first heavily doped N region 420 of a plurality of heavily doped N regions formed in the DNW 404. A second heavily doped N region 422 of the plurality of heavily doped N regions is separated from the first heavily doped N region of the plurality of heavily doped N regions by the p-well 406 in the cross-sectional view. Figure 4 It can be seen that the first heavily doped N region and the second heavily doped N region 420 and 422 are part of a ring or n-well surrounding the p-well 406 .

[0025] The third heavily doped N region 424 and the fourth heavily doped N region 426 of the plurality of heavily doped N regions are formed in the p-well 406 in the DNW 404. Figure 4 It can be seen that they are two parallel or substantially parallel doped regions in the p-well. The third and fourth heavily doped N regions 424 , 426 are coupled to the source / drain regions of the second NMOS transistor 104 .

[0026] As can be seen in FIG. 3 , the terminals of the PMOS and NMOS transistors are formed in heavily doped N-type and P-type regions, which in operation form the emitter, collector and base terminals of the parasitic NPN BJT and PNP BJT (BJT 130 and BJT 132), respectively. The inclusion of R emitter 418 allows for this significant reduction in the total area used by the circuit. In particular, Figure 3B The distance d1 in is less than the dimension d2. In one embodiment, only a single ground line, P+ region 414, may be formed or required between n-well 402 and DNW 404. This significantly reduces size compared to previous designs that required multiple ground lines to create enough space to manage latching between DNW and n-well 402.

[0027] Figure 4 4 is a top view of a silicon substrate 400 having multiple doped regions. The substrate 400 includes a P-type dopant. A first n-well 402 is formed in the substrate. A first heavily doped region 408 and a second heavily doped region 410 are in the first n-well 402. The first heavily doped region and the second heavily doped region 408, 410 have a longest dimension in a first direction. The first heavily doped region and the second heavily doped region 408, 410 are substantially parallel to each other. A first heavily doped N+ region 412 is also formed in the first N-well 402. The first heavily doped N+ region 412 has a longest dimension in the first direction and is substantially parallel to the first heavily doped P+ region and the second heavily doped P+ region 408, 410.

[0028] Another heavily doped P+ region 414 is formed in the substrate adjacent to the n-well 402. The heavily doped P+ region 414 is formed in a region 416 between the n-well 402 and the DNW 404.

[0029] The present disclosure aims to eliminate or substantially reduce the latch-up problem without wasting area for isolating the NPN base region. The present disclosure works only when only DNW is used to isolate the p-substrate, resistors, capacitors and ESD N-diodes of the NMOS device. There should not be any P+ / NWELL (N-well) junction inside it. The present disclosure is to isolate the NPN base region by a DNW called R 发射极 A resistor (with a value in kilo-ohms) connects the DNW isolating the p-substrate to VDDE. In other words, the solution can be used for any device with a DNW inside. The constraint is that there should be no p+ / nwell junction inside this DNW. The DNW is the emitter side of a parasitic npn. Therefore, the resistor connected to this DNW acts as R 发射极 , which reduces the current gain of the npn.

[0030] By including this resistor R 发射极 , which can significantly save area. It can be imagined that R 发射极 will be formed on the outside of the ground ring 110 . Figure 4 The ground ring 110 in the DNW 404 may be formed completely around the DNW 404. The ground ring 110 may also extend completely around the n-well 402. In an alternative embodiment, the R may be formed within the DNW. 发射极 .

[0031] Resistor R 发射极 The design can be done using the smallest polysilicon resistors. 发射极 should not be diffusion type or well resistors. 发射极 In the case of , the dimension d1 between the DNW 404 and the n-well 402 may be within the range of 3.3 to 7 microns (inclusive). These dimensions are only provided as an example, and various dimensions may be implemented.

[0032] The present disclosure relates to a device including a set of complementary metal oxide semiconductor (CMOS) transistors, which includes a P-type substrate, a first N-type region in the substrate, a second N-type region in the substrate spaced apart from the first N-type region, and the second N-type region is a deep-N well (DNW). A first heavily doped P-type region is between the first N-type region and the second N-type region, and the first heavily doped P-type region is coupled to ground. The second heavily doped P-type region is in the first N-type region, and the second heavily doped P-type region is coupled to an output terminal. The first heavily doped N-type region is in the first N-type region, and the first heavily doped N-type region is coupled to a floating well (FW) terminal. The second heavily doped N-type region is in the second N-type region and a resistor is coupled to the DNW, and the resistor is coupled to a voltage source terminal.

[0033] The resistor is coupled to an emitter terminal of a first parasitic bipolar junction transistor (BJT). The first BJT is an NP-NBJT, the DNW serves as an emitter terminal of the first parasitic BJT, and the first heavily doped N-type region serves as a collector terminal of the first parasitic BJT. The second parasitic BJT is coupled to the first parasitic BJT, the second parasitic BJT is a PNP BJT, and the base terminal of the second parasitic BJT is coupled to the collector terminal of the first parasitic BJT. The emitter terminal of the second parasitic BJT is coupled to the second heavily doped P-type region.

[0034] The combination of the first parasitic BJT and the second parasitic BJT is equivalent to a silicon controlled rectifier (SCR), and the SCR is a latch circuit of the group of CMOS transistors. The group of CMOS transistors serves as an input / output (I / O) interface operating in a fail-safe or fail-tolerant mode. The resistor is an on-chip resistor coupled to the DNW. The resistor reduces the gain of the first parasitic BJT and limits the current flowing from the collector terminal of the first parasitic BJT to the emitter terminal.

[0035] A method includes: forming a fail-safe input / output (I / O) on a complementary metal oxide semiconductor (CMOS) layout by coupling an I / O interface to an output terminal. Forming the fail-safe I / O includes coupling a PMOS to the output terminal, the PMOS formed in a P-type substrate of the CMOS layout, the PMOS including a first heavily doped N-type region and a first heavily doped P-type region in a first N-type region, the first heavily doped N-type region coupled to a floating well (FW) terminal, and the first heavily doped P-type region coupled to the output terminal. Coupling an NMOS to the output terminal, the NMOS formed in a P-type substrate, the NMOS including a second heavily doped N-type region in a second N-type region and a second heavily doped P-type region in the P-type substrate, the second heavily doped P-type region coupled to ground, the second N-type region being laterally spaced a distance from the first N-type region. Coupling a resistor to the second heavily doped N-type region, the resistor coupling a voltage source to the second N-type region, the coupling resistor reducing current leakage to a parasitic latch circuit.

[0036] The method includes: the second N-type region is a deep-N well (DNW). The parasitic latch circuit has a parasitic bipolar junction transistor (BJT), and the resistor is coupled to an emitter terminal of one of the parasitic BJTs. The distance has a threshold value, which is determined to limit current leakage of the parasitic latch circuit. The resistor makes the distance less than the threshold value.

[0037] A method includes: forming a complementary metal oxide semiconductor (CMOS) layout with an area threshold, the threshold being determined based on a voltage difference between a pad and a power supply (anode-cathode voltage of an SCR, Vac), the forming of the CMOS layout including: forming a deep N-well (DNW) region in a P-type substrate; forming an N-well region in the substrate, the N-well region being laterally spaced apart from the DNW region by a certain distance; forming a first heavily doped P-type region in the N-well region, the first heavily doped P-type region being coupled to an output terminal; forming a second heavily doped P-type region between the N-well region and the DNW region, the second heavily doped P-type region being coupled to a ground; forming a heavily doped N-type region in the N-well region, the heavily doped N-type region being coupled to a floating well (FW) terminal, the DNW region, the first heavily doped P-type region, the second heavily doped P-type region, and the heavily doped N-type region forming a parasitic latch circuit; and forming a resistor on the DNW region, the resistor being coupled between the DNW region and a voltage source, the resistor limiting current leakage of the parasitic latch circuit, and in response thereto, the area of ​​the CMOS layout is reduced to a value less than the threshold.

[0038] The distance is determined between the right edge of the DNW and the left edge of the N-well region along the first direction, and the distance is less than the size of the N-well in the first direction. The distance is less than a threshold value, which is between about 30 μm (may be in the range of 18 to 30 μm), and the distance may be between 3 and 7 μm. The aforementioned threshold value may be between 700 and 800 μm. 2 The area value is between 100 and 200 μm 2 between.

[0039] Figure 6 and Figure 7 6 is a cross-sectional view and a top view of a diode configuration of the present disclosure. The diode configuration 600 can be formed to have similar features to a MOS configuration. The same features will be described with the same reference numerals. In the diode configuration, a p-type substrate 400 includes a first n-well 402, and the first n-well 402 is adjacent to a second deep n-well (DNW) 404. A p-well 406 is formed in the DNW 404. A first PMOS transistor 602 is formed in the first n-well 402. A diode 604 is formed in the DNW 404.

[0040] The first PMOS transistor 602 includes a plurality of heavily doped P regions 408, 410. The N-well is biased using heavily doped N regions 412, all of which are included in the first N-well 402. The source / drain region of the first PMOS transistor 602 is coupled to a first heavily doped P region 408 of the plurality of heavily doped P regions. The pad 106 is coupled to a second heavily doped P region 410 of the plurality of heavily doped P regions. The voltage FW 115 is coupled to a third heavily doped N region 412 of the plurality of heavily doped N regions in the N-well 402.

[0041] The ground 110 is coupled to a heavily doped P region 414 formed in the substrate 400 in a region 416 between the first n-well 402 and the DNW 404. The region 616 between the transistor and the diode is significantly reduced in the present disclosure by including a resistor 418 (R emitter). The resistor 418 is coupled to a first heavily doped N region 420 of a plurality of heavily doped N regions formed in the DNW 404. A second heavily doped N region 422 of the plurality of heavily doped N regions is separated from the first heavily doped N region of the plurality of heavily doped N regions by the p-well 406 in the cross-sectional view. As shown in FIG. Figure 7 It can be seen that the first and second heavily doped N regions 420 and 422 are part of a ring or n-well surrounding the p-well 406 .

[0042] A third heavily doped N region 426 of the plurality of heavily doped N regions is formed in the p-well 406 in the DNW 404. The p-well 406 includes a p+ (heavily doped P) region 625 adjacent to the n+ region 426.

[0043] Figure 7 4 is a top view of a silicon substrate 400 having multiple doped regions. The substrate 400 includes a P-type dopant. A first n-well 402 is formed in the substrate. A first heavily doped region 408 and a second heavily doped region 410 are in the first n-well 402. The first and second heavily doped regions 408, 410 have a longest dimension in a first direction. The first and second heavily doped regions 408, 410 are substantially parallel to each other. A first heavily doped N+ region 412 is also formed in the first N-well 402. The first heavily doped N+ region 412 has a longest dimension in the first direction and is substantially parallel to the first and second heavily doped P+ regions 408, 410.

[0044] Another heavily doped P+ region 414 is formed in the substrate adjacent to the n-well 402. The heavily doped P+ region 414 is formed in the region 416 between the n-well 402 and the DNW 404. The p-well 406 in the DNW 404 includes both the n+ region 426 and the p+ region 625. As described above, the present disclosure is intended to eliminate or substantially reduce latch-up problems while not wasting area for separating the NPN base region from the ESD N diode. The present disclosure is intended to provide a latch-up protection layer by means of a so-called R 发射极 A resistor (having a value in kilo-ohms) connects DNW, which isolates the p-substrate, to VDDE.

[0045] As with the MOS configuration, by including this resistor (R 发射极 ), which can significantly save area. It can be imagined that R 发射极 will be formed on the outside of the ground ring 110 . Figure 7The ground ring 110 in the n-well 404 may be formed completely around the DNW 404. The ground ring 110 may also extend completely around the n-well 402. In an alternative embodiment, the R emitter may be formed within the DNW.

[0046] Resistor (R 发射极 ) can be designed using the smallest polysilicon resistors. 发射极 should not be diffusion type or well resistors. 发射极 In the case of , dimension d1 between DNW 404 and n-well 402 may be in the range of 3.3 microns and 7 microns, inclusive. These dimensions are one example, and a variety of dimensions may be implemented for a diode configuration.

[0047] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

[0048] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalent forms to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A device comprising: P-type substrate; a first N-type region in the substrate; a second N-type region in the substrate, spaced less than 7 microns from the first N-type region, the second N-type region being a deep N-well; a first heavily doped P-type region, between the first N-type region and the deep N-well, the first heavily doped P-type region coupled to ground; a second heavily doped P-type region in the first N-type region; a first heavily doped N-type region in the first N-type region; a second heavily doped N-type region in the deep N-well; as well as A resistor is coupled to the second heavily doped N-type region.

2. The device of claim 1 , wherein the resistor is coupled to an emitter terminal of a first parasitic bipolar junction transistor, the first heavily doped P-type region is coupled to ground, the second heavily doped P-type region is coupled to an output terminal, the first heavily doped N-type region is coupled to a floating well terminal, and the resistor is coupled to a voltage supply terminal.

3. The device of claim 2, wherein the first bipolar junction transistor is an NPN bipolar junction transistor, the deep N-well is an emitter terminal of the first parasitic bipolar junction transistor, and the first heavily doped N-type region is a collector terminal of the first parasitic bipolar junction transistor.

4. The device of claim 3, wherein the second parasitic bipolar junction transistor is coupled to the first parasitic bipolar junction transistor, the second parasitic bipolar junction transistor is a PNP bipolar junction transistor, and a base terminal of the second parasitic bipolar junction transistor is coupled to a collector terminal of the first parasitic bipolar junction transistor. 5 . The device of claim 4 , wherein an emitter terminal of the second parasitic bipolar junction transistor is coupled to the second heavily doped P-type region.

6. The device according to claim 5, wherein a combination of the first parasitic bipolar junction transistor and the second parasitic bipolar junction transistor is equivalent to a silicon controlled rectifier, and the silicon controlled rectifier serves as a latch circuit of a group of CMOS transistors.

7. The device of claim 6, wherein the set of CMOS transistors is an input / output interface operating in a fail-safe or fail-tolerant mode.

8. The device of claim 7, wherein the resistor is an on-chip resistor coupled to a deep N-well. 9 . The device of claim 8 , wherein the resistor reduces a gain of the first parasitic bipolar junction transistor and limits a current flowing from a collector terminal of the first parasitic bipolar junction transistor to an emitter terminal of the first parasitic bipolar junction transistor.

10. The device according to claim 1, comprising: p-well in a deep N-well; a third heavily doped N-type region in the p-well; as well as A fourth heavily doped N-type region in the p-well.

11. The device according to claim 1, comprising: p-well in a deep N-well; a third heavily doped N-type region in the p-well; as well as A third heavily doped P-type region in the p-well.

12. A method comprising: A fail-safe input / output is formed on a complementary metal oxide semiconductor (CMOS) layout by coupling an input / output interface to an output terminal, the fail-safe input / output comprising: coupling a PMOS to an output terminal, the PMOS being in a P-type substrate of a CMOS layout, the PMOS comprising a first heavily doped N-type region and a first heavily doped P-type region in the first N-type region; coupling the first heavily doped N-type region to the floating well terminal; coupling the first heavily doped P-type region to an output terminal; coupling an NMOS to the output terminal, the NMOS being in a P-type substrate, the NMOS comprising a second heavily doped N-type region in a second N-type region and a second heavily doped P-type region in the P-type substrate; coupling the second heavily doped P-type region to ground, and laterally spacing the second N-type region from the first N-type region by a distance less than 7 microns; and A resistor is coupled to the second heavily doped N-type region, the resistor coupling a voltage source to the second N-type region. The method of claim 12 , wherein the second N-type region is a deep N-well.

14. The method of claim 12, wherein the parasitic latch circuit has parasitic bipolar junction transistors, and the resistor is coupled to an emitter terminal of one of the parasitic bipolar junction transistors.

15. The method of claim 12, wherein the distance has a threshold value determined to limit current leakage of a parasitic latch circuit.

16. A method comprising: Forming a complementary metal oxide semiconductor (CMOS) layout having an area threshold, the threshold being determined based on a current leakage of a parasitic latch circuit, the forming the CMOS layout comprising: forming a deep N-well region in a P-type substrate; forming an N-well region in the substrate, wherein the N-well region is laterally spaced apart from the deep N-well region by a certain distance; forming a first heavily doped P-type region in the N-well region, the first heavily doped P-type region being coupled to the output terminal; forming a second heavily doped P-type region between the N-well region and the deep N-well region, wherein the second heavily doped P-type region is coupled to the ground; forming a heavily doped N-type region in the N-well region, the heavily doped N-type region being coupled to the floating well terminal, the deep N-well region, the first heavily doped P-type region, the second heavily doped P-type region and the heavily doped N-type region forming a parasitic latch circuit; and A resistor is formed on the deep N-well region, the resistor is coupled between the deep N-well region and a voltage source, the resistor limits current leakage of the parasitic latch circuit, and in response, The area of ​​the CMOS layout is reduced to a value smaller than the threshold value. 17 . The method of claim 16 , wherein the distance is determined between a right edge of the deep N-well and a left edge of the N-well region along a first direction, and the distance is smaller than a size of the N-well in the first direction.

18. The method of claim 15, wherein the distance is less than a threshold value, the threshold value is approximately 30 μm, and the distance is between 3 and 7 μm.

19. The method according to claim 16, wherein the threshold value is between 700 and 800 μm 2 and area values ​​between 100 and 200 μm 2 between.

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