Multi-mode communication equipment multiprocessor core program management and control system construction method and system

Abstract

The invention discloses a method for constructing a multi-processor core program management and control system of multimode communication equipment. The method comprises the following steps: constructing an abstract interface of the multi-processor core program management and control system and a core processor parameter input interface; constructing specific operation interfaces corresponding to different processor cores; and constructing a function interface loaded by the processor core, and mapping the abstract interface to a specific processor core operation interface through the function interface loaded by the processor core to obtain the multi-processor core program management and control system. According to the invention, the development process of the multimode communication equipment is simplified, the portability of software is enhanced, and the cross-platform compatibility is improved.

Description

Technical Field

[0001] The present invention relates to the field of multi-processor core program control, and in particular to a method and system for constructing a multi-processor core program control system for multi-mode communication equipment. Background Art

[0002] With the rapid development of wireless communication technology, in order to cope with different wireless communication scenarios and promote software-defined radio, multi-mode wireless communication equipment needs to support multiple waveforms. In order to adapt to this multi-waveform application trend, the design complexity of its underlying hardware platform continues to increase. These hardware platforms integrate multiple types of processor cores, such as ARM processors, FPGAs, DSPs, etc. Each processor core is optimized for a specific type of computing task, and the number varies to meet diverse signal processing needs.

[0003] ARM processors are typically used to handle general computing tasks, high real-time processing tasks, and run operating system tasks, FPGAs are used to run hardware acceleration, parallel data processing, and waveform protocol development, while DSPs are used for dedicated digital signal processing tasks. This combination of multi-type processor cores provides powerful computing power and flexibility to meet a variety of complex application requirements.

[0004] However, this kind of program loading for multiple types of processor cores lacks a unified program loading abstract interface. The lack of a unified program loading abstract interface will lead to the following problems. First, different processor cores require independent management and programming interfaces, which increases code complexity, reduces development efficiency, and makes maintenance difficult. Second, the portability of the application is greatly reduced. When replacing different hardware platforms, the program loading interface of each processor core needs to be modified, resulting in low cross-platform compatibility. Third, when a new processor needs to be added, the existing loading method may require a lot of modifications, which limits the scalability of the system.

[0005] The Chinese invention application with application number 202211543375.3 discloses "An Embedded System", and its technical solution is: the embedded system includes: a hardware layer, an operating system layer, a general operating system interface and an adaptation layer. The operating system layer obtains the file to be written with the help of the general operating system interface. Then, the adaptation layer is called to determine the target interface corresponding to the hardware layer, and by calling this target interface, the file to be written is written to the storage unit in the hardware layer. In the above system, with the help of the compatibility of the general operating system interface with the operating system layer, the embedded system can achieve compatibility with different real-time kernels deployed in multiple operating system layers. The transmission adaptation function between the hardware layer and the operating system layer provided by the adaptation layer makes the embedded system compatible with multiple microcontrollers deployed in different hardware layers. Its technical solution aims to improve the porting efficiency and compatibility of the operating system, and the present invention aims to achieve efficient management and control of multiple processor cores. Summary of the invention

[0006] In order to solve the technical problems of high code complexity, low cross-platform compatibility and poor scalability of the prior art multi-mode communication equipment, the present invention provides a method and system for constructing a multi-processor core program control system for a multi-mode communication device. The technical solution adopted by the present invention is:

[0007] A first aspect of the present invention provides a method for constructing a multi-processor core program control system for a multi-mode communication device, the method comprising the following steps:

[0008] Construct an abstract interface for the multi-processor core program control system and a core processor parameter input interface;

[0009] Build specific operation interfaces corresponding to different processor cores;

[0010] A function interface loaded by the processor core is constructed, and the abstract interface is mapped to a specific processor core operation interface through the function interface loaded by the processor core, so as to obtain a multi-processor core program management and control system.

[0011] As a preferred solution, the abstract interface includes a program control interface and a management interface.

[0012] As a preferred solution, the program control interface includes loading an abstract interface, starting an abstract interface, pausing an abstract interface, resuming an abstract interface and unloading an abstract interface;

[0013] The management interface includes an upgrade abstract interface and a status query abstract interface.

[0014] As a preferred solution, the different processor cores include an ARM processor core, an FPGA processor core and a DSP processor core.

[0015] As a preferred solution, the method for constructing specific operation interfaces corresponding to different processor cores includes:

[0016] Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, uninstalling specific interface, upgrading specific interface and status query specific interface corresponding to the ARM processor core;

[0017] Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, unloading specific interface, upgrading specific interface and status query specific interface corresponding to the FPGA processor core;

[0018] Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, unloading specific interface, upgrading specific interface and status query specific interface corresponding to the DSP processor core.

[0019] As a preferred solution, a method for constructing a function interface loaded by a processor core and mapping an abstract interface to a specific processor core operation interface through the function interface loaded by the processor core to obtain a multi-processor core program control system includes:

[0020] Mapping the function interface loaded by the processor core through the abstract loading interface to the specific loading interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0021] Mapping the startup abstract interface through the function interface loaded by the processor core to the startup specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0022] Mapping the pause abstract interface to the pause specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively through the function interface loaded by the processor core;

[0023] Mapping the recovery abstract interface through the function interface loaded by the processor core to the recovery specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0024] Mapping the function interface loaded by the processor core through the unloading abstract interface to the unloading specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0025] Mapping the upgrade abstract interface through the function interface loaded by the processor core to the upgrade specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0026] The state query abstract interface is mapped to the state query specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively through the function interface loaded by the processor core.

[0027] A second aspect of the present invention provides a multi-mode communication device multi-processor core program management and construction system, the system comprising an abstract interface construction module, a specific operation interface construction module and an interface mapping module;

[0028] The abstract interface construction module is used to construct an abstract interface of a multi-processor core program management and control system and a core processor parameter input interface;

[0029] The specific operation interface construction module is used to construct specific operation interfaces corresponding to different processor cores;

[0030] The interface mapping module is used to construct a function interface loaded by the processor core, and to map the abstract interface to a specific processor core operation interface through the function interface loaded by the processor core, so as to obtain a multi-processor core program management and control system.

[0031] As a preferred solution, the core processor parameter input interface is used to input a processor core ID number and a processor core type parameter.

[0032] A third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the aforementioned method for constructing a multi-processor core program control system for a multi-mode communication device.

[0033] The fourth aspect of the present invention provides a computer device, including a storage medium, a processor, and a computer program stored in the storage medium and executable by the processor, and when the computer program is executed by the processor, the steps of the aforementioned method for constructing a multi-processor core program control system for a multi-mode communication device are implemented.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] The present invention respectively constructs a multi-processor core abstract interface and specific operation interfaces corresponding to different processor cores, and then realizes operations such as loading, starting, pausing, resuming and unloading of different types of processor cores by mapping the multi-processor core abstract interface to the specific processor core operation interface, thereby simplifying the development process, enhancing the portability of the software, improving cross-platform compatibility, and meeting future scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A flow chart of a method for constructing a multi-processor core program control system for a multi-mode communication device provided in this embodiment. DETAILED DESCRIPTION

[0037] The accompanying drawings are only used for illustrative purposes and are not to be construed as limiting the present invention;

[0038] It should be clear that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.

[0039] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. The singular forms of "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0040] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and do not have to be used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0041] In addition, in the description of this application, unless otherwise specified, "multiple" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0042] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0043] Example 1

[0044] Please refer to Figure 1This embodiment provides a method for constructing a multi-processor core program control system for a multi-mode communication device, the method comprising the following steps:

[0045] S1: Construct the abstract interface of the multi-processor core program control system and the core processor parameter input interface;

[0046] In a specific embodiment, the abstract interface includes a program control interface and a management interface;

[0047] In a specific embodiment, the program control interface includes loading an abstract interface, starting an abstract interface, pausing an abstract interface, resuming an abstract interface, and unloading an abstract interface;

[0048] The management interface includes an upgrade abstract interface and a status query abstract interface.

[0049] S2: Build specific operation interfaces corresponding to different processor cores;

[0050] In a specific embodiment, the different processor cores include an ARM processor core, an FPGA processor core, and a DSP processor core.

[0051] In a specific embodiment, a method for constructing specific operation interfaces corresponding to different processor cores includes:

[0052] Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, uninstalling specific interface, upgrading specific interface and status query specific interface corresponding to the ARM processor core;

[0053] Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, unloading specific interface, upgrading specific interface and status query specific interface corresponding to the FPGA processor core;

[0054] Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, unloading specific interface, upgrading specific interface and status query specific interface corresponding to the DSP processor core.

[0055] S3: constructing a function interface loaded by the processor core, and mapping the abstract interface to a specific processor core operation interface through the function interface loaded by the processor core, so as to obtain a multi-processor core program management and control system;

[0056] In a specific embodiment, a method for constructing a function interface loaded by a processor core and mapping an abstract interface to a specific processor core operation interface through the function interface loaded by the processor core to obtain a multi-processor core program control system includes:

[0057] Mapping the function interface loaded by the processor core through the abstract loading interface to the specific loading interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0058] Mapping the startup abstract interface through the function interface loaded by the processor core to the startup specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0059] Mapping the pause abstract interface to the pause specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively through the function interface loaded by the processor core;

[0060] Mapping the recovery abstract interface through the function interface loaded by the processor core to the recovery specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0061] Mapping the function interface loaded by the processor core through the unloading abstract interface to the unloading specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0062] Mapping the upgrade abstract interface through the function interface loaded by the processor core to the upgrade specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively;

[0063] The state query abstract interface is mapped to the state query specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively through the function interface loaded by the processor core.

[0064] Example 2

[0065] This embodiment provides a multi-mode communication device multi-processor core program management and construction system, the system includes an abstract interface construction module, a specific operation interface construction module and an interface mapping module;

[0066] The abstract interface construction module is used to construct an abstract interface of a multi-processor core program management and control system and a core processor parameter input interface;

[0067] In a specific embodiment, the core processor parameter input interface is used to input a processor core ID number and a processor core type parameter.

[0068] The specific operation interface construction module is used to construct specific operation interfaces corresponding to different processor cores;

[0069] The interface mapping module is used to construct a function interface loaded by the processor core, and to map the abstract interface to a specific processor core operation interface through the function interface loaded by the processor core, so as to obtain a multi-processor core program management and control system.

[0070] Example 3

[0071] This embodiment provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for constructing a multi-processor core program control system for a multi-mode communication device described in Embodiment 1 are implemented.

[0072] Example 4

[0073] A computer device comprises a storage medium, a processor and a computer program stored in the storage medium and executable by the processor, wherein the computer program, when executed by the processor, implements the steps of the method for constructing a multi-processor core program control system for a multi-mode communication device as described in Example 1.

[0074] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A method for constructing a multi-processor core program control system for a multi-mode communication device, characterized in that: The method comprises the following steps: Construct an abstract interface for the multi-processor core program control system and a core processor parameter input interface; Build specific operation interfaces corresponding to different processor cores; A function interface loaded by the processor core is constructed, and the abstract interface is mapped to a specific processor core operation interface through the function interface loaded by the processor core, so as to obtain a multi-processor core program management and control system.

2. The method for constructing a multi-processor core program control system for a multi-mode communication device according to claim 1, characterized in that: The abstract interface includes a program control interface and a management interface.

3. The method for constructing a multi-processor core program control system for a multi-mode communication device according to claim 2, characterized in that: The program control interface includes loading abstract interface, starting abstract interface, pausing abstract interface, resuming abstract interface and unloading abstract interface; The management interface includes an upgrade abstract interface and a status query abstract interface.

4. The method for constructing a multi-processor core program control system for a multi-mode communication device according to claim 3, characterized in that: The different processor cores include an ARM processor core, an FPGA processor core and a DSP processor core.

5. The method for constructing a multi-processor core program control system for a multi-mode communication device according to claim 4, characterized in that: Methods for constructing specific operation interfaces corresponding to different processor cores include: Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, uninstalling specific interface, upgrading specific interface and status query specific interface corresponding to the ARM processor core; Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, unloading specific interface, upgrading specific interface and status query specific interface corresponding to the FPGA processor core; Construct the loading specific interface, starting specific interface, pausing specific interface, resuming specific interface, unloading specific interface, upgrading specific interface and status query specific interface corresponding to the DSP processor core.

6. The method for constructing a multi-processor core program control system for a multi-mode communication device according to claim 5, characterized in that: The method of constructing a function interface loaded by a processor core and mapping an abstract interface to a specific processor core operation interface through the function interface loaded by the processor core to obtain a multi-processor core program control system includes: Mapping the function interface loaded by the processor core through the abstract loading interface to the specific loading interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively; Mapping the startup abstract interface through the function interface loaded by the processor core to the startup specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively; Mapping the pause abstract interface to the pause specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively through the function interface loaded by the processor core; Mapping the recovery abstract interface through the function interface loaded by the processor core to the recovery specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively; Mapping the function interface loaded by the processor core through the unloading abstract interface to the unloading specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively; Mapping the upgrade abstract interface through the function interface loaded by the processor core to the upgrade specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively; The state query abstract interface is mapped to the state query specific interfaces corresponding to the ARM processor core, the FPGA processor core and the DSP processor core respectively through the function interface loaded by the processor core.

7. A multi-processor core program control and construction system for multi-mode communication equipment, characterized in that: The system includes an abstract interface building module, a specific operation interface building module and an interface mapping module; The abstract interface construction module is used to construct an abstract interface of a multi-processor core program management and control system and a core processor parameter input interface; The specific operation interface construction module is used to construct specific operation interfaces corresponding to different processor cores; The interface mapping module is used to construct a function interface loaded by the processor core, and to map the abstract interface to a specific processor core operation interface through the function interface loaded by the processor core, so as to obtain a multi-processor core program management and control system.

8. The multi-processor core program management and construction system for multi-mode communication equipment according to claim 7, characterized in that: The core processor parameter input interface is used to input a processor core ID number and a processor core type parameter.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, the steps of the method for constructing a multi-processor core program control system for a multi-mode communication device as described in any one of claims 1 to 6 are implemented.

10. A computer device, characterized in that: It includes a storage medium, a processor, and a computer program stored in the storage medium and executable by the processor, and when the computer program is executed by the processor, it implements the steps of the method for constructing a multi-processor core program control system for a multi-mode communication device as described in any one of claims 1 to 6.

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