BCH decoding method for MCU-level embedded memory with high bit error rate

Abstract

The invention discloses a BCH (Broadcast Channel) decoding method for an MCU (Microprogrammed Control Unit)-level embedded memory with a high bit error rate, which realizes BCH decoding by multiplexing a verification equation sub-circuit of a Chien search circuit and combining a syndrome generation circuit, an error equation generation circuit and a counter. Different from a previous table look-up decoding method and a BM (Berlekamp-Massey) iteration method, the BCH decoder circuit area is remarkably reduced, meanwhile, the multiplexing condition of a Cash search circuit verification equation sub-circuit can be automatically adjusted, and in combination with an actual scene, the results of low decoding beat and low resource loss are achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of BCH decoding in the field of memory and error correction coding, and in particular relates to a BCH decoding method with low resource loss and low delay. Background Art

[0002] Memory often undergoes random flipping errors in space due to various factors. This error only affects whether the stored content is correct, but does not damage the device itself. Soft errors are a kind of error. There are many ways to reduce the impact of soft errors. Among them, the method widely used in industrial and civilian fields is ECC (Error correction code), which uses an error correction algorithm to add a small amount of redundant check bits to each frame of fixed data bits. Before writing to the memory, it is encoded according to a predetermined error correction algorithm, and after reading out of the memory, it is decoded to determine whether an error occurs and find the corresponding error location for error correction. [1] For multi-bit errors, more powerful error correction codes such as BCH codes are needed.

[0003] At present, the largest shipment volume of consumer electronics is often MCU-level embedded products. In these products, the storage unit for storing programs and data is generally at the KB and MB level. It is possible that multiple bit errors will occur in one frame of data, and the error pattern is relatively small. For such embedded storage devices with small storage capacity but important storage content and low fault tolerance, storage close to the core and high memory access speed requirements, BCH parallel encoding and decoding circuits are generally used as ECC solutions. When the circuit is optimized, good delay and frequency performance can be achieved, while resource loss can be controlled within an acceptable range. Summary of the invention

[0004] The present invention proposes a low resource loss and low delay frequency BCH decoding method for a high bit error rate memory.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A BCH decoding method for a high bit error rate memory, characterized by comprising the following steps performed under a finite field rule:

[0007] 1) The external input codeword polynomial R(x) is used to calculate the syndrome S using the syndrome calculation circuit according to formulas (1) and (2). i That is S i (x), (a j ) i Represents a finite field primitive polynomial a j The i-th power, note that in all polynomials in this finite field, the coefficients (in formula (1) refer to r0~r n-1That is, the codeword binary value) refers to the binary value, and 0, x~x n-1 It represents the position of the binary value:

[0008] R(x)=r0+r1x……+r n-1 x n-1 Formula (1)

[0009]

[0010] 2) Using the error equation generation circuit, the error equation coefficient δ is obtained according to formula (3) (4) j , where t is the maximum error correction capability and v is the sequential index of the error bits:

[0011] S j+v +δ1 S j+v-1 +…+ δ v-1 S j+1 +δ v S j =0 1≤j≤2t-v Formula (3)

[0012]

[0013] 3) Reuse the Chien search circuit of the verification equation subcircuit to solve the error equation and finally obtain the error position; wherein the reuse period of the Chien search circuit is set to M, where the value of M is between 1 and n, and the counter is used to control the search of n / M positions in each clock cycle.

[0014] Furthermore, the syndrome generation circuit uses a bit XOR device to perform modular addition calculation, and uses the external input code word polynomial R(x) in the form of a binary logic sequence as an enable logic signal to control the gate switch of the XOR device input. The binary number R corresponding to each bit of R(x) in the code word i , controls the element a in the finite field corresponding to the number of digits i i The binary representation of the sequence is used as the input of the XOR.

[0015] Furthermore, the error equation generation circuit uses a constant modular multiplier and a modular addition operator (bitwise XOR) to calculate the error equation. The constant modular multiplier maps the coefficient relationship between the polynomial multiplication result in the real number field and the finite field based on the descending power identity related to the primitive polynomial in the finite field, and logically optimizes the mapping relationship according to the constants used and converts it into pure XOR logic.

[0016] Furthermore, when the counter counts to 1, the first group is input, and when the count is M, the Mth group is input. If n / M has a remainder, M+1 cycles are searched and divided into M+1 groups. The finite field elements corresponding to the possible error positions in the group are substituted into the error equation one by one for verification. On the premise that the number of errors is within the error correction capability, if the equation value is zero, it means that an error has occurred at the position represented here.

[0017] The beneficial effects of the present invention are as follows:

[0018] The present invention is based on Peterson decoding theory. For (n, k, t) BCH codes with n-bit codeword length, k-bit data bits, and t-bit error correction capability, the verification equation subcircuit of the Qian search circuit is reused, and the BCH decoding is realized by combining the syndrome generation circuit, the error equation generation circuit and the counter. Unlike the previous table lookup decoding method and the BM (Berlekamp-Massey) iteration method, the present invention significantly reduces the circuit area of ​​the decoder. At the same time, the reuse of the verification equation subcircuit of the Qian search circuit can be adjusted by itself. Combined with the actual scene, the result of low decoding beats and low resource loss is achieved. Experiments show that the present invention has a very high application value when the error correction capability is less than 5. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of a BCH decoding method according to a specific embodiment of the present invention;

[0020] Figure 2 A schematic diagram of a syndrome generation circuit according to a specific embodiment of the present invention;

[0021] Figure 3 A schematic diagram of an error equation generating circuit according to a specific embodiment of the present invention;

[0022] Figure 4 A schematic diagram of a Qian's search circuit according to a specific embodiment of the present invention;

[0023] Figure 5 A schematic diagram of the present invention performing 2-cycle multiplexing on the Qian's search circuit; DETAILED DESCRIPTION

[0024] Next, we use the Galois Field GF(2 6 )'s (44, 32, 2) BCH code (total codeword 44 bits, data bits 32 bits, error correction capability 2 bits) is implemented based on a 2-cycle Qian search circuit to illustrate the entire design scheme.

[0025] The (44, 32, 2) BCH code has the following common characteristics of BCH codes:

[0026] 1. The number of data bits before encoding is k = 32, the total number of code bits after encoding is n = 44, and the number of check bits is nk = 12.

[0027] 2. (44, 32, 2) The error correction capability of the BCH code is 2, which can correct up to two random errors in a 44-bit total codeword. 6 -1>44>2 5 -1, so its encoding and decoding operations occur in the Galois field GF(2 6 ), if m=6, the length of the check bit is mt=6x2=12.

[0028] like Figure 1 As shown, the specific steps of the present invention are as follows:

[0029] 1) The syndrome generation circuit uses a bitwise XOR device to perform modular addition calculation, where the finite field element a 0 ~a 43 and its third power (a 0 ) 3 ~a 43 As a constant input, through the codeword r0~r 43 As an enable signal, it controls whether to enter the bit XOR device for modular addition calculation. i When a is zero, i It will not enter the analog addition calculation. In this calculation process, the constant input can be stored and used as a fixed circuit structure. According to the syndrome S1 and S3 calculation formulas (Formulas 5 and 6) corresponding to the BCH code,

[0030]

[0031] Use "*" to represent modular multiplication and "+" to represent modular addition, such as Figure 2 As shown, the syndrome calculation circuit replaces "+" with a bitwise XOR, i.e., modular addition, and then calculates the syndrome value.

[0032] 2) With syndromes S1 and S3 as input, the relationship between coefficients δ0, δ1 and δ2 and syndromes S1 and S3 is obtained through equation 7 (Equations 8, 9, and 10). The error equation generation circuit uses a constant modular multiplier and a modular addition operator (bitwise XOR) to calculate the error equation coefficients. The modular addition operation can be replaced by a bitwise XOR, such as Figure 3 shown.

[0033] δ0+δ1x+δ2x 2 =0 Formula (7)

[0034] δ0=S1 Formula (8)

[0035] δ1=S1 2 Formula (9)

[0036] δ2=S1 3 +S3 formula (10)

[0037] According to the logical relationship between constants and companion variables, for all constants 1 corresponding to the finite field elements used for verification, (a -1 ) 2 , (a -2 ) 2 ……(a -43 ) 2 ; 1, a -1 ……a -43 , design the corresponding constant modular multipliers one by one.

[0038] In this example, the design process of the constant modular multiplier is as follows:

[0039] By GF(2 6 ) field is P(x)=x 6 +x+1, P(a)=0, so a 6 =a+1. Therefore, for any two elements a(x) and b(x), their multiplication result c(x) in the real number field, and their multiplication result w(x) in the finite field, we have:

[0040]

[0041] And c(x)=(a5x 5 +a4x 4 +a3x 3 +a2x 2 +a1x+a0)*(b5x 5 +b4x 4 +b3x 3 +b2x 2 +b1x+b0) are:

[0042]

[0043] Since in GF(2 6 ) domain, x 6 、x 8 ......x 10 It can be done through x 6 = x + 1 to convert it into a polynomial with a maximum power of 5. Since the addition in the finite field is bitwise XOR, the sum of two terms with the same power is 0, so we can get GF(2 6 The coefficients of the modular multiplication result in the domain are:

[0044]

[0045] Substitute the constant into one of the multipliers, for example, 22Taking the constant modular multiplier as an example, let b(x) equal a 22 ,Right now:

[0046] a 22 =x 5 +x 4 +x 2 +1 Formula (14)

[0047] In the above formula, a 22 With b0, b2, b4, b5 equal to 1, and b1 and b3 equal to 0, substituting the coefficients of the above polynomial into the formula in Chapter 2, we get:

[0048]

[0049] Simplify the above formula to get:

[0050]

[0051] Substitute the above formula into the result polynomial, and then get the result polynomial of constant modular multiplication as follows:

[0052] Combining the above two formulas, we can get a more concise expression:

[0053]

[0054] Modular multiplication and modular addition are implemented using constant modular multipliers and bitwise XOR respectively.

[0055] 3) Using Qian's search circuit (such as Figure 4 ), the 1 representing the wrong position, (a -1 ) 2 , (a -2 ) 2 ……(a -43 ) 2 ; 1, a -1 ……a -43 Substitute these 44 finite field elements and their cubic powers into the error equation to generate 44 verification equations. If the result of the verification equation is 0, it indicates that there is an error in the corresponding position. Finally, the vector representing the error position is obtained, that is, the error pattern. Then, according to the relationship a in the finite field -i =a 63-i , combined with the corresponding relationship of the error position (as shown in the following table) to find the corresponding error position:

[0056]

[0057] The Qian search circuit is reused for 2 cycles (such as Figure 5), which consists of 22 verification equation subcircuits, can verify 22 positions at a time, and can verify all positions in 2 cycles to find the wrong position. Its circuit area is about half of that of a single-cycle Chien search circuit.

[0058] The multiplexing period of the Chien search circuit is set to M, where the value of M is between 1 and n. The counter is used to control the search of n / M positions in each clock cycle. When the count is 1, the first group is input, and when the count is M, the Mth group is input. If n / M has a remainder, M+1 cycles are searched and divided into M+1 groups. The finite field elements corresponding to the possible error positions in the group are substituted into the error equation one by one for verification. Under the premise that the number of errors is within the error correction capability, if the equation value is zero, it means that an error has occurred at the position represented here.

[0059] According to the number of multiplexing cycles M, the corresponding number of output and output registers are set. The bit width of each group of registers is n / M, which is the same as the number of positions searched by the Chien search circuit in each cycle. At the same time, the position set searched by the Chien search circuit in the xth cycle should be the same as the position set of the code words stored in the xth output and xth output registers. At the beginning of the system input data, the received code words are grouped according to the same grouping rules as the Qian search and stored in the input register. After the Chien search circuit obtains the error pattern in the xth cycle, the error pattern is XORed with the code word in the xth input register, so that the error bit in the code word part is flipped to obtain the correct code word, and stored in the xth output register. Finally, all the output registers splice the code words in order as output to obtain the decoded code word.

[0060] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A BCH decoding method for a high bit error rate memory, characterized in that: It includes the following steps under the finite domain rule: 1) The external input codeword polynomial R(x) is used to calculate the syndrome S using the syndrome calculation circuit according to formulas (1) and (2). i That is S i (x), where (a j ) i Represents a finite field primitive polynomial a j The i-th power, r0~r n-1 Refers to binary values, and 0, x~x n - 1 It represents the position of the binary value: R(x)=r0+r i x……+r n-i x n-1 Formula (1) 2) Using the error equation generation circuit, the error equation coefficient δ is obtained according to formula (3) (4) j , where t is the maximum error correction capability and v is the sequential index of the error bits: S j+v +δ 1 S j+v- 1 +…+ δ v- 1 S j+ 1 +δ v S j = 0 1 ≤ j ≤ 2t - v Equation (3) 3) Reuse the Chien search circuit of the verification equation subcircuit to solve the error equation and finally obtain the error position; wherein the reuse period of the Chien search circuit is set to M, where the value of M is between 1 and n, and the counter is used to control the search of n / M positions in each clock cycle.

2. The BCH decoding method for high bit error rate memory according to claim 1, characterized in that: In step 1), the syndrome generating circuit uses a bit XOR device to perform modular addition calculation, and uses the external input code word polynomial R(x) in the form of a binary logic sequence as an enabling logic signal to control the gate switch of the XOR device input. The binary number R corresponding to each bit of R(x) in the code word i , controls the element a in the finite field corresponding to the number of digits i i The binary representation of the sequence is used as the input of the XOR.

3. The BCH decoding method for high bit error rate memory according to claim 1, characterized in that: In step 2), the error equation generating circuit uses a constant modular multiplier and a modular addition operator to calculate the error equation coefficients.

4. The BCH decoding method for high bit error rate memory according to claim 3, characterized in that: The constant modular multiplier maps the coefficient relationship between the polynomial multiplication result in the real number field and the finite field according to the power reduction identity related to the primitive polynomial in the finite field, and logically optimizes the mapping relationship and converts it into pure XOR logic according to the constants used.

5. The BCH decoding method for high bit error rate memory according to claim 1, characterized in that: In step 3), when the count is 1, the first group is input, and when the count is M, the Mth group is input. If n / M has a remainder, M+1 cycles are searched and divided into M+1 groups. The finite field elements corresponding to the possible error positions in the group are substituted into the error equation one by one for verification. Under the premise that the number of errors is within the error correction capability, if the equation value is zero, it means that an error has occurred at the position represented here.

6. The BCH decoding method for high bit error rate memory according to claim 5, characterized in that: According to the number of multiplexing cycles M, the corresponding number of groups of output and output registers are set. The bit width of each group of registers is n / M, which is the same as the number of positions searched by the Chien search circuit in each cycle. At the same time, the position set searched by the Chien search circuit in the xth cycle should be consistent with the position set of the codewords stored in the xth output and xth output registers.

7. The BCH decoding method for high bit error rate memory according to claim 6, characterized in that: After the Chien search circuit obtains the error pattern in the xth cycle, it performs an XOR operation on the error pattern and the code word in the xth input register to flip the error bit in the code word part to obtain the correct code word, and stores it in the xth output register.

Images