Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The semiconductor device includes a substrate, a stacked structure, and a first capping layer. The stacked structure is arranged on the substrate and comprises an array part and a first step part, and the first step part is provided with a plurality of first step surfaces with the heights gradually decreased in the first direction. The first covering layer is arranged on the stacking structure, covers the array part and exposes the first step part, and the top surface of the first covering layer is higher than the topmost surface of the first step part; in a direction perpendicular to the substrate, the plurality of first stepped surfaces are simultaneously flush with sidewalls of the first capping layer. Therefore, the length ratio or the area ratio of the first step part relative to the array part is effectively reduced, so that the structure of the semiconductor device is tighter and more stable, and the optimized operation performance can be achieved.

Description

Technical Field

[0001] The present application relates to a semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In modern electronic products, memory plays an indispensable and important role. In addition to storing user data, memory is also responsible for storing program codes executed by the central processing unit and information that needs to be temporarily saved during the operation process. Memory can be divided into volatile memory and non-volatile memory. Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). Their data will disappear after power failure and must be re-entered the next time power is supplied. Non-volatile memory includes read-only memory (ROM) and flash memory. The data stored in them still exists even if the power is cut off, so the valid data stored earlier can be directly read after power is restored.

[0003] With the advancement of semiconductor manufacturing technology, memory has shifted from a planar structure to a three-dimensional (3D) stacked structure to achieve higher cell density per unit wafer area and meet the demand for higher storage capacity. A three-dimensional memory generally includes a staircase structure formed on one or more sides of a memory stack structure to fan out each layer of wordline to electrically connect to an interconnect structure (e.g., a wordline contact plug). However, as the number of levels of the memory stack structure gradually increases, the related manufacturing process and device structure must be further improved to maintain good device performance while simplifying the manufacturing process. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device, in which a step portion to be electrically connected to a plug is arranged on one side of an array portion. In this way, the length ratio or area ratio of the step portion relative to the array portion can be effectively reduced, making the structure of the semiconductor device more compact and stable, and achieving more optimized operating performance.

[0005] The purpose of the present application is to provide a method for manufacturing a semiconductor device, by pre-forming a covering layer to limit the formation of a step portion on one side of an array portion. In this way, the manufacturing process of the step portion can be effectively simplified, and the length ratio or area ratio of the step portion relative to the array portion can be reduced, so that the structure of the manufactured semiconductor device is more compact and stable, and can achieve more optimized operating performance.

[0006] A semiconductor device provided by an embodiment of the present application includes a substrate, a stacking structure, and a first covering layer. The stacking structure is arranged on the substrate, including an array portion and a first stepped portion, wherein the first stepped portion has a plurality of first stepped surfaces with gradually decreasing heights along a first direction. The first covering layer is arranged on the stacking structure, covering the array portion and exposing the first stepped portion, wherein the bottom surface of the first covering layer is higher than the topmost surface of the first stepped portion. In a direction perpendicular to the substrate, the plurality of first stepped surfaces are simultaneously flush with the sidewalls of the first covering layer.

[0007] A method for manufacturing a semiconductor device provided in one embodiment of the present application includes the following steps. A substrate is provided, and a stacking structure is formed on the substrate, wherein the stacking structure includes an array portion and a first step portion, wherein the array portion is arranged on one side of the first step portion, and the first step portion has a plurality of first step surfaces whose heights gradually decrease along a first direction. A first covering layer is formed on the stacking structure, covering the array portion and exposing the first step portion, wherein the bottom surface of the first covering layer is higher than each of the first step surfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a deeper understanding of this embodiment and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figure 1 FIG. 1 is a top view of a semiconductor device according to a first embodiment of the present application;

[0010] Figure 2 FIG. 1 is a schematic three-dimensional diagram of a semiconductor device according to a first embodiment of the present application;

[0011] Figure 3 Illustrated is a three-dimensional schematic diagram after forming a first mask layer in the method for manufacturing a semiconductor device according to the first embodiment of the present application;

[0012] Figure 4Illustrated are other schematic diagrams of the method for manufacturing a semiconductor device according to the first embodiment of the present application after forming a first mask layer;

[0013] Figure 5 FIG. 1 is a three-dimensional schematic diagram of a method for manufacturing a semiconductor device according to the first embodiment of the present application after an etching process is performed;

[0014] Figure 6 Illustrated are other schematic diagrams of the method for manufacturing a semiconductor device according to the first embodiment of the present application after an etching process is performed;

[0015] Figure 7 Illustrated is a schematic diagram of the method for manufacturing a semiconductor device after forming a second mask layer according to the first embodiment of the present application;

[0016] Figure 8 Illustrated is a schematic diagram of the method for manufacturing a semiconductor device after trimming the second mask layer according to the first embodiment of the present application;

[0017] Fig. 9 Illustrated is a schematic diagram of the method for manufacturing a semiconductor device according to the first embodiment of the present application after the second mask layer is trimmed again;

[0018] Fig.10 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device after forming a stepped portion according to the first embodiment of the present application;

[0019] Fig.11 Illustrated is a schematic structural diagram of a semiconductor device according to a second embodiment of the present application;

[0020] Fig.12 FIG. 1 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present application.

[0021] The reference numerals are described as follows:

[0022] 10, 30, 40 Semiconductor devices

[0023] 100 Substrate

[0024] 102 Stop layer

[0025] 110 stacking structure

[0026] 112 First Step

[0027] 114 Array Department

[0028] 112s First step surface

[0029] 112t Top

[0030] 112w Sidewall

[0031] 114t Top

[0032] 120 Conductive-dielectric layer pair

[0033] 122 Dielectric layer

[0034] 124 Conductive layer

[0035] 130 Etch stop layer

[0036] 130a Etching stop material layer

[0037] 140 First Covering Layer

[0038] 140t Top

[0039] 150 First Plug

[0040] 150t top surface

[0041] 160 Isolation layer

[0042] 162 First Isolation Layer

[0043] 164 Second isolation layer

[0044] 166 Electrical connector

[0045] 166t Top

[0046] 170 first mask layer

[0047] 172 second mask layer

[0048] 212, 312, 412 Second step

[0049] 212s, 312s, 412s second step surface

[0050] 212t, 312t top surface

[0051] 250 Second plug

[0052] 340 Second Covering Layer

[0053] A1 Zone 1

[0054] A2 Zone 2

[0055] A3 Zone 3

[0056] D1 First direction

[0057] D2 Second direction

[0058] D3 vertical direction

[0059] H1, H3, H5 distance

[0060] H2, H4, H6 distance

[0061] L1, L2 length

[0062] R1, R2, R3 gap

[0063] S1, S3, S5 step surface

[0064] S2, S4, S6 step surface DETAILED DESCRIPTION

[0065] In order to enable a person skilled in the art who is familiar with the technical field to which the present application belongs to further understand the present application, several preferred embodiments of the present application are listed below, and the components and intended effects of the present application are described in detail with the accompanying drawings. A person skilled in the art who is familiar with the present application can refer to the following embodiments and replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present application.

[0066] Figure 1 to Figure 2 The diagrams shown are schematic diagrams of a semiconductor device 10 according to an embodiment of the present application, which are respectively a top view schematic diagram and a three-dimensional schematic diagram of the semiconductor device 10. Those skilled in the art should easily understand that in order to clearly present the three-dimensional structure of each component arrangement in the semiconductor device 10, Figure 2 Only present Figure 1 1. The structure of a portion of the semiconductor device 10 is shown in FIG.

[0067] Please refer to Figure 1 and Figure 2 As shown, the semiconductor device 10 includes a substrate 100, a stacked structure 110, a plurality of electrical connectors 166, and a first covering layer 140. The substrate 100 is, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, and the stacked structure 110, the electrical connectors 166, and the first covering layer 140 are respectively disposed on the substrate 100, and the electrical connectors 166 are connected to the substrate 100 through the stacked structure 110.

[0068] The stacked structure 110 includes an array portion 114 and a first stepped portion 112 disposed on one side of the array portion 114, wherein the first stepped portion 112 has a plurality of first stepped surfaces 112s with gradually decreasing heights along a first direction D1, and in a direction perpendicular to the substrate 100, each of the first stepped surfaces 112s is tangent to the sidewall of the first cover layer 140. Those skilled in the art should easily understand that the height of the first stepped surface 112s refers to the distance from the first stepped surface 112s of each layer to the top surface of the substrate 100, such as Figure 2 The distance H1 is shown, but is not limited thereto.

[0069] A plurality of electrical connectors 166 are disposed in the array portion 114 of the stacked structure 110, wherein the electrical connectors 166 are sequentially arranged along a first direction D1 and a second direction D2 perpendicular to the first direction D1 so as to be Figure 1 A memory array is shown in a top view.

[0070] It should be noted that the first covering layer 140 is additionally disposed on the stacking structure 110, covering the array portion 114 and exposing the first step portion 112, wherein the bottom surface of the first covering layer 140 is higher than the first step surface 112s of each layer. In this way, the array portion 114 of the stacking structure 110 can be effectively covered and protected by the setting of the first covering layer 140, and the first step portion 112 is confined to one side of the array portion 114, which greatly reduces the length or area occupied by the first step portion 112 in the stacking structure 110, so that the structure of the semiconductor device 10 is more compact and stable, and can achieve more optimized operating performance.

[0071] In one embodiment, a ratio (L1 / L2) of a length L1 of the first step portion 112 of the stacking structure 110 in the second direction D2 to a length L2 of the array portion 114 of the stacking structure 110 in the second direction D2 is, for example, approximately 1 / 10 to 1 / 100, and an area ratio of the first step portion 112 to the array portion 114 may also be reduced accordingly, but is not limited thereto.

[0072] In detail, the stacked structure 110 includes a plurality of dielectric layers 122 and a plurality of conductive layers 124 alternately stacked in a vertical direction D3 (e.g., a direction perpendicular to the substrate 100), and each conductive layer 124 and a dielectric layer 122 thereon together form a set of conductive-dielectric layer pairs 120, such as Figure 2That is, the stacked structure 110 includes a plurality of groups of conductive-dielectric layer pairs 120 stacked in sequence, wherein the dielectric layer 122 and each conductive layer 124 in each group of conductive-dielectric layer pairs 120 completely extend over the entire array portion 114, and at least partially extend over the first stepped portion 112. The topmost surface 112t of the first stepped portion 112 is, for example, at the same level as the top surface 114t of the array portion 114, and is higher than the first stepped surface 112s of each layer.

[0073] In one embodiment, the conductive layer 124 includes, for example, a conductive material such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), doped polysilicon, doped silicon, metal silicide, and other metal or non-metal conductive materials or any combination thereof, and the dielectric layer 122 includes, for example, a dielectric material such as silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), and other dielectric materials or any combination thereof, but is not limited thereto.

[0074] For example Figure 1 and Figure 2 As shown, the semiconductor device 10 further includes a plurality of first plugs 150 disposed on the first stepped portion 112, and an isolation layer 160 sequentially disposed on the first cover layer 140. Specifically, the first plugs 150 are all disposed on one side of the electrical connection member 166 in the second direction D2, and are sequentially arranged in the second direction D2, and are respectively located on each first stepped surface 112s of the first stepped portion 112, wherein each first plug 150 is partially disposed in the isolation layer 160, and partially disposed in the first stepped portion 112 of the stacked structure 110, and respectively penetrates the dielectric layer 122 in a corresponding group of conductive-dielectric layer pairs 120, and is physically in contact with and electrically connected to the conductive layer 124 in the same group of conductive-dielectric layer pairs 120. On the other hand, each electrical connection member 166 has, for example, a columnar shape (e.g., a cylindrical shape), and is partially disposed in the isolation layer 160 and partially disposed in the array portion 114 of the stacked structure 110, so as to penetrate the array portion 114 and be electrically connected to a plug (not shown) or a conductive structure (not shown) disposed in the substrate 100. Thus, the top surface 140t of the first cover layer 140 is lower than the top surface 150t of the first plug 150, or lower than the top surface 166t of the electrical connection member 166.

[0075] In one embodiment, each first plug 150 and each electrical connector 166, for example, comprises a conductive material, such as a low-resistance metal conductive material such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, etc., preferably tungsten, but not limited thereto. In another embodiment, the isolation layer 160, for example, comprises a first isolation layer 162 and a second isolation layer 164 stacked in sequence, wherein the first isolation layer 162 and the second isolation layer 164, for example, respectively comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but not limited thereto.

[0076] In addition, a liner layer (not shown) and a stop layer 102 may be additionally disposed between the substrate 100 and the stacked structure 110, wherein the liner layer may include, for example, a material such as silicon oxide, and the stop layer 102 may include, for example, a dielectric material having an etching selectivity with the dielectric layer 122 and the liner layer, such as aluminum oxide (Al2O3). 2 O 3 ), but is not limited to this.

[0077] Furthermore, in another embodiment, the stacked structure 110 of the semiconductor device 10 may further include a second stepped portion 212 also disposed on one side of the array portion 114, and the semiconductor device 10 may additionally include an etching stop layer 130 disposed between the second stepped portion 212 and the first stepped portion 112 in the vertical direction D3, and a plurality of second plugs 250 disposed on the second stepped portion 212. Specifically, the second stepped portion 212 is, for example, disposed adjacent to the first stepped portion 112, and is also exposed from the first covering layer 140 and has a plurality of second stepped surfaces 212s with gradually decreasing heights along the first direction D1. The topmost surface 212t of the second stepped portion 212 is, for example, located at the same horizontal height as the bottom surface of the etching stop layer 130, and is significantly lower than the bottom surface of the first covering layer 140, the top surface 114t of the array portion 114, or the topmost surface 112t of the first stepped portion 112. Those skilled in the art can easily understand that the height of the second stepped surface 212s refers to the distance from the second stepped surface 212s of each layer to the top surface of the substrate 100. Figure 2 The distance H2 is shown, but is not limited to this.

[0078] On the other hand, the etching stop layer 130 is disposed in the stacked structure 110 and has a sidewall that is flush with the first stepped portion 112, so that the second stepped portion 212 is exposed from the etching stop layer 130. The etching stop layer 130, for example, also includes a dielectric material that has etching selectivity with the dielectric layer 122 and the liner layer, such as aluminum oxide, but is not limited thereto.

[0079] The second plug 250 is disposed on one side of the electrical connector 166 in the second direction D2, adjacent to the first plug 150, and arranged in sequence in the second direction D2, and respectively aligned with each second step surface 212s of the second step portion 212. Each second plug 250 is also partially disposed in the isolation layer 160, and partially disposed in the second step portion 212 of the stacked structure 110, and respectively penetrates the dielectric layer 122 in a corresponding group of conductive-dielectric layer pairs 120, and physically contacts and electrically connects to the conductive layer 124 in the same group of conductive-dielectric layer pairs 120. In one embodiment, each second plug 250, for example, also includes a conductive material, such as a low-resistance metal conductive material such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, etc., preferably including tungsten, but not limited thereto. It should be noted that each second step surface 212s is, for example, disposed in alignment with each adjacent first step surface 112s in the second direction D2, such as Figure 2 As shown, each second plug 250 is staggered with each adjacent first plug 150 in the second direction D2, as shown in FIG. Figure 1 As shown, the second plug 250 and the first plug 150 can both retain a relatively sufficient process window in the subsequent manufacturing process.

[0080] Since the first stepped portion 112 and / or the second stepped portion 212 of the present embodiment are both confined to one side of the array portion 114, the first plug 150 and / or the second plug 250 can also be correspondingly confined to one side of the array portion 114, thereby greatly reducing the length or area occupied by the first stepped portion 112 and / or the second stepped portion 212 in the stacked structure 110, making the structure of the semiconductor device 10 more compact and stable. In addition, since the first stepped portion 112 and the second stepped portion 212 of the present embodiment are respectively disposed above and below the etching stop layer 130, each first plug 150 and each second plug 250 can alternately fan out from different regions on each first stepped surface 112s and each second stepped surface 212s in sequence to avoid compressing the manufacturing space of the first plug 150 and the second plug 250, so that the semiconductor device 10 of the present embodiment has a more reliable component structure and can achieve a more optimized operating performance.

[0081] However, those skilled in the art should easily understand that although the semiconductor device 10 of the aforementioned embodiment is described as an implementation mode in which the first step portion 112 and the second step portion 212 are simultaneously provided on one side of the array portion 114, it is not limited thereto, and the first step portion 112 or the second step portion 212 may be provided only on one side of the array portion 114 according to actual device requirements, and the provision of the etching stop layer 130 may be omitted. In order to enable those skilled in the art to implement the semiconductor device 10 of the aforementioned embodiment of the present application, the manufacturing method of the semiconductor device 10 is further described below.

[0082] Please refer to Figures 3 to 10 , which is a schematic diagram of the steps of a method for manufacturing a semiconductor device 10 according to the first embodiment of the present application, wherein: Figure 3 and Figure 5 is a three-dimensional schematic diagram of the semiconductor device 10 at different manufacturing stages, and the remaining figures are top-view schematic diagrams and cross-sectional schematic diagrams of the semiconductor device 10 at different manufacturing stages.

[0083] First, if Figure 3 and Figure 4 As shown, a substrate 100 is provided, and a stop layer 102, a plurality of dielectric layers 122 and a plurality of conductive layers 124 alternately stacked, an etch stop material layer 130a, a plurality of dielectric layers 122 and a plurality of conductive layers 124 alternately stacked, and a first cover layer 140 are sequentially formed on the substrate 100, and each conductive layer 124 and a dielectric layer 122 thereon jointly form a group of conductive-dielectric layer pairs 120. Preferably, the dielectric layers 122 and the conductive layers 124 stacked above and below the etch stop material layer 130a have the same number, and the plurality of conductive-dielectric layer pairs 120 disposed above and below the etch stop material layer 130a also have the same number of groups, but this is not limited thereto. Next, a first mask layer 170 is formed on the first cover layer 140. In one embodiment, the first mask layer 170, for example, comprises a photoresist material or other suitable materials, but this is not limited thereto.

[0084] Those skilled in the art should be able to easily understand that Figure 4 1 is a schematic top view of the semiconductor device 10 of the present embodiment after the first mask layer 170 is formed and a schematic cross-sectional view thereof along the cut line A-A' and the cut line BB'. It should be noted that the first covering layer 140 completely covers the second area A2 of the substrate 100, while exposing the first area A1 of the substrate 100, and the first mask layer 170 completely covers the second area A2 of the substrate 100 and part of the first area A1, while exposing the third area A3 of the substrate 100 (i.e., the part of the first area A1 not covered by the first mask layer 170), as shown in FIG. Figure 3 and Figure 4In one embodiment, the second area A2 and the first area A1 of the substrate 100 are disposed adjacent to each other in the second direction D2, for example. Figure 3 and Figure 4 As shown, but not limited thereto, in another embodiment, the first area A1 may be disposed on the other side of the second area A2 in the second direction D2 or on one side in the second direction D2 according to actual device requirements.

[0085] like Figure 5 and Figure 6 As shown, an etching process is performed with the aid of the first mask layer 170, such as a dry etching process or a wet etching process, to remove the dielectric layer 122 and the conductive layer 124 exposed from the first mask layer 170, that is, to remove the dielectric layer 122 and the conductive layer 124 located in the third area A3 of the substrate 100. Those skilled in the art should easily understand that Figure 6 1 is a schematic diagram showing a top view of the semiconductor device 10 of the present embodiment after the etching process is performed and a schematic diagram showing a cross section along the cut line A-A' and the cut line BB'. It should be noted that the etching process uses the etching stop material layer 130a as the etching stop layer. For this reason, the dielectric layer 122 and the conductive layer 124 located above the etching stop material layer 130a and located in the third area A3 and exposed from the first mask layer 170 are completely removed. In addition, the etching stop material layer 130a is also partially removed to form an etching stop layer 130 whose sidewalls are aligned with the first mask layer 170, as shown in FIG. Figure 5 and Figure 6 Then, the first mask layer 170 is completely removed.

[0086] like Figure 7 As shown, a second mask layer 172 is formed on the first cover layer 140, and a first etching process is performed with the aid of the second mask layer 172, such as a dry etching process or a wet etching process. Figure 7 1 is a schematic diagram showing a top view of the semiconductor device 10 of the present embodiment after the first etching process is performed and a schematic diagram showing a cross section along the cut line A-A', the cut line B-B' and the cut line CC'. It should be noted that the second mask layer 172 completely covers the second area A2 and most of the first area A1 of the substrate 100, and only the notch R1 of the second mask layer 172 exposes part of the first area A1 and part of the third area A3. The notch R1 is, for example, as shown in FIG. Figure 7 The rectangular opening shown in FIG. Figure 7The second mask layer 172 is shown as a corner of the second mask layer 172, but the present invention is not limited thereto. In this way, the dielectric layer 122 and the conductive layer 124 located on one side of the first area A1 and the third area A3 in the second direction D2 are exposed from the second mask layer 172. The dielectric layer 122 located in the third area A3 exposed by the notch R1 is located below the etching stop layer 130, while the dielectric layer 122 located in the first area A1 outside the third area A3 exposed by the notch R1 is located above the etching stop layer 130, as shown in FIG. Figure 7 . Then, a group of conductive-dielectric layer pairs 120 located in the third area A3 and a group of conductive-dielectric layer pairs 120 located in the first area A1 outside the third area A3 are removed from the gap R1 through a first etching process, and a layer of stepped surface S2 located below the etching stop layer 130 is formed in the third area A3, and a layer of stepped surface S1 located above the etching stop layer 130 is formed in the first area A1 outside the third area A3. The height of the stepped surface S2 in the vertical direction D3 is lower than the bottom surface of the etching stop layer 130, and the height of the stepped surface S1 in the vertical direction D3 is lower than the bottom surface of the first covering layer 140. In one embodiment, the second mask layer 172 includes, for example, a photoresist material or other suitable materials, but is not limited thereto.

[0087] like Figure 8 First, the second mask layer 172 is subjected to a trimming process, such as a dry etching process or a wet etching process to further enlarge the size of the aforementioned gap R1 to form a gap R2, and then a second etching process is performed using the trimmed second mask layer 172. Those skilled in the art should be able to easily understand that Figure 8 The schematic diagram simultaneously presents a top view of the semiconductor device 10 of the present embodiment after the trim-etching process and a schematic cross-sectional view along the cutting line AA′, the cutting line BB′ and the cutting line CC′.

[0088] It should be noted that the enlarged size of the gap R1 refers to, for example, the enlarged length of the gap R1 in the first direction D1 and / or the second direction D2. Preferably, the lengths of the gap R1 in the first direction D1 and the second direction D2 are simultaneously enlarged, so that the gap R2 has a greater length than the gap R1 in both the first direction D1 and the second direction D2. Figure 8. In addition, when the trimming process is performed, the thickness of the second mask layer 172 will be relatively reduced. In this way, the step surface S2 formed in the third area A3 and a portion of the dielectric layer 122 in the third area A3 are completely exposed from the notch R2, and the step surface S1 formed in the first area A1 outside the third area A3 and a portion of the dielectric layer 122 in the first area A1 outside the third area A3 are completely exposed, and the first cover layer 140 is also partially exposed, but not limited thereto.

[0089] The second etching process is to remove a set of conductive-dielectric layer pairs 120 from the dielectric layer 122 and the step surfaces S1 and S2 exposed by the notch R2, and further form a step surface S4 below the etching stop layer 130 in the third area A3, and form a step surface S3 above the etching stop layer 130 in the first area A1 outside the third area A3, and reduce the height of the step surfaces S1 and S2 again. It should be noted that since the portion exposed by the notch R2 is covered by the first covering layer 140, the formation of the step surfaces S1, S2, S3, and S4 is limited to the first area A1, so that the formation range and position of the step surfaces S1, S2, S3, and S4 can be more efficiently controlled.

[0090] like Fig. 9 As shown, the trimming-etching process is performed again. First, the second mask layer 172 is trimmed again, for example, by using a dry etching process or a wet etching process to further expand the size of the aforementioned gap R2 to form a gap R3, and then a third etching process is performed to remove the portion exposed from the gap R3. Those skilled in the art should easily understand that Fig. 9 The schematic diagram simultaneously presents a top view of the semiconductor device 10 of the present embodiment after the trim-etching process and a schematic cross-sectional view along the cutting line AA′, the cutting line BB′ and the cutting line CC′.

[0091] It should be noted that the enlarged size of the gap R2 refers to, for example, the enlarged length of the gap R2 in the first direction D1 and / or the second direction D2. Preferably, only the length of the gap R2 in the first direction D1 is enlarged, so that the gap R3 has a greater length than the gap R2 in the second direction D2. Fig. 9As shown in the top view in FIG. . Thus, the step surfaces S2, S4 formed in the third area A3 and a portion of the dielectric layer 122 in the third area A3 are completely exposed from the notch R3, and the step surfaces S1, S3 formed in the first area A1 outside the third area A3 and a portion of the dielectric layer 122 in the first area A1 outside the third area A3 are completely exposed, and the first cover layer 140 is also partially exposed, but not limited thereto. The third etching process is to remove a group of conductive-dielectric layer pairs 120 from the dielectric layer 122 and the step surfaces S1, S2, S3, S4 exposed by the notch R3 simultaneously downward, and further form a step surface S6 below the etching stop layer 130 in the third area A3, and a step surface S5 above the etching stop layer 130 in the first area A1 outside the third area A3, and the height of the step surfaces S1, S2, S3, S4 is further reduced downward. It should be noted that, since the portion exposed by the notch R3 is still covered by the first covering layer 140 , the stepped surfaces S1 , S2 , S3 , S4 , S5 , and S6 are only formed in the first area A1 .

[0092] In this way, after repeating the aforementioned trimming-etching process, the second mask layer 172 is completely removed, and new stepped surfaces can be gradually formed in the third area A3 and in the first area A1 outside the third area A3, and the heights of the stepped surfaces S1, S2, S3, S4, S5, and S6 formed above are further reduced. Finally, a plurality of second stepped surfaces 212s with gradually decreasing heights along the first direction D1 are formed in the third area A3, and a plurality of first stepped surfaces 112s with gradually decreasing heights along the first direction D1 are formed in the first area A1 outside the third area A3, and the second area A2 covered by the first covering layer 140 can be used as the subsequent array portion 114, forming a structure as shown in FIG. Fig.10 The stacked structure 110 shown in FIG. Fig.10Also shown are the schematic top view of the semiconductor device 10 of the present embodiment after repeated trimming-etching processes and the schematic cross-sectional view along the cut lines A-A', B-B' and CC'. Specifically, the first step portion 112 and the second step portion 212 are adjacent to each other and are both formed on one side of the array portion 114. The first step surface 112s of each layer in the first step portion 112 is significantly lower than the bottom surface of the first covering layer 140. In the direction perpendicular to the substrate (i.e., in the top view direction), each first step surface 112s is flush with the side wall of the first covering layer 140, and the distances H5, H3, and H1 from the first step surface 112s of each layer to the top surface of the substrate 100 gradually decrease in the first direction D1. The second stepped surface 212s of each layer in the second stepped portion 212 is also lower than the top surface 114t of the array portion 114, or lower than the bottom surface of the etching stop layer 130, and the distance H6, H4, H2 from the second stepped surface 212s of each layer to the top surface of the substrate 100 also gradually decreases in the first direction D1.

[0093] Subsequently, an isolation layer 160 (including a first isolation layer 162 and a second isolation layer 164 stacked in sequence) may be further formed on the stacked structure 110, an electrical connection member 166 arranged in sequence along the first direction D1 and the second direction D2 may be formed in the array portion 114, and a first plug 150 and a second plug 250 may be formed on the first step portion 112 and the second step portion 212, respectively, to finally form a structure as shown in FIG. Figure 1 and Figure 2 A semiconductor device 10 is shown.

[0094] After this operation, the manufacturing of the semiconductor device 10 in this embodiment is completed. It should be noted that, since the first cover layer 140 is pre-formed on the alternately stacked multi-layer dielectric layer 122 and the multi-layer conductive layer 124, the array portion 114 of the stacked structure 110 is pre-defined, and the subsequent trimming-etching process will also be affected by the coverage of the first cover layer 140 and be confined to the first area A1 exposed outside the first cover layer 140. In other words, the first cover layer 140 can effectively protect the pre-defined array portion 114 from being processed by the trimming-etching process, so that the trimming-etching process will only simultaneously etch the pre-defined first step portion 112 and / or the second step portion 212 to form step surfaces S1, S3, S5 and step surfaces S2, S4, S6. Thus, the first stepped portion 112 and / or the second stepped portion 212 can only be formed on one side of the array portion 114, and the positions of the first plug 150 and / or the second plug 250 formed subsequently can also be correspondingly limited to one side of the array portion 114, so as to greatly reduce the length or area occupied by the first stepped portion 112 and / or the second stepped portion 212 in the stacked structure 110, so that the formed semiconductor device 10 has a more compact and stable structure, and can achieve more optimized operation performance. In addition, since the first stepped portion 112 and the second stepped portion 212 of the present embodiment are respectively arranged above and below the etching stop layer 130, the first plug 150 and the second plug 250 formed subsequently can alternately fan out from different regions on the first stepped surface 112s and the second stepped surface 212s in sequence, avoiding compression of the manufacturing space of the first plug 150 and the second plug 250, thereby having a more reliable component structure.

[0095] Please refer to Fig.11 As shown, Fig.11 : is a cross-sectional schematic diagram of a semiconductor device 30 of the second embodiment of the present application. The structure and manufacturing method of the semiconductor device 30 of the present embodiment are substantially the same as the structure and manufacturing method of the semiconductor device 10 in the aforementioned first embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 30 of the present embodiment and the aforementioned semiconductor device 10 is that it also includes a second covering layer 340 additionally arranged above the first covering layer 140, covering the top surface 140t of the first covering layer 140, the topmost surface 112t and multiple sidewalls 112w of the first stepped portion 112, and the first stepped surfaces 112s of each layer, and exposing the second stepped portion 312 of the present embodiment.

[0096] In detail, the second step portion 312 of the present embodiment is also disposed adjacent to the first step portion 112, and has a plurality of second step surfaces 312s of gradually decreasing height along the first direction D1, and in the direction perpendicular to the substrate, each second step surface 312s is flush with the side wall of the second covering layer 340. Furthermore, the topmost surface 312t of the second step portion 312, for example, is also located at the same horizontal height as the bottom surface of the etching stop layer 130, and is significantly lower than the top surface 114t of the array portion 114 or the topmost surface 112t of the first step portion 112. It should be noted that the second step portion 312 is made, for example, by forming the second covering layer 340 on the first covering layer 140 after the first step portion 112 is formed, so as to define the formation area of ​​the second step portion 312 (i.e., Figure 5 Then, another mask layer (not shown) with a notch (not shown) is formed on the second cover layer 340, and then an etching process and a trimming-etching process are repeatedly performed under the cover of the other mask layer and the second cover layer 340 until the second stepped portion 312 of the present embodiment is formed. In this operation, each of the formed second stepped surfaces 312s is preferably staggered with each of the adjacent first stepped surfaces 112s in the second direction D2, such as Fig.11 As shown, each second plug 250 disposed on each second stepped surface 312s is also disposed in a staggered manner with each adjacent first plug 150 in the second direction D2, so as to further improve the manufacturing space of the second plug 250 and the first plug 150 in the subsequent manufacturing process. In addition, since the second covering layer 340 also covers the topmost surface 112t and the side wall 112w of the first stepped portion 112, the first stepped portion 112 can be additionally protected when the second stepped portion 312 is manufactured, and each second plug 250 respectively penetrates the second covering layer 340 covering each first stepped surface 112s and contacts the corresponding conductive layer 124.

[0097] Since the present embodiment performs two-stage trimming-etching processes on the first cover layer 140 and the second cover layer 340, respectively, the first step portion 112 and the second step portion 312 formed in the two-stage trimming-etching process may also have other forms, not limited to the aforementioned. For example, the step portions formed in the two-stage trimming-etching process may be formed on opposite sides of the array portion 114, or the step surfaces of the step portions formed in the two-stage trimming-etching process may have increasing heights along different directions, or the step surfaces may have different sizes, etc., but the present invention is not limited thereto.

[0098] According to the semiconductor device 30 of the present embodiment, the first step portion 112 and / or the second step portion 312 are still confined to the same side of the array portion 114, so that the first plug 150 and / or the second plug 250 can still be confined to the same side of the array portion 114, and a relatively sufficient manufacturing space is obtained. Therefore, in the semiconductor device 30 of the present embodiment, the length or area occupied by the first step portion 112 and / or the second step portion 312 in the stacking structure 110 can also be greatly reduced, and the manufacturing space of the first plug 150 and the second plug 250 can be further improved, so that the semiconductor device 30 of the present embodiment has a more reliable component structure and can achieve a more optimized operating performance.

[0099] Please refer to Fig.12 As shown, Fig.12 1 is a cross-sectional schematic diagram of a semiconductor device 40 of the third embodiment of the present application. The structure and manufacturing method of the semiconductor device 40 of the present embodiment are substantially the same as the structure and manufacturing method of the semiconductor device 20 of the second embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 40 of the present embodiment and the semiconductor device 30 is that the second step portion 412 of the present embodiment has a plurality of second step surfaces 412s with gradually increasing heights along the first direction D1.

[0100] In detail, the second step portion 412 of the present embodiment is also disposed adjacent to the first step portion 112, and is also formed by performing an etching process and a repeated trimming-etching process under the cover of another mask layer and the second cover layer 340 after the first step portion 112 is formed. However, the notch (not shown) on the other mask layer of the present embodiment is formed at another corner of the other mask layer, so that the distances H2, H4, and H6 from the second step surface 412s of each layer in the second step portion 412 to the top surface of the substrate 100 gradually increase in the first direction D1, and are also disposed in a staggered manner with each adjacent first step surface 112s, such as Fig.12 As shown. Under this arrangement, each second plug 250 disposed on each second stepped surface 412s is also disposed in a staggered manner with each adjacent first plug 150 in the second direction D2, thereby increasing the manufacturing space of the second plug 250 and the first plug 150 in the subsequent manufacturing process. In addition, the second covering layer 340 can also additionally protect the first stepped portion 112 when manufacturing the second stepped portion 412, and each second plug 250 respectively penetrates the second covering layer 340 covering each first stepped surface 112s and contacts the corresponding conductive layer 124.

[0101] According to the semiconductor device 40 of the present embodiment, the first step portion 112 and / or the second step portion 412 are still confined to the same side of the array portion 114, so that the first plug 150 and / or the second plug 250 can still be confined to the same side of the array portion 114, and a relatively sufficient manufacturing space is obtained. Therefore, in the semiconductor device 40 of the present embodiment, the length or area occupied by the first step portion 112 and / or the second step portion 412 in the stacking structure 110 can also be greatly reduced, and the manufacturing space of the first plug 150 and the second plug 250 can be further improved, so that the semiconductor device 40 of the present embodiment has a more reliable component structure and can achieve a more optimized operating performance.

[0102] In general, the present application predefines the arrangement positions of the array portion and the step portion of the stacked structure on the alternately stacked dielectric layer and the conductive layer by means of an additionally arranged covering layer, whereby the etching process and / or the trimming-etching process etching area can be further limited by the covering layer in the subsequent process. Therefore, the manufacturing method of the present application can greatly reduce the length or area occupied by the step portion in the formed stacked structure by the arrangement of the covering layer, so that the formed semiconductor device has a more compact and stable structure, and can achieve more optimized operating performance. Moreover, the plugs manufactured subsequently can also choose to fan out alternately from different areas of the step portion in sequence, thereby improving the manufacturing space of the plugs and forming a more reliable component structure. In this way, the semiconductor device of the present application can obtain a more optimized structural integrity and enhance its component performance.

[0103] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0104] It should be noted that the phrases "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. mentioned in the specification indicate that the described embodiments may include certain features, structures or characteristics, but not every embodiment may include the certain features, structures or characteristics. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when describing certain features, structures or characteristics in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such features, structures or characteristics in conjunction with other embodiments, whether explicitly or not explicitly described.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; A stacked structure, disposed on the substrate, comprising an array portion and a first step portion, wherein the first step portion has a plurality of first step surfaces with gradually decreasing heights along a first direction; as well as A first covering layer, disposed on the stacked structure, covering the array portion and exposing the first stepped portion, wherein a top surface of the first covering layer is higher than a topmost surface of the first stepped portion; In a direction perpendicular to the substrate, the plurality of first step surfaces are simultaneously flush with sidewalls of the first covering layer.

2. The semiconductor device according to claim 1, wherein: The stacked structure includes a plurality of conductive-dielectric layer pairs arranged sequentially in a vertical direction, and the semiconductor device further includes: a plurality of first plugs disposed on the first stepped portion and electrically connected to portions of the conductive layers of the conductive-dielectric layer pair, respectively; and An isolation layer covers the first covering layer and the topmost surface of the first stepped portion.

3. The semiconductor device according to claim 2, characterized in that The stacked structure further includes a second stepped portion having a plurality of second stepped surfaces with gradually decreasing heights along the first direction.

4. The semiconductor device according to claim 3, characterized in that Each of the second stepped surfaces and each of the first stepped surfaces are staggered with each other in a second direction, and the second direction is perpendicular to the first direction.

5. The semiconductor device according to claim 4, characterized in that Also includes: The second cover layer is disposed above the first cover layer, covers the top surface of the first cover layer, the topmost surface and a plurality of side walls of the first stepped portion, and exposes the second stepped portion.

6. The semiconductor device according to claim 2, wherein: Also includes: A second step portion, disposed in the stacked structure and having a plurality of second step surfaces with gradually increasing heights along the first direction; An etching stop layer is disposed on the substrate and is located between the first step portion and the second step portion in the vertical direction; as well as The second cover layer is disposed above the first cover layer, covers the top surface of the first cover layer, the topmost surface and a plurality of side walls of the first stepped portion, and exposes the second stepped portion.

7. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately stacked on the substrate to form a plurality of conductive-dielectric layer pairs; forming a first covering layer on the conductive-dielectric layer pair, exposing a first region of the conductive-dielectric layer pair and covering a second region of the conductive-dielectric layer pair; forming a second mask layer on the first covering layer, exposing the first region from a notch portion of the second mask layer; Performing a first etching process through the second mask layer to partially remove one of the conductive-dielectric layer pairs; Repeating the trimming-etching process to form a stacked structure, the stacked structure comprising an array portion formed in the second region and a first stepped portion formed in the first region, the first stepped portion having a plurality of first stepped surfaces with gradually decreasing heights along a first direction; as well as The second mask layer is completely removed.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The trimming-etching process also includes: Performing a trimming process on the second mask layer to enlarge the gap to partially expose the first covering layer and the conductive-dielectric layer pair; and A second etching process is performed through the trimmed second mask layer to partially remove a set of the conductive-dielectric layer pairs again.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: Before forming the second mask layer, the method further includes: forming an etch stop layer on the substrate, vertically disposed on a portion of the conductive-dielectric layer pair; forming a first mask layer on the first covering layer, exposing a third region from the first mask layer, wherein the third region is completely located within the first region; partially removing the portion of the conductive-dielectric layer pair and the etch stop layer through the first mask layer; and The first mask layer is completely removed.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that: Also includes: Partially removing one of the conductive-dielectric layer pairs by the first etching process; Repeat the trimming-etching process until the stacked structure is formed on the second step portion of the third region. forming a plurality of first plugs on the first stepped portion, each of which is electrically connected to the conductive layer of the corresponding conductive-dielectric layer pair; as well as A plurality of second plugs are formed on the second stepped portion and are electrically connected to the conductive layers of the corresponding conductive-dielectric layer pairs of the parts respectively. The first plugs and the second plugs are alternately arranged in a second direction, and the second direction is perpendicular to the first direction.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The second step portion has a plurality of second step surfaces whose heights gradually decrease along the first direction.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: The second step portion has a plurality of second step surfaces with gradually increasing heights along the first direction.

13. The method for manufacturing a semiconductor device according to claim 9, wherein: After forming the first stepped portion, the method further comprises: forming a second covering layer on the first covering layer, covering the topmost surface and sidewalls of the first terrace portion in the first region and exposing the third region; forming another mask layer on the second covering layer, exposing the first region from a notch portion of the another mask layer; and Another trimming-etching process is repeated through the second covering layer and the other mask layer to form a second step portion in the third area in the stacked structure, the second step portion having a plurality of second step surfaces, each of the second step surfaces and each of the first step surfaces being offset from each other in a second direction, and the second direction being perpendicular to the first direction.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: Also includes: forming a plurality of first plugs on the first stepped portion, respectively penetrating the second covering layer covering the first stepped portion and electrically connected to the conductive layer of the corresponding conductive-dielectric layer pair; as well as A plurality of second plugs are formed on the second stepped portion and are electrically connected to the conductive layers of the corresponding conductive-dielectric layer pairs of the portions, respectively. The first plugs and the second plugs are alternately arranged in the second direction.

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