Solid-state memory control method and device and computer readable storage medium
By using a temperature sensor and an SSD controller in solid state memory to stop the chip enablement of high-temperature flash memory particles, the problem of excessive temperature of solid state memory is solved, and the dual effects of temperature reduction and stable performance are achieved.
Patent Information
- Application Number
- CN202411329784.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-01-07
AI Technical Summary
Solid-state memory can cause excessive temperatures when performing large or frequent data operations. The prior art cools down by installing a heat dissipation device or reducing the main control operating frequency. However, the former has poor reliability, while the latter is prone to performance oscillation.
Introducing a temperature sensor in the solid state memory, the SSD controller stops the corresponding flash die set to work and reduces the overall temperature by obtaining the temperature of the flash particles and stops the chip enable pin whose enable temperature exceeds the preset threshold.
It realizes a simple and quick reduction in solid-state memory temperature, avoids performance degradation due to excessive temperature, and does not affect the performance smoothness of the memory.
Smart Images
Figure CN119274614A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to memory technology, and more particularly to a control method and device for a solid-state memory and a computer-readable storage medium. Background Art
[0002] Solid-state memory generates heat when performing data operations, especially when performing large or frequent data operations, such as running large software or games for a long time or performing large-scale data backup, which will cause the solid-state memory to overheat.
[0003] In the related art, a heat dissipation device is often installed on the solid-state memory to accelerate the heat dissipation of the solid-state memory, or the operating frequency of the main control of the solid-state memory is reduced to reduce the heat generation.
[0004] However, the method of adding a heat sink requires reliance on external devices and has poor reliability, while the method of reducing the main control operating frequency is prone to cause solid-state memory performance fluctuations. Summary of the invention
[0005] The present application provides a control method, device and computer-readable storage medium for a solid-state memory, which can reduce the overall temperature of the solid-state memory and avoid performance degradation of the solid-state memory due to excessively high temperature.
[0006] In a first aspect, the present application provides a control method for a solid-state memory, which is applied to a solid-state memory, wherein the solid-state memory comprises: an SSD controller, and a flash memory particle module array; each flash memory particle module in the flash memory particle module array comprises: a flash memory particle and a temperature sensor additionally provided for detecting the temperature of the flash memory particle, or a flash memory particle with a built-in temperature sensor; each flash memory particle comprises: a plurality of groups of flash memory bare chips, each flash memory particle corresponds to a group of chip enable pins, each group of flash memory bare chips corresponds to one chip enable pin in a group of chip enable pins corresponding to the flash memory particle to which it belongs, and each group of flash memory bare chips is connected to the SSD controller through the corresponding chip enable pin; the control method comprises: The SSD controller acquires the detected temperature of the flash memory particle from the temperature sensor of each flash memory particle; The SSD controller stops enabling some chip enable pins in a group of chip enable pins corresponding to flash memory particles whose temperature exceeds a preset temperature threshold, so that the corresponding flash memory die group stops working.
[0007] In a second aspect, the present application provides an SSD controller, comprising: a memory and a processor, wherein the memory is used to store an executable program; The processor is used to read and execute the executable program to implement the solid-state memory control method as described above.
[0008] In a third aspect, the present application provides a computer-readable storage medium, on which computer-executable commands are stored, and the computer-executable commands are used to execute the control method of the solid-state memory as described above.
[0009] Compared with the related art, the SSD controller described in the embodiment of the present application obtains the detected temperature of the corresponding flash memory particle from the temperature sensor of each flash memory particle in the flash memory particle module array, stops enabling some of the chip enable pins in a group of chip enable pins corresponding to the flash memory particles whose temperature exceeds the preset temperature threshold, so as to stop the corresponding flash memory die group from working. The embodiment of the present application can stop working some of the flash memory dies in the flash memory particles with excessively high temperature, thereby playing a role in reducing the temperature of the flash memory particles, thereby realizing the reduction of the overall temperature of the solid-state memory in a simple and quick manner, and avoiding the performance degradation of the solid-state memory due to the high temperature.
[0010] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0012] Figure 1 A schematic flow chart of a control method of a solid-state memory according to an embodiment of the present application; Figure 2 This is a schematic diagram of the structure of a solid-state memory according to an embodiment of the present application; Figure 3 This is a structural schematic diagram of a flash memory particle module according to an embodiment of the present application; Figure 4 This is a schematic diagram of the structure of another flash memory particle module according to an embodiment of the present application; Figure 5 A schematic flow chart of another solid-state memory control method according to an embodiment of the present application; Figure 6 A schematic diagram of a process of selecting a second chip enable pin according to an embodiment of the present application; Figure 7 A flowchart of another solid-state memory control method according to an embodiment of the present application; FIG. 8 is a flow chart of another method for controlling a solid-state memory according to an embodiment of the present application. DETAILED DESCRIPTION
[0013] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.
[0014] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.
[0015] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation for the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.
[0016] In the related art, the heat dissipation method of the solid-state memory is accelerated by adding heat sinks, heat dissipation patches, heat dissipation fans, etc. to the solid-state memory, or the method of lowering the ambient temperature by air conditioning, etc. The cooling effect depends on the quality of the external heat sinks, heat dissipation patches and air conditioners. Once the heat sinks and heat dissipation patches age and fall off, or the fans and air conditioners have problems, the temperature of the solid-state memory cannot be lowered. If the temperature exceeds the tolerance of the solid-state memory, it will cause damage to the solid-state memory hardware. The method of reducing the main control frequency combined with low power consumption will reduce the main control performance, thereby reducing the overall performance of the solid-state memory, making the solid-state memory performance oscillating and not smooth.
[0017] To this end, an embodiment of the present application provides a control method for a solid-state memory, which is applied to a solid-state memory, wherein the solid-state memory includes: an SSD controller, and a flash memory particle module array; each flash memory particle module in the flash memory particle module array includes: a flash memory particle and a temperature sensor for detecting the temperature of the flash memory particle, or a flash memory particle with a built-in temperature sensor; each flash memory particle includes: a plurality of groups of flash memory bare chips, each flash memory particle corresponds to a group of chip enable pins, each group of flash memory bare chips corresponds to one chip enable pin in a group of chip enable pins corresponding to the flash memory particle to which it belongs, and each group of flash memory bare chips is connected to the SSD controller through the corresponding chip enable pin; Figure 1 As shown, the control method includes: Step 101: The SSD controller obtains the detected temperature of each flash memory particle from the temperature sensor of each flash memory particle; Step 102: The SSD controller stops enabling some chip enable pins in a group of chip enable pins corresponding to flash memory particles whose temperature exceeds a preset temperature threshold, so as to stop the corresponding flash memory die group from working.
[0018] Among them, when the flash memory particle is a flash memory particle in a flash memory particle module that is additionally provided with a temperature sensor, the temperature sensor of the flash memory particle refers to the temperature sensor in the flash memory particle module to which it belongs; when the flash memory particle is a flash memory particle with a built-in temperature sensor, the temperature sensor of the flash memory particle refers to the temperature sensor built into the flash memory particle.
[0019] The temperature sensor may detect the temperature in a timed detection manner. When the timed detection manner is adopted, each temperature sensor detects the temperature of the corresponding flash memory particle in a timed manner.
[0020] The structural diagram of solid-state memory can be shown as follows Figure 2 As shown, the solid-state storage includes: an SSD controller 21, and a flash memory particle module array, the flash memory particle module array includes multiple flash memory particle modules 22, each flash memory particle module 22 includes: a flash memory particle 221 and a temperature sensor (not shown) for detecting the temperature of the flash memory particle, or a flash memory particle with a built-in temperature sensor (not shown); each flash memory particle 221 includes: multiple groups of flash memory bare chips (Die) 2211, each flash memory particle corresponds to a group of chip enable pins (CE), each group of flash memory bare chips corresponds to one chip enable pin in a group of chip enable pins corresponding to the flash memory particle to which it belongs, and each group of flash memory bare chips is connected to the SSD controller 21 through the corresponding chip enable pin.
[0021] The structural diagram of the flash memory particle module can be as follows Figure 3As shown, the flash memory particle module 22 includes: a flash memory particle 221 and a temperature sensor 222 additionally provided for detecting the temperature of the flash memory particle. Figure 4 As shown, the flash memory particle module 22 includes a flash memory particle 221 with a built-in temperature sensor 222 .
[0022] Each flash memory module in the flash memory module array can be composed of Figure 3 The flash memory particle module shown is composed of, or can be composed of Figure 4 The flash memory particle module shown is composed of, or may be partially composed of Figure 3 The flash memory particle module shown is composed of another part Figure 4 The flash memory particle module shown is composed of.
[0023] The control method of the solid-state memory provided by the embodiment of the present application, the SSD controller obtains the temperature of the corresponding flash memory particle detected from the temperature sensor of each flash memory particle in the flash memory particle module array, stops enabling some chip enable pins in a group of chip enable pins corresponding to the flash memory particles whose temperature exceeds the preset temperature threshold, so as to stop the corresponding flash memory bare chip group from working. The embodiment of the present application can stop the operation of some flash memory bare chips in the flash memory particles with excessively high temperature, play a role in reducing the temperature of the flash memory particles, thereby realizing the reduction of the overall temperature of the solid-state memory in a simple and quick manner, and avoiding the performance degradation of the solid-state memory caused by too high temperature.
[0024] In an exemplary instance, the preset temperature threshold includes: multiple levels of preset temperature sub-thresholds; wherein each level of preset temperature sub-threshold corresponds to a chip enable pin stop enable ratio, and the chip enable pin stop enable ratio corresponding to the low-level preset temperature sub-threshold is smaller than the chip enable pin stop enable ratio corresponding to the high-level preset temperature sub-threshold.
[0025] Exemplarily, the multi-level preset temperature sub-thresholds may include: 60°C, 70°C, 80°C, and 90°C. The chip enable pin stop enable ratio corresponding to the preset temperature sub-threshold of 60°C may be 20%, the chip enable pin stop enable ratio corresponding to the preset temperature sub-threshold of 70°C may be 40%, the chip enable pin stop enable ratio corresponding to the preset temperature sub-threshold of 80°C may be 60%, and the chip enable pin stop enable ratio corresponding to the preset temperature sub-threshold of 90°C may be 80%.
[0026] In an exemplary embodiment, the stop enabling temperature exceeds a preset temperature threshold of the flash memory particles corresponding to a group of chip enable pins of some chip enable pins, including: Step 102a, selecting a target preset temperature sub-threshold for evaluating the temperatures of all flash memory particles from the multiple levels of preset temperature sub-thresholds, and acquiring a first target flash memory particle whose temperature exceeds the target preset temperature sub-threshold; Step 102b: according to the chip enable pin stop enable ratio corresponding to the target preset temperature sub-threshold, stop enabling the chip enable pins in a group of chip enable pins corresponding to the first target flash memory particle, so that the corresponding flash memory die group stops working.
[0027] Exemplarily, taking the multi-level preset temperature sub-thresholds and the corresponding chip enable pin stop enable ratios in the above-mentioned embodiment as an example, assuming that the target preset temperature sub-threshold for evaluating the temperature of all flash memory particles is 60°C, a flash memory particle with a temperature exceeding 60°C is obtained and used as the first target flash memory particle, and since the chip enable pin stop enable ratio corresponding to 60°C is 20%, 20% of the chip enable pins in a group of chip enable pins corresponding to the first target flash memory particle are stopped from being enabled, so that the corresponding flash memory die group stops working.
[0028] In an exemplary embodiment, selecting a target preset temperature sub-threshold for evaluating the temperature of all flash memory particles from the multiple levels of preset temperature sub-thresholds includes: Step 102a1, starting from the lowest level preset sub-threshold, using two adjacent level preset sub-thresholds and the temperatures of all flash memory particles for comparison; Step 102a2: When the temperature of at least one flash memory particle exceeds a lower preset sub-threshold in an adjacent level preset sub-threshold, and the temperatures of all flash memory particles do not exceed a higher preset sub-threshold in the same adjacent level preset sub-threshold, the lower preset sub-threshold in the adjacent level preset sub-threshold is selected as the target preset temperature sub-threshold.
[0029] Exemplarily, still taking the multi-level preset temperature sub-thresholds and the corresponding chip enable pin stop enable ratio in the above embodiment as an example, the preset sub-thresholds of two adjacent levels: 60°C, 70°C and the temperatures of all flash memory particles are compared. When the temperature of at least one flash memory particle exceeds 60°C and the temperatures of all flash memory particles do not exceed 70°C, 60°C is selected as the target preset temperature sub-threshold; otherwise, the preset sub-thresholds of two adjacent levels: 70°C, 80°C and the temperatures of all flash memory particles are compared. When the temperature of at least one flash memory particle exceeds 70°C and the temperatures of all flash memory particles do not exceed 80°C, 70°C is selected as the target preset temperature sub-threshold; otherwise, the preset sub-thresholds of two adjacent levels: 80°C, 90°C and the temperatures of all flash memory particles are compared. When the temperature of at least one flash memory particle exceeds 80°C and the temperatures of all flash memory particles do not exceed 90°C, 80°C is selected as the target preset temperature sub-threshold.
[0030] In an exemplary embodiment, after the chip enable pins corresponding to the target preset temperature sub-threshold are stopped enabling a ratio, and the chip enable pins in a group of chip enable pins corresponding to the first target flash memory particles are stopped enabling, as follows: Figure 5 As shown, the control method also includes: Step 301: when the temperature of at least one flash memory particle does not exceed a target preset temperature sub-threshold, obtaining a second target flash memory particle whose temperature does not exceed the target preset temperature sub-threshold; Step 302: Calculate the number of disabled first chip enable pins on the first target flash memory particle; Step 303: Determine the number of second chip enable pins used to replace the first chip enable pins according to the calculated number of the first chip enable pins; Step 304: select a second chip enable pin on the second target flash memory particle to replace the first chip enable pin according to the number of the second chip enable pins, and record the correspondence between the identification information of the first chip enable pin and the identification information of the second chip enable pin.
[0031] When the temperature of at least one flash memory particle does not exceed the target preset temperature sub-threshold, it indicates that there is a flash memory particle on which the second chip enable pin for replacing the first chip enable pin can be selected. When the temperature of no flash memory particle does not exceed the target preset temperature sub-threshold, it indicates that there is no flash memory particle on which the second chip enable pin for replacing the first chip enable pin can be selected, that is, each flash memory particle is a first target flash memory particle, and therefore some chip enable pins in a group of chip enable pins corresponding to each flash memory particle can be stopped from being enabled.
[0032] Exemplarily, the number of disabled first chip enable pins on the first target flash memory particle can be calculated by the chip enable pin disable ratio corresponding to the target preset temperature sub-threshold and the number of chip enable pins on the first target flash memory particle (all chip enable pins are enabled by default in the initial state).
[0033] Exemplarily, the identification information refers to information that can uniquely identify a chip enable pin, and may include information for indicating a connected flash memory particle, and information for indicating the chip enable pin in a group of chip enable pins corresponding to the connected flash memory particle.
[0034] The correspondence between the identification information of the first chip enable pin and the identification information of the second chip enable pin may be recorded and saved in the form of a table, which is convenient for subsequent use.
[0035] In an exemplary embodiment, step 303 includes: determining the number of the second chip enable pins according to the calculated number of the first chip enable pins.
[0036] When the number of the second chip enable pins is equal to the calculated number of the first chip enable pins, each of the first chip enable pins can be replaced by a second chip enable pin.
[0037] In an exemplary embodiment, step 303 includes: determining a number that is less than the calculated number of the first chip enable pins as the number of the second chip enable pins.
[0038] When the number of the second chip enable pins is less than the calculated number of the first chip enable pins, there must be a situation where one or more first chip enable pins are replaced by one second chip enable pin.
[0039] The number less than the calculated number of the first chip enable pins may be 1 / k of the calculated number of the first chip enable pins, where k is a positive integer. For example, the number of first chip enable pins is N, and the number of second chip enable pins is (1 / k)*N, then every N / k first chip enable pins are replaced by one second chip enable pin.
[0040] In an exemplary embodiment, the selecting, on the second target flash memory particle according to the number of the second chip enable pins, the second chip enable pin for replacing the first chip enable pin includes: When there are multiple second target flash memory particles, at least one second target flash memory particle is arbitrarily selected from the multiple second target flash memory particles, and a second chip enable pin for replacing the first chip enable pin is selected on the selected second target flash memory particle according to the number of second chip enable pins.
[0041] Randomly selecting at least one second target flash memory particle from a plurality of second target flash memory particles includes: randomly selecting any one second target flash memory particle from a plurality of second target flash memory particles, or randomly selecting any multiple second target flash memory particles from a plurality of second target flash memory particles. When randomly selecting a second target flash memory particle from a plurality of second target flash memory particles, a second chip enable pin can be selected on the selected second target flash memory particle according to the number of second chip enable pins to replace the first chip enable pin; when randomly selecting multiple second target flash memory particles from a plurality of second target flash memory particles, at least one second chip enable pin can be selected on each selected second target flash memory particle to replace the first chip enable pin, and the total number of second chip enable pins selected on all selected second target flash memory particles is equal to the number of second chip enable pins previously determined.
[0042] In an exemplary embodiment, the selecting, on the second target flash memory particle according to the number of the second chip enable pins, the second chip enable pin for replacing the first chip enable pin includes: When there are multiple second target flash memory particles, second chip enable pins for replacing the first chip enable pins are selected on all second target flash memory particles according to the temperatures of all second target flash memory particles and the number of the second chip enable pins; wherein the number of the second chip enable pins selected on the second target flash memory particles with higher temperatures is less than the number of the second chip enable pins selected on the second target flash memory particles with lower temperatures.
[0043] Exemplarily, assuming that the number of the second target flash memory particles is 3, recorded as flash memory particles A, flash memory particles B and flash memory particles C, and the temperature of flash memory particles A is the lowest and the temperature of flash memory particles B is the highest, then the second chip enable pins selected on flash memory particles A are the largest, the second chip enable pins selected on flash memory particles B are the smallest, and the sum of the second chip enable pins selected on flash memory particles A, flash memory particles B and flash memory particles C is equal to the number of determined second chip enable pins. Taking the number of second chip enable pins as 10 as an example, the actual selection method may be to select 5 second chip enable pins on flash memory particles A, 2 second chip enable pins on flash memory particles B, and 3 second chip enable pins on flash memory particles C.
[0044] In an exemplary embodiment, Figure 6 As shown, the selecting, on all second target flash memory particles, second chip enable pins for replacing the first chip enable pins according to the temperatures of all second target flash memory particles and the number of the second chip enable pins includes: Step 401: acquiring the replacement weights corresponding to all second target flash memory particles from a preset weight set according to the temperatures of all second target flash memory particles, or calculating the replacement weights corresponding to all second target flash memory particles according to the temperatures of all second target flash memory particles; Step 402: Calculate the number of second chip enable pins to be selected on each second target flash memory particle according to the obtained replacement weights corresponding to all second target flash memory particles and the number of the second chip enable pins; Step 403: Select a corresponding number of second chip enable pins on the corresponding second target flash memory particles according to the calculated number of second chip enable pins to be selected on each second target flash memory particle.
[0045] Exemplarily, when the replacement weights corresponding to all second target flash memory particles are obtained from a preset weight set according to the temperature of all second target flash memory particles, the number of weights in the weight set may be equal to the number of all second target flash memory particles. It is still assumed that the number of the second target flash memory particles is 3, recorded as flash memory particle A, flash memory particle B and flash memory particle C, and the temperature of flash memory particle A is the lowest, the temperature of flash memory particle B is the highest, and the weight set is (w1, w2, w3), w1, w2, w3 in descending order. Since the temperature of flash memory particle A is the lowest, the largest replacement weight, i.e., w1, is assigned to flash memory particle A. Since the temperature of flash memory particle B is the highest, the smallest replacement weight, i.e., w3, is assigned to flash memory particle B, and w2 is assigned to flash memory particle C.
[0046] Therefore, assuming that the number of the second chip enable pins is N, the number of the second chip enable pins to be selected on the flash memory particle A is N* , the number of second chip enable pins to be selected on flash memory particle B is N* , the number of second chip enable pins to be selected on the flash memory particle C is N* .
[0047] Exemplarily, when calculating the replacement weights corresponding to all second target flash memory particles according to the temperatures of all second target flash memory particles, it actually involves a weighted average method. When calculating the replacement weights corresponding to all second target flash memory particles according to the temperatures of all second target flash memory particles, it is still assumed that the number of the second target flash memory particles is 3, recorded as flash memory particle A, flash memory particle B and flash memory particle C, and the temperature of flash memory particle A is t1, the temperature of flash memory particle B is t2, and the temperature of flash memory particle C is t3. The temperature is inversely proportional to the replacement weight. Therefore, 1 / t1 can be used as the replacement weight of flash memory particle A, 1 / t2 can be used as the replacement weight of flash memory particle B, and 1 / t3 can be used as the replacement weight of flash memory particle C. Therefore, assuming that the number of the second chip enable pins is N, the number of the second chip enable pins to be selected on the flash memory particle A is N* , the number of second chip enable pins to be selected on flash memory particle B is N* , the number of second chip enable pins to be selected on the flash memory particle C is N* .
[0048] In an exemplary embodiment, after selecting the second chip enable pin to replace the first chip enable pin, Figure 7 As shown, the control method also includes: Step 501: when it is necessary to perform data operation on a corresponding flash memory die group through a first chip enable pin on a first target flash memory particle, obtain identification information of a second chip enable pin for replacing the first chip enable pin according to the corresponding relationship; Step 502: determine the second chip enable pin according to the obtained identification information of the second chip enable pin, and perform data operation on the corresponding flash memory die through the determined second chip enable pin.
[0049] Since the first chip enable pin on the first target flash memory particle has stopped being enabled, when it is necessary to perform data operations on the corresponding flash memory die group through the first chip enable pin on the first target flash memory particle, it is necessary to obtain identification information of the second chip enable pin used to replace the first chip enable pin, and then determine the second chip enable pin, and perform the data operation originally intended to be performed on the flash memory die group corresponding to the first chip enable pin on the first target flash memory particle on the corresponding flash memory die group through the determined second chip enable pin.
[0050] The embodiment of the present application further provides a control method for a solid-state memory, taking four levels of preset temperature sub-thresholds (respectively T1, T2, T3, and T4) as an example, as shown in FIG8, including: Step 601, regularly detecting the temperature of all flash memory particles; Step 602, determining whether there is a flash memory particle with a temperature greater than T1 and not greater than T2, if there is a flash memory particle with a temperature greater than T1 and not greater than T2, executing step 603, if there is no flash memory particle with a temperature greater than T1 and not greater than T2, executing step 607; Step 603, determining whether there are other flash memory particles with a temperature not greater than T1, if there are other flash memory particles with a temperature not greater than T1, executing step 604, if the temperatures of other flash memory particles are greater than T1, executing step 605; Step 604: stop enabling the number of CEs with a P1 ratio on the flash memory particle, and replace them with CEs on other flash memory particles with a temperature not greater than T1 by an average weighted method, and execute step 606; Step 605: stop enabling the CE number of P1 ratio on all flash memory particles, and execute step 606; Step 606, determining whether the temperature of all flash memory particles is not greater than T2, if the temperature of all flash memory particles is not greater than T2, executing step 621, if there is a flash memory particle whose temperature is greater than T2, executing step 607; Step 607, determining whether there is a flash memory particle with a temperature greater than T2 and not greater than T3, if there is a flash memory particle with a temperature greater than T2 and not greater than T3, executing step 608, if there is no flash memory particle with a temperature greater than T2 and not greater than T3, executing step 612; Step 608, determining whether there are other flash memory particles with a temperature not greater than T2, if there are other flash memory particles with a temperature not greater than T2, executing step 609, if the temperatures of other flash memory particles are greater than T2, executing step 610; Step 609: stop enabling the number of CEs with a P2 ratio on the flash memory particle, and replace them with CEs on other flash memory particles with a temperature not greater than T2 by an average weighted method, and execute step 611; Step 610: stop enabling the number of CEs of the P2 ratio on all flash memory particles, and execute step 611; Step 611, determine whether the temperature of all flash memory particles is not greater than T3, if the temperature of all flash memory particles is not greater than T3, execute step 621, if there is a flash memory particle whose temperature is greater than T3, execute step 612; Step 612, determining whether there is a flash memory particle with a temperature greater than T3 and not greater than T4, if there is a flash memory particle with a temperature greater than T3 and not greater than T4, executing step 613, if there is no flash memory particle with a temperature greater than T3 and not greater than T4, executing step 617; Step 613, determining whether there are other flash memory particles with a temperature not greater than T3, if there are other flash memory particles with a temperature not greater than T3, executing step 614, if the temperatures of other flash memory particles are greater than T3, executing step 615; Step 614: stop enabling the number of CEs with a P3 ratio on the flash memory particle, and replace them with CEs on other flash memory particles with a temperature not greater than T3 by an average weighted method, and execute step 616; Step 615: stop enabling the CE number of the P3 ratio on all flash memory particles, and execute step 616; Step 616, determining whether the temperature of all flash memory particles is not greater than T4, if the temperature of all flash memory particles is not greater than T4, executing step 621, if there is a flash memory particle whose temperature is greater than T4, executing step 617; Step 617, determining whether there is a flash memory particle with a temperature greater than T4, if there is a flash memory particle with a temperature greater than T4, executing step 618; Step 618, determining whether there are other flash memory particles with a temperature not greater than T4, if there are other flash memory particles with a temperature not greater than T4, executing step 619, if the temperatures of other flash memory particles are greater than T4, executing step 620; Step 619: stop enabling the number of CEs of the P4 ratio on the flash memory particle, and replace them with CEs on other flash memory particles whose temperature is not greater than T4 by an average weighted method, and execute step 621; Step 620, turn off the power supply; Step 621: Maintain the current state and run stably.
[0051] The control method of the solid-state memory provided in the embodiment of the present application is that the solid-state memory will periodically detect the temperature of all flash memory particles. When the temperature of a flash memory particle exceeds T1 (for example, 60°C), the firmware checks the temperature of the remaining flash memory particles. When there are other flash memory particles whose temperatures are not greater than (less than or equal to) T1, the number of CEs of the flash memory particle P1 ratio (for example, 20%) is stopped from being enabled, and the CEs on other flash memory particles whose temperatures are not greater than T1 are replaced by the average weighted method. When the temperatures of other flash memory particles are all greater than T1, the number of CEs of each flash memory particle P1 ratio is stopped from being enabled. When the temperature of all flash memory particles is not greater than T2 (for example, 70°C), the solid-state memory maintains the current state and runs stably. When the temperature of the flash memory particles continues to rise, and the temperature of some flash memory particles is greater than T2, the firmware checks the temperature of the remaining flash memory particles. If the temperature of other flash memory particles is not greater than T2, the firmware stops enabling the number of CEs of the P2 ratio (for example, 40%) of the flash memory particles, and replaces them with CEs on other flash memory particles with a temperature not greater than T2 through an average weighted method. When the temperature of other flash memory particles is greater than T2, the firmware stops enabling the number of CEs of the P2 ratio of each flash memory particle. When the temperature of all flash memory particles is not greater than T3 (for example, 80°C), the solid-state storage maintains the current state and runs stably. When the temperature of the flash memory particles continues to rise and the temperature of some flash memory particles is greater than T3, the firmware checks the temperature of the remaining flash memory particles. If the temperature of other flash memory particles is not greater than T3, the firmware stops enabling the CE quantity of the flash memory particle P3 ratio (for example, 60%), and replaces it with the CE on other flash memory particles with a temperature not greater than T3 through the average weighted method. When the temperature of other flash memory particles is greater than T3, the firmware stops enabling the CE quantity of each flash memory particle P3. When the temperature of all flash memory particles is not greater than T4 (for example, 90°C), the solid-state storage maintains the current state and runs stably. When the temperature of the flash memory particles continues to rise and the temperature of some flash memory particles is greater than T4, the firmware checks the temperature of the remaining flash memory particles. If the temperature of other flash memory particles is not greater than T4, the firmware stops enabling the number of CEs of each flash memory particle P4 (for example, 80%), and replaces them with CEs on other flash memory particles with a temperature not greater than T4 through the average weighted method. When the temperature of all flash memory particles is greater than T4, the power supply of the solid-state storage is turned off through the main control chip.
[0052] The control method of the solid-state memory provided in the embodiment of the present application is that when the solid-state memory is running, it will periodically measure the temperature of all flash memories of the solid-state memory and record the temperature information inside the firmware. When the temperature reaches a specific situation, such as T1 (temperature1), T2 (temperature2), T3 (temperature3), T4 (temperature4), the firmware will dynamically replace the CE on the flash memory particles with high temperatures with the CE on other flash memory particles with low temperatures through an average weighted algorithm, while reducing the overall temperature of the solid-state memory, achieving smooth performance without oscillation, and avoiding damage to the solid-state memory hardware caused by excessive temperature.
[0053] An embodiment of the present application provides an SSD controller, comprising: a memory and a processor, wherein the memory is used to store an executable program; The processor is used to read and execute the executable program to implement the control method of the solid-state memory as described in any of the above embodiments.
[0054] The SSD controller provided in the embodiment of the present application obtains the temperature of the corresponding flash memory particle detected from the temperature sensor of each flash memory particle in the flash memory particle module array, stops enabling some chip enable pins in a group of chip enable pins corresponding to the flash memory particles whose temperature exceeds the preset temperature threshold, so as to stop the corresponding flash memory bare chip group from working. The embodiment of the present application can stop working some flash memory bare chips in the flash memory particles with excessively high temperature, play a role in reducing the temperature of the flash memory particles, thereby realizing the reduction of the overall temperature of the solid-state memory in a simple and quick manner, and avoiding the performance degradation of the solid-state memory due to the excessively high temperature.
[0055] An embodiment of the present application further provides a computer-readable storage medium, on which computer-executable commands are stored, and the computer-executable commands are used to execute the control method of the solid-state memory as described in any of the above embodiments.
[0056] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
Claims
1. A control method for a solid-state memory, characterized in that: Applied to a solid-state memory, the solid-state memory comprises: an SSD controller, and a flash memory particle module array; each flash memory particle module in the flash memory particle module array comprises: a flash memory particle and a temperature sensor additionally provided for detecting the temperature of the flash memory particle, or a flash memory particle with a built-in temperature sensor; each flash memory particle comprises: a plurality of groups of flash memory bare chips, each flash memory particle corresponds to a group of chip enable pins, each group of flash memory bare chips corresponds to one chip enable pin in a group of chip enable pins corresponding to the flash memory particle, and each group of flash memory bare chips is connected to the SSD controller through the corresponding chip enable pin; the control method comprises: The SSD controller acquires the detected temperature of the flash memory particle from the temperature sensor of each flash memory particle; The SSD controller stops enabling some chip enable pins in a group of chip enable pins corresponding to flash memory particles whose temperature exceeds a preset temperature threshold, so that the corresponding flash memory die group stops working.
2. The control method according to claim 1, characterized in that: The preset temperature threshold comprises: a plurality of preset temperature sub-thresholds; wherein each level of preset temperature sub-threshold corresponds to a chip enable pin stop enable ratio, and the chip enable pin stop enable ratio corresponding to the low-level preset temperature sub-threshold is smaller than the chip enable pin stop enable ratio corresponding to the high-level preset temperature sub-threshold; Part of the chip enable pins in a group of chip enable pins corresponding to the flash memory particles whose enabling temperature exceeds a preset temperature threshold include: Selecting a target preset temperature sub-threshold for evaluating the temperature of all flash memory particles from the multiple levels of preset temperature sub-thresholds, and acquiring a first target flash memory particle whose temperature exceeds the target preset temperature sub-threshold; According to the chip enable pin stop enable ratio corresponding to the target preset temperature sub-threshold, the chip enable pins in a group of chip enable pins corresponding to the first target flash memory particle are stopped to stop the corresponding flash memory die group from working.
3. The control method according to claim 2, characterized in that: The step of selecting a target preset temperature sub-threshold for evaluating the temperature of all flash memory particles from the multiple levels of preset temperature sub-thresholds includes: Starting from the lowest level preset sub-threshold, using two adjacent level preset sub-thresholds and the temperature of all flash memory particles for comparison; When the temperature of at least one flash memory particle exceeds a lower preset sub-threshold in an adjacent level preset sub-threshold, and the temperatures of all flash memory particles do not exceed a higher preset sub-threshold in the same adjacent level preset sub-threshold, the lower preset sub-threshold in the adjacent level preset sub-threshold is selected as the target preset temperature sub-threshold.
4. The control method according to claim 2, characterized in that: After stopping enabling the chip enable pins in a group of chip enable pins corresponding to the first target flash memory particles according to the chip enable pin stop enabling ratio corresponding to the target preset temperature sub-threshold, the control method further includes: When the temperature of at least one flash memory particle does not exceed the target preset temperature sub-threshold, acquiring a second target flash memory particle whose temperature does not exceed the target preset temperature sub-threshold; Calculating the number of disabled first chip enable pins on the first target flash memory particle; determining the number of second chip enable pins used to replace the first chip enable pins according to the calculated number of the first chip enable pins; A second chip enable pin for replacing the first chip enable pin is selected on the second target flash memory particle according to the number of the second chip enable pins, and a corresponding relationship between identification information of the first chip enable pin and identification information of the second chip enable pin is recorded.
5. The control method according to claim 4, characterized in that: The determining, according to the calculated number of the first chip enable pins, the number of second chip enable pins used to replace the first chip enable pins comprises: Determining the number of the second chip enable pins according to the calculated number of the first chip enable pins; Alternatively, a number that is less than the calculated number of the first chip enable pins is determined as the number of the second chip enable pins.
6. The control method according to claim 4, characterized in that: The selecting, according to the number of the second chip enable pins, the second chip enable pin on the second target flash memory particle for replacing the first chip enable pin comprises: When there are multiple second target flash memory particles, arbitrarily select at least one second target flash memory particle from the multiple second target flash memory particles, and select a second chip enable pin for replacing the first chip enable pin on the selected second target flash memory particle according to the number of second chip enable pins; Alternatively, when there are multiple second target flash memory particles, second chip enable pins are selected on all second target flash memory particles to replace the first chip enable pins according to the temperatures of all second target flash memory particles and the number of second chip enable pins; wherein the number of second chip enable pins selected on second target flash memory particles with higher temperatures is less than the number of second chip enable pins selected on second target flash memory particles with lower temperatures.
7. The control method according to claim 6, characterized in that: The selecting, on all second target flash memory particles, second chip enable pins for replacing the first chip enable pins according to the temperatures of all second target flash memory particles and the number of the second chip enable pins comprises: Obtaining the replacement weights corresponding to all the second target flash memory particles from a preset weight set according to the temperatures of all the second target flash memory particles, or calculating the replacement weights corresponding to all the second target flash memory particles according to the temperatures of all the second target flash memory particles; Calculate the number of second chip enable pins to be selected on each second target flash memory cell according to the obtained replacement weights corresponding to all the second target flash memory cells and the number of the second chip enable pins; A corresponding number of second chip enable pins are selected on the corresponding second target flash memory particles according to the calculated number of second chip enable pins to be selected on each second target flash memory particle.
8. The control method according to claim 4, characterized in that: After selecting the second chip enable pin for replacing the first chip enable pin, the control method further includes: When it is necessary to perform data operation on the corresponding flash memory die group through the first chip enable pin on the first target flash memory particle, obtaining identification information of a second chip enable pin used to replace the first chip enable pin according to the corresponding relationship; The second chip enable pin is determined according to the obtained identification information of the second chip enable pin, and data operation is performed on the corresponding flash memory die through the determined second chip enable pin.
9. An SSD controller, characterized in that: include: A memory and a processor, wherein the memory is used to store an executable program; The processor is used to read and execute the executable program to implement the control method of the solid-state memory according to any one of claims 1 to 8.
10. A computer-readable storage medium, characterized in that: The readable storage medium stores computer executable commands, and the computer executable commands are used to execute the control method of the solid-state memory according to any one of claims 1 to 8.