Pixel circuit, driving method thereof and ultrasonic imaging device

Abstract

The invention provides a pixel circuit, a driving method thereof and an ultrasonic imaging device, and the pixel circuit comprises a receiving transducer which is configured to convert a detected ultrasonic signal into an electric signal; the control circuit is configured to provide a detection voltage corresponding to the electric signal to the first node, the control circuit comprises a first switch tube, the first switch tube is an oxide thin film transistor and comprises a first control end and a second control end which are mutually independent, the first control end is used for controlling the first switch tube to be switched on or switched off, and the second control end is used for controlling the second switch tube to be switched off; the second control end is used for adjusting the threshold voltage of the first switching tube; the charge storage circuit is used for storing electric energy so as to lock the first node at a high potential; and the reading circuit is configured to convert an electric signal related to the potential of the first node into a current signal and output the current signal to the detection output end. According to the scheme provided by the invention, the leakage current at the node can be maintained, so that the signal maintaining capability of the large-area ultrasonic imaging device is improved.

Description

Technical Field

[0001] The present application relates to the field of ultrasonic imaging technology, and more specifically, to a pixel circuit and a driving method thereof, and an ultrasonic imaging device. Background Art

[0002] Medical ultrasound imaging usually uses linear array probes and is achieved through mechanical scanning, which has low imaging speed and limited detection resolution. Based on this, the implementation of large-area and refined ultrasound imaging devices is studied, so that the distribution of spatial acoustic signals can be obtained with a single sampling.

[0003] Since the array size of large-area devices is large, and the pixel size is small in order to improve the resolution, there are more pixel rows, and it takes 200ms or even longer to complete a scan. In other words, the reading time of the last row differs from that of the first row by at least 200ms or more. Figure 1 The 4T1C pixel circuit design shown in Figure 1 In the circuit shown, the stable maintenance of the gate potential of the switch tube M3 is very important for imaging. In addition, the switch tube M2 adopts an oxide thin film transistor (Oxide Thin Film Transistor, OTFT), which can reduce leakage current and improve signal retention rate.

[0004] However, the oxide characteristics in the Low-Temperature Polycrystalline Oxide (LTPO) process structure are not very stable. When debugging and improving the process, the threshold voltage of the switch tube is prone to shift, which will cause the leakage current at node 1 in the circuit to be unable to be maintained, thereby losing its signal holding function. Therefore, how to improve and optimize the characteristics of the oxide in the pixel circuit is particularly important. Summary of the invention

[0005] The present application provides a pixel circuit and a driving method thereof, and an ultrasonic imaging device, which maintain leakage current at a node, so that the pixel circuit can output a more uniform current signal, thereby improving the signal retention capability of a large-area ultrasonic imaging device.

[0006] In a first aspect, a pixel circuit is provided, comprising: a receiving transducer, a control circuit, a charge storage circuit and a reading circuit, wherein the output end of the receiving transducer is connected to the input end of the control circuit, and the output end of the control circuit is connected to the input end of the charge storage circuit and the reading circuit, wherein the connection point of the output end of the control circuit, the charge storage circuit and the input end of the reading circuit is a first node. The receiving transducer is configured to convert the detected ultrasonic signal into an electrical signal; the control circuit is configured to provide a detection voltage corresponding to the electrical signal to the first node, wherein the control circuit comprises a first switch tube, the first switch tube is an oxide thin film transistor, the first switch tube comprises a first control end and a second control end which are independent of each other, the first control end is used to control the conduction or shutoff of the first switch tube, and the second control end is used to adjust the threshold voltage of the first switch tube; the charge storage circuit is used to store electrical energy to lock the first node to a high potential; the reading circuit is configured to convert the electrical signal related to the potential of the first node into a current signal and output it to the detection output end.

[0007] In combination with the first aspect, in a possible implementation, the control circuit also includes a second switch tube; the first control end of the first switch tube is electrically connected to the first signal end, the second control end of the first switch tube is electrically connected to the second signal end, the first end of the first switch tube is electrically connected to the receiving transducer, and the second end of the first switch tube is electrically connected to the first node; the control end of the second switch tube is electrically connected to the third signal end, the first end of the second switch tube is electrically connected to the fourth signal end, the second end of the second switch tube is electrically connected to the second node, and the second node is the connection point between the receiving transducer and the first switch tube.

[0008] In combination with the first aspect, in a possible implementation manner, the charge storage circuit includes a storage capacitor; a first electrode of the storage capacitor is electrically connected to the first node, and a second electrode of the storage capacitor is connected to a reference ground.

[0009] In combination with the first aspect, in a possible implementation, the reading circuit includes a third switch tube and a fourth switch tube; the control end of the third switch tube is electrically connected to the first node, the first end of the third switch tube is electrically connected to the fifth signal end, and the second end of the third switch tube is electrically connected to the first end of the fourth switch tube; the control end of the fourth switch tube is electrically connected to the sixth signal end, the first end of the fourth switch tube is electrically connected to the second end of the third switch tube, and the second end of the fourth switch tube is electrically connected to the detection output end.

[0010] In combination with the first aspect, in a possible implementation manner, the signal output by the second signal terminal is adjusted according to the current signal output by the detection output terminal.

[0011] In combination with the first aspect, in a possible implementation manner, the switch tubes other than the first switch tube in the pixel circuit are low-temperature polycrystalline silicon thin film transistors.

[0012] In a second aspect, a driving method for a pixel circuit is provided, the driving method being applied to the pixel circuit in the first aspect or any possible implementation of the first aspect, the driving cycle of the pixel circuit comprising a reset phase, a sampling phase, a holding phase and a reading phase, the driving method comprising: in the reset phase, controlling the control circuit to write a low-level signal provided by a fourth signal terminal into a first node; in the sampling phase, controlling the control circuit to write a high-level signal provided by the fourth signal terminal into the charge storage circuit; in the holding phase, controlling the control circuit to be in an off state so that the potential of the first node maintains a high potential in the sampling phase, and controlling the low-level signal provided by the second signal terminal to be input into the second control terminal of the first switch tube of the control circuit to adjust the threshold voltage of the first switch tube; in the reading phase, controlling the reading circuit to be in an on state so that the electrical signal related to the potential of the first node is converted into a current signal and output to the detection output terminal.

[0013] In combination with the second aspect, in a possible implementation, the method further includes: in the reset phase and the sampling phase, controlling the second signal terminal to output a preset voltage to the second control terminal of the first switch tube so that the first switch tube maintains a threshold voltage of the current phase.

[0014] In a third aspect, an ultrasonic imaging device is provided, comprising: a substrate and a plurality of pixel units, each of the pixel units comprising the pixel circuit described in the first aspect or any possible design of the first aspect.

[0015] In an embodiment of the present application, the receiving transducer converts the detected signal into an electrical signal, and the control circuit can provide a detection voltage corresponding to the electrical signal to the first node. Since the first switch tube of the control circuit includes two independent control terminals, that is, the first control terminal and the second control terminal are independent of each other, and the second control terminal can be used to adjust the threshold voltage of the first switch tube, the threshold voltage of the first switch tube can be effectively adjusted. In this way, the leakage current at the first node can be maintained, and the reading circuit outputs the current signal converted from the electrical signal related to the potential of the first node to the detection output terminal. As a result, the uniformity of the current signal output by the reading circuit to the detection output terminal can be improved, thereby improving the signal retention capability of the large-area ultrasonic imaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the drawings without paying creative work.

[0017] Figure 1 It is a structural schematic diagram of a pixel circuit.

[0018] Figure 2 It is a structural schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0019] Figure 3 It is a circuit diagram of a pixel circuit provided in an embodiment of the present application.

[0020] Figure 4 It is a schematic diagram of a driving method of a pixel circuit provided in an embodiment of the present application.

[0021] Figure 5 A schematic diagram of a threshold voltage shift provided in an embodiment of the present application

[0022] Figure 6 Schematic diagram of the control signal timing of the pixel circuit provided in the embodiment of the present application.

[0023] Figures 7 to 10 A schematic diagram of the states of a pixel circuit in different stages provided in an embodiment of the present application.

[0024] Fig.11 A schematic structural diagram of a dual-gate structure TFT device provided in an embodiment of the present application.

[0025] Fig.12 A schematic structural diagram of a pixel circuit provided in an embodiment of the present application.

[0026] Description of reference numerals:

[0027] 10 - receiving transducer, 20 - control circuit, 30 - charge storage circuit, 40 - reading circuit. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0029] The terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one, two or more. The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0030] References to "one embodiment", "some embodiments", "one embodiment" or "some embodiments" etc. described in the embodiments of the present application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0031] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0032] The ordinal numbers such as "first", "second", "third" and the like used in the embodiments of the present disclosure do not indicate any order, quantity or importance. They are provided to avoid confusion of constituent elements, rather than to limit the quantity. Similar words do not indicate any order, quantity or importance, but are only used to distinguish different components. Similar words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0033] In the description of the embodiments of the present application, "electrical connection" includes the situation where the components are electrically connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transfer electrical signals between the electrically connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0034] If not otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0035] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0036] In the circuit structure provided in the embodiments of the present disclosure, the switching tube used in the circuit structure can be a thin film transistor (Thin Film Transistor, TFT), a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), a gallium nitride (Gallium Nitride, GaN) high electron mobility transistor (High Electron Mobility Transistor, HEMT) or other switching devices with the same characteristics.

[0037] In the circuit structure provided in the embodiment of the present disclosure, the first electrode of each switch tube is one of the source and the drain, and the second electrode of each switch tube is the other of the source and the drain. Since the source and the drain of the switch tube can be symmetrical in structure, the source and the drain can be indistinguishable in structure, that is, the first electrode and the second electrode of the switch tube in the embodiment of the present disclosure can be indistinguishable in structure. Exemplarily, the first electrode of the switch tube is the source, and the second electrode is the drain, or the first electrode of the switch tube is the drain, and the second electrode is the source.

[0038] In the circuit structure provided by the embodiments of the present disclosure, the first node, the second node and other nodes do not represent actual existing components, but represent related connected junctions in the circuit diagram, that is, these nodes are nodes formed by the equivalent of related connected junctions in the circuit diagram.

[0039] The switch tubes included in the circuit structure provided in the embodiment of the present disclosure may all be N-type switch tubes, or may all be P-type switch tubes. In the present disclosure, the P-type switch tube can be turned on under the control of a low-level signal, and the N-type switch tube can be turned on under the control of a high-level signal. The following is a schematic description of the circuit structure provided in the embodiment of the present disclosure, in which the switch tubes are all N-type switch tubes.

[0040] The present application embodiments will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0041] Medical ultrasound imaging usually uses linear array probes and is achieved through mechanical scanning, which has low imaging speed and limited detection resolution. Based on this, the implementation of large-area and refined ultrasound imaging devices is studied, so that the distribution of spatial acoustic signals can be obtained with a single sampling.

[0042] Since the array size of large-area devices is large, and the pixel size is small in order to improve the resolution, there are more pixel rows, and it takes 200ms or even longer to complete a scan. In other words, the reading time of the last row differs from that of the first row by at least 200ms or more. Figure 1 The 4T1C pixel circuit design shown in Figure 1 In the circuit shown, the stable maintenance of the gate potential of the switch tube M3 is very important for imaging. In addition, the switch tube M2 adopts OTFT, which can reduce leakage current and improve signal retention rate.

[0043] However, the oxide characteristics in the LTPO process structure are not very stable. When debugging and improving the process, the threshold voltage of the switch tube is prone to shift, which will cause the leakage current at node 1 in the circuit to be unable to be maintained, thus losing its signal holding function. Therefore, how to improve and optimize the characteristics of the oxide in the pixel circuit is particularly important.

[0044] Based on this, the present application provides a pixel circuit that can maintain the leakage current at node 1, so that the pixel circuit can output a more uniform current signal, thereby improving the signal retention capability of a large-area ultrasonic imaging device.

[0045] Figure 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present application. Figure 2As shown, the pixel circuit includes: a receiving transducer 10, a control circuit 20, a charge storage circuit 30 and a reading circuit 40, the output end of the receiving transducer 10 is connected to the input end of the control circuit 20, the output end of the control circuit 20 is connected to the input end of the charge storage circuit 30 and the reading circuit 40, wherein the connection point of the output end of the control circuit 20, the charge storage circuit 30 and the input end of the reading circuit 40 is the first node N1.

[0046] The receiving transducer 10 is configured to convert the detected ultrasonic wave signal into an electrical signal.

[0047] The control circuit 20 is configured to provide a detection voltage corresponding to the electrical signal to the first node N1, wherein the control circuit 20 includes a first switch tube M1, the first switch tube is an OTFT, the first switch tube M1 includes a first control end and a second control end that are independent of each other, the first control end is used to control the conduction or cutoff of the first switch tube M1, and the second control end is used to adjust the threshold voltage of the first switch tube M1.

[0048] The charge storage circuit 30 is used to store electric energy to lock the first node N1 to a high potential.

[0049] The read circuit 40 is configured to convert an electric signal related to the potential of the first node N1 into a current signal and output it to the detection output terminal Read.

[0050] In the embodiment of the present application, the first switch tube M1 is an OTFT, and the switch tubes in the pixel circuit except the first switch tube M1 are low temperature polycrystalline silicon thin film transistors (LTPS TFT).

[0051] Among them, the first switch tube M1 includes two control terminals, and the first switch tube M1 can also be called a TFT device with a dual-gate structure. The two control terminals of the first switch tube M1 are respectively a first control terminal and a second control terminal, and the first control terminal is used to control the conduction or shutdown of the first switch tube M1, and the first control terminal can be called a top gate (TG), and the second control terminal is used to adjust the threshold voltage of the first switch tube M1, and the second control terminal can be called a bottom gate (BG). The top gate and the bottom gate are independent of each other, that is, the signals of the top gate and the bottom gate do not affect each other, that is, the signal of the bottom gate can be controlled separately, so that the threshold voltage of the first switch tube M1 can be effectively adjusted, which is conducive to improving the signal retention ability of the large-area ultrasonic imaging device.

[0052] In the embodiment of the present application, the receiving transducer 10 may be an ultrasonic sensor, which is configured to transmit an ultrasonic signal, receive a reflected ultrasonic signal, and convert the received ultrasonic signal into an electrical signal.

[0053] The ultrasonic sensor may be a transceiver integrated type or a separate sound source type. The type of ultrasonic sensor may be designed and determined according to the actual application environment and is not limited here.

[0054] Exemplarily, the ultrasonic sensor includes at least one of a piezoelectric film (Poly Vinyli Dene Fluoride) PVDF sensor, a capacitive micromachined ultrasonic transducer (CMUT) sensor, and a piezoelectric micromachined ultrasonic transducer (PMUT) sensor. In practical applications, the material of the ultrasonic sensor can be designed and determined according to the actual application environment, and is not limited here.

[0055] In an embodiment of the present application, the receiving transducer 10 converts the detected signal into an electrical signal, and the control circuit 20 can provide a detection voltage corresponding to the electrical signal to the first node. Since the first switch tube of the control circuit 20 includes two independent control terminals, that is, the first control terminal and the second control terminal are independent of each other, and the second control terminal can be used to adjust the threshold voltage of the first switch tube, the threshold voltage of the first switch tube can be effectively adjusted. In this way, the leakage current at the first node can be maintained, and the reading circuit 40 outputs the current signal converted from the electrical signal related to the potential of the first node to the detection output terminal. As a result, the uniformity of the current signal output by the reading circuit 40 to the detection output terminal can be improved, thereby improving the signal retention capability of the large-area ultrasonic imaging device.

[0056] Figure 3 is a circuit diagram of a pixel circuit provided in an embodiment of the present application. Figure 3 The control circuit also includes a second switch tube M2.

[0057] The first control end of the first switch tube M1 is electrically connected to the first signal end Gate1, the second control end of the first switch tube M1 is electrically connected to the second signal end Gate2, the first end of the first switch tube M1 is electrically connected to the receiving transducer 10, and the second end of the first switch tube M1 is electrically connected to the first node N1.

[0058] The control end of the second switch tube M2 is electrically connected to the third signal end Gate3, the first end of the second switch tube M2 is electrically connected to the fourth signal end V1, and the second end of the second switch tube M2 is electrically connected to the second node N2, wherein the second node N2 is the connection point between the receiving transducer 10 and the first switch tube M1.

[0059] In the embodiment of the present application, the first switch tube M1 includes four terminals, namely, a first control terminal, a second control terminal, a first terminal, and a second terminal. Among them, the first control terminal of the first switch tube M1 is electrically connected to the first signal terminal Gate1, and when the first signal terminal Gate1 inputs a high-level signal to the first control terminal of the first switch tube M1, the first switch tube M1 is turned on; the second control terminal of the first switch tube M1 is electrically connected to the second signal terminal Gate2, and when the second signal terminal Gate2 inputs a low-level signal to the second control terminal of the first switch tube M1, the threshold voltage of the first switch tube M1 changes; the first terminal of the first switch tube M1 is electrically connected to the receiving transducer 10, and the second terminal of the first switch tube M1 is electrically connected to the first node N1, so that when the first switch tube M1 is turned on, the first switch tube M1 can transmit the detection voltage corresponding to the electrical signal to the first node N1.

[0060] The second switch tube M2 includes three terminals, namely, a control terminal, a first terminal, and a second terminal. The control terminal of the second switch tube M2 is electrically connected to the third signal terminal Gate3. When the third signal terminal Gate3 inputs a high-level signal to the first control terminal of the second switch tube M2, the second switch tube M2 is turned on. The first terminal of the second switch tube M2 is electrically connected to the fourth signal terminal V1, and the second terminal of the second switch tube M2 is electrically connected to the second node N2. Therefore, when the second switch tube M2 is turned on, the second switch tube M2 can transmit the signal provided by the fourth signal terminal V1 to the second node N2.

[0061] Continue to refer Figure 3 The charge storage circuit 30 includes a storage capacitor C. A first electrode of the storage capacitor C is electrically connected to the first node N1, and a second electrode of the storage capacitor C is connected to a reference ground.

[0062] Continue to refer Figure 3 The reading circuit 40 includes a third switch tube M3 and a fourth switch tube M4. The control end of the third switch tube M3 is electrically connected to the first node N1, the first end of the third switch tube M3 is electrically connected to the fifth signal end V2, and the second end of the third switch tube M3 is electrically connected to the first end of the fourth switch tube M4; the control end of the fourth switch tube M4 is electrically connected to the sixth signal end Gate4, the first end of the fourth switch tube M4 is electrically connected to the second end of the third switch tube M3, and the second end of the fourth switch tube M4 is electrically connected to the detection output end Read.

[0063] In the embodiment of the present application, the third switch tube M3 includes three terminals, namely, a control terminal, a first terminal, and a second terminal. The control terminal of the third switch tube M3 is electrically connected to the first node N1, and when the voltage value of the first node N1 is a high voltage value, the third switch tube M3 is turned on; the first terminal of the third switch tube M3 is electrically connected to the fifth signal terminal V2, and the second terminal of the third switch tube M3 is electrically connected to the first terminal of the fourth switch tube M4, so that when the third switch tube M3 is turned on, the third switch tube M3 can transmit the signal provided by the fifth signal terminal V2 to the first terminal of the fourth switch tube.

[0064] The fourth switch tube M4 includes three terminals, namely, a control terminal, a first terminal and a second terminal. The control terminal of the fourth switch tube M4 is electrically connected to the sixth signal terminal Gate4, and when the sixth signal terminal Gate4 outputs a high level signal, the fourth switch tube M4 is turned on; the first terminal of the fourth switch tube M4 is electrically connected to the second terminal of the third switch tube M3, and the second terminal of the fourth switch tube M4 is electrically connected to the detection output terminal Read, so that when the fourth switch tube M4 is turned on, the fourth gate tube M4 can transmit the signal provided by the fifth signal terminal V2 of the third switch tube to the detection output terminal Read.

[0065] Among them, when the low level signal is loaded on the control end of the N-type switch tube, the N-type switch tube is turned off, and when the high level signal is loaded on the control end of the N-type switch tube, the N-type switch tube is turned on. The absolute values ​​of the specific level values ​​of the high level signal and the low level signal can be equal or different. Generally, the absolute values ​​of the specific level values ​​of the two level signals are equal. For example, the specific level value of the high level signal can be set to 4V, and the specific level value of the low level signal can be set to -4V.

[0066] It should be understood that the specific level values ​​of the high / low level signals of the fourth signal terminal V1 and the fifth signal terminal V2 are not necessarily equal to the specific level values ​​of the high / low level signals of other signal terminals (such as Gate1, Gate2, Gate3, Gate4) (of course, for the sake of driving simplicity, the two can usually be equal).

[0067] It should also be understood that the first end and the second end of each switch tube in the embodiment of the present application are equivalent, that is, the first end and the second end of each switch tube may be structurally indistinguishable, and the general principle is that the source voltage of the switch tube is less than the drain voltage. Taking the second switch tube M2 as an example, when the fourth signal terminal V1 inputs a high-level signal to the first end of the second switch tube M2, the first end of the second switch tube M2 is the drain, and the second end of the second switch tube M2 is the source; when the fourth signal terminal V1 inputs a low-level signal to the first end of the second switch tube M2, the first end of the second switch tube M2 is the source, and the second end of the second switch tube M2 is the drain.

[0068] like Figure 4 As shown, the embodiment of the present application also provides a driving method 400 of a pixel circuit, and the driving method 400 is applied to Figure 3 For the pixel circuit shown, the driving method 400 may include steps 410-440.

[0069] The driving cycle of the pixel circuit includes a reset phase, a sampling phase, a holding phase and a reading phase, and the driving method includes:

[0070] 410 , in a reset phase, controlling the control circuit to write a low level signal provided by the fourth signal terminal into the first node.

[0071] 420 , in the sampling phase, the control circuit is controlled to write the high level signal provided by the fourth signal terminal into the charge storage circuit.

[0072] 430, in the holding phase, the control circuit is controlled to be in an off state so that the potential of the first node maintains the high potential of the sampling phase, and the low-level signal provided by the second signal terminal is controlled to be input to the second control terminal of the first switch tube of the control circuit to adjust the threshold voltage of the first switch tube.

[0073] 440, in the reading phase, controlling the reading circuit to be in a conducting state so that the electrical signal related to the potential of the first node is converted into a current signal and output to the detection output terminal.

[0074] In order to facilitate the understanding of the following text, Figure 5 The adjustment of the shift in the threshold voltage of a dual-gate TFT device will be briefly described.

[0075] refer to Figure 5 The horizontal axis represents the voltage between the gate and source of the switching tube, and the vertical axis represents the current between the drain and source of the switching tube. It can be seen that when a negative constant voltage is applied to the bottom gate, such as the negative voltages of -4V, -8V, -12V, and -15V shown in the figure, the threshold voltage of the dual-gate structure TFT device will move positively; when a positive constant voltage is applied to the bottom gate, such as the positive voltages of 4V and 8V shown in the figure, its threshold voltage will move negatively.

[0076] like Figure 6 FIG. 1 is a schematic diagram of the control signal timing of the pixel circuit provided by the embodiment of the present application. Figure 6 In the embodiment, the driving cycle of the pixel circuit may include a reset phase T1, a sampling phase T2, a holding phase T3 and a reading phase T4.

[0077] In the reset phase T1 , the first signal terminal Gate1 , the third signal terminal Gate3 , and the fifth signal terminal V2 provide high level signals, the sixth signal terminal Gate4 and the fourth signal terminal V1 both provide low level signals, and the second signal terminal Gate2 provides 0V. Figure 7 Schematic diagram of the state of the pixel circuit in the reset phase T1.

[0078] In the reset phase T1, since Gate1 provides a high-level signal, the switch tube M1 is in the on state. Since Gate3 provides a high-level signal, the switch tube M2 is in the on state. Since V1 provides a low-level signal, the low-level signal provided by V1 is written into the first node N1 through the switch tubes M2 and M1, and the first node N1 is reset to a low potential. Since the first node N1 is reset to a low potential, the switch tube M3 is turned off. Since Gate4 provides a low-level signal, the switch tube M4 is turned off.

[0079] Furthermore, since Gate2 provides 0V, the threshold voltage of the switch tube M1 is not adjusted in the reset phase T1.

[0080] In the sampling phase T2 , the first signal terminal Gate1 , the third signal terminal Gate3 , the fourth signal terminal V1 , and the fifth signal terminal V2 all provide high level signals, the sixth signal terminal Gate4 provides a low level signal, and the second signal terminal Gate2 provides 0V. Figure 8 Schematic diagram of the state of the pixel circuit in the sampling phase T2.

[0081] In the sampling stage T2, since Gate1 and Gate3 provide high-level signals, the switch tubes M1 and M2 continue to be in the on state. Since V1 provides a high-level signal, the high-level signal provided by V1 is written into the first node N1 through the switch tubes M2 and M1, and the first node N1 is at a high potential, thereby charging the storage capacitor C. The first node N1 is transformed into a high potential, and the switch tube M3 is turned on. Since Gate4 provides a low-level signal, the switch tube M4 is turned off.

[0082] Furthermore, since Gate2 provides 0V, the threshold voltage of the switch tube M1 is not adjusted in the sampling phase T2.

[0083] In the sampling phase, when the receiving transducer detects the ultrasonic echo of the object, it starts integrating and sampling, and the potential of the first node N1 is affected by the echo.

[0084] In the holding stage T3 , the fifth signal terminal V2 provides a high level signal, and the first signal terminal Gate1 , the second signal terminal Gate2 , the third signal terminal Gate3 , the sixth signal terminal Gate4 , and the fourth signal terminal V1 all provide low level signals. Fig. 9 FIG. 1 is a schematic diagram of the state of the pixel circuit in the holding phase T3.

[0085] In the holding stage T3, since Gate1 and Gate3 provide low-level signals, the switch tubes M1 and M2 are turned off, so that the potential of the first node N1 can be locked to a high potential. Because the switch tube M1 of the present application adopts an OTFT, in order to prevent the switch tube M1 from being negatively biased and causing leakage, Gate2 provides a low-level signal at this time, and the threshold voltage of the switch tube M1 is positively shifted, which can ensure that the switch tube M1 reduces leakage current, so that the high potential of the first node N1 can be maintained as much as possible.

[0086] When the first node N1 maintains a high potential, the switch tube M3 is turned on. Since Gate4 provides a low level signal, the switch tube M4 is still in the off state.

[0087] In the reading phase T4 , the sixth signal terminal Gate4 and the fifth signal terminal V2 provide high level signals, and the first signal terminal Gate1 , the second signal terminal Gate2 , the third signal terminal Gate3 , and the fourth signal terminal V1 provide low level signals. Fig.10 FIG. 4 is a schematic diagram of the state of the pixel circuit in the reading phase T4.

[0088] In the reading stage T4, Gate1 and Gate3 both provide low-level signals, and the switches M1 and M2 are turned off. The first node N1 continues to maintain a high potential, and the switch M3 continues to remain in the on state. Since Gate4 provides a high-level signal, the switch M4 is turned on, so that the electrical signal related to the potential of the first node N1, that is, V2, is converted into a current signal and output to the detection output terminal Read.

[0089] It should be understood that in the reading stage T4, the detection output terminal Read outputs a current signal converted by V2, and this current signal can indirectly reflect the change of the potential at the first node N1. Specifically, if the switch tube M1 does not include the second control terminal, due to the negative bias of the threshold voltage of the switch tube M1, it is possible that the switch tube M1 should be turned off but is actually in a conductive state. In this way, the potential of the first node N1 jumps, resulting in an incorrect state of the switch tube M3, so that the current signal converted based on the signal provided by V2 is output to the detection output terminal unevenly. In the present application, since the switch tube M1 includes the second control terminal, the second control terminal can adjust the threshold voltage of the first switch tube M1, so that the threshold voltage of the first switch tube M1 can be corrected. In this way, the leakage current at the first node N1 can be maintained, and the reading circuit 40 outputs the current signal converted from the electrical signal related to the potential of the first node to the detection output terminal Read, thereby, the current signal output by the reading circuit 40 to the detection output terminal Read is relatively uniform, thereby improving the signal retention capability of the large-area ultrasonic imaging device.

[0090] In one embodiment, during the reset phase and the sampling phase, the second signal terminal is controlled to output a preset voltage to the second control terminal of the first switch tube, so that the first switch tube maintains a threshold voltage of the current phase.

[0091] The preset voltage in the embodiment of the present application may be 0V. Figure 6 It can be seen that in the reset stage T1, Gate2 provides 0V, that is, in the reset stage T1, the second signal terminal Gate2 inputs a 0V voltage signal to the second control terminal of the first switch tube M1. Therefore, in this stage, the threshold voltage of the switch tube M1 is not adjusted. This is because the main purpose of this stage is to reset the first node N1. If the threshold voltage of the switch tube M1 is adjusted in the reset stage T1, it may affect the potential of the first node N1 in the subsequent holding stage T3, which is not conducive to the detection output terminal Read outputting a uniform current signal.

[0092] Similarly, in the sampling stage T2, Gate2 also provides 0V. The specific reasons are similar to those mentioned above and will not be repeated here.

[0093] It should be understood that in actual scenarios, the second signal terminal Gate2 may not be able to guarantee the output of an accurate preset voltage, and the voltage value output by the second signal terminal Gate2 may deviate from the preset voltage. Therefore, the present application allows the existence of errors. In other words, taking the error of ±0.1V as an example, in the reset phase T1 and the sampling phase T2, when the preset voltage is 0V, the second signal terminal Gate2 can be allowed to output any voltage of -0.1V to +0.1V to the second control terminal of the first switch tube M1. In this way, the impact of the error on the solution of the present application can be ignored.

[0094] In one embodiment, the signal output by the second signal terminal is adjusted according to the current signal output by the detection output terminal.

[0095] In the embodiment of the present application, the size of the specific signal of the second signal terminal Gate2 is related to the unevenness of the current signal output by the detection output terminal Read. If the current signal output by the detection output terminal Read is relatively uniform, the second signal terminal Gate2 can output a signal with a smaller voltage value; if the current signal output by the detection output terminal Read is not uniform, the second signal terminal Gate2 can output a signal with a larger voltage value.

[0096] In actual scenarios, the second signal terminal Gate2 can start to output a low-level signal with a smaller voltage absolute value, such as -2V. When the second signal terminal Gate2 outputs a low-level signal of -2V, if the current signal output by the detection output terminal Read is basically uniform, that is, there is no obvious spike signal, there is no need to adjust the voltage value output by the second signal terminal Gate2; if the current signal output by the detection output terminal Read is not uniform, that is, there is an obvious spike signal, then the voltage value output by the second signal terminal Gate2 can continue to be adjusted, such as adjusting the voltage value to -4V, until the current signal output by the detection output terminal Read becomes uniform.

[0097] Those skilled in the art can understand that in the pixel circuit shown in any of the above embodiments, all switch tubes can also use P-type transistors. When P-type transistors are used, the states of Gate1, Gate2, Gate3, Gate4, V1, and V2 are opposite to those when N-type transistors are used.

[0098] It should be noted that the storage capacitor C may be a parasitic capacitor of a transistor or an external capacitor, which is not limited in any way in the embodiments of the present disclosure.

[0099] The following will combine Fig.11 The structure of a dual-gate TFT device will be described.

[0100] refer to Fig.11 First, a BG metal layer can be made on the substrate (Glass) as the bottom gate, and a buffer layer (Buffer), an active layer (Oxide), and a gate insulating layer (Gate Insulate, GI) are deposited in sequence, wherein the active layer is patterned accordingly; next, a TG metal layer is made as the top gate, an interlayer dielectric layer (Inter Layer Dielectric, ILD) is deposited and patterned, and finally a drain metal layer and a source metal layer are deposited to form the drain and source of a dual-gate structure TFT device.

[0101] Fig.12 This is a schematic diagram of the structure of a pixel circuit provided by the present application. The following is a brief description of the manufacturing process of the pixel circuit.

[0102] (1) First, a buffer layer (Buffer) and an active layer of amorphous silicon (a-Si) are deposited on the substrate (Glass), and polycrystalline silicon (poly-Si) is formed through processes such as dehydrogenation and crystallization. The polysilicon (poly-Si) is patterned and threshold channel doping is performed.

[0103] (2) Depositing a gate insulating layer 1 and a Gate layer, patterning the Gate layer, and performing P+doping and N+doping to form a source and a drain. The P+doping is intended to form a lateral PIN with the N+doping as an electrostatic discharge (ESD), which can prevent the occurrence of static electricity. A thin layer of low-doped intrinsic semiconductor layer is added between the P and N semiconductor materials to form a PIN structure.

[0104] (3) Deposit an interlayer dielectric layer 1 and a buffer layer (Buffer-O) to form an oxide active layer.

[0105] (4) depositing and patterning a gate insulating layer 2, depositing and patterning a Gate2, and forming an LTPS TFT and a PIN structure; and forming a top gate structure of an OTFT in the same layer of Gate2.

[0106] (5) Deposit an interlayer dielectric layer 2 and pattern it to produce a source-drain (SD) metal layer to form the source and drain of the OTFT.

[0107] (6) Deposit an insulating layer 1 and an organic planarization layer, and perform patterning.

[0108] (7) Deposit an indium tin oxide (ITO) metal layer and pattern it, and finally deposit an insulating layer 2.

[0109] In addition, the present application discloses an ultrasonic imaging device, which includes a substrate and a plurality of pixel units, each of which includes a pixel circuit according to any one of the above embodiments.

[0110] The embodiment of the present application further provides a computer program product, which includes: a computer program code, and when the computer program code is executed on a computer, the computer executes the method 400 in the above embodiment.

[0111] The embodiment of the present application further provides a computer-readable medium, wherein the computer-readable medium stores a program code. When the computer program code is executed on a computer, the computer executes the method 400 in the above embodiment.

[0112] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0113] The terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "multiple" means two or more. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0114] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0115] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts or steps therein may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no conflict in structure or method steps. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A pixel circuit, characterized in that: include: A receiving transducer, a control circuit, a charge storage circuit and a reading circuit, wherein the output end of the receiving transducer is connected to the input end of the control circuit, and the output end of the control circuit is connected to the input ends of the charge storage circuit and the reading circuit, wherein a connection point among the output end of the control circuit, the charge storage circuit and the input end of the reading circuit is a first node; The receiving transducer is configured to convert the detected ultrasonic signal into an electrical signal; The control circuit is configured to provide a detection voltage corresponding to the electrical signal to the first node, wherein the control circuit includes a first switch tube, the first switch tube is an oxide thin film transistor, the first switch tube includes a first control end and a second control end that are independent of each other, the first control end is used to control the first switch tube to be turned on or off, and the second control end is used to adjust the threshold voltage of the first switch tube; The charge storage circuit is used to store electric energy to lock the first node to a high potential; The read circuit is configured to convert an electric signal related to the potential of the first node into a current signal and output it to a detection output terminal.

2. The pixel circuit according to claim 1, characterized in that: The control circuit also includes a second switch tube; The first control end of the first switch tube is electrically connected to the first signal end, the second control end of the first switch tube is electrically connected to the second signal end, the first end of the first switch tube is electrically connected to the receiving transducer, and the second end of the first switch tube is electrically connected to the first node; The control end of the second switch tube is electrically connected to the third signal end, the first end of the second switch tube is electrically connected to the fourth signal end, and the second end of the second switch tube is electrically connected to the second node, which is the connection point between the receiving transducer and the first switch tube.

3. The pixel circuit according to claim 1 or 2, characterized in that: The charge storage circuit includes a storage capacitor; A first electrode of the storage capacitor is electrically connected to the first node, and a second electrode of the storage capacitor is connected to a reference ground.

4. The pixel circuit according to any one of claims 1 to 3, characterized in that: The reading circuit includes a third switch tube and a fourth switch tube; The control end of the third switch tube is electrically connected to the first node, the first end of the third switch tube is electrically connected to the fifth signal end, and the second end of the third switch tube is electrically connected to the first end of the fourth switch tube; The control end of the fourth switch tube is electrically connected to the sixth signal end, the first end of the fourth switch tube is electrically connected to the second end of the third switch tube, and the second end of the fourth switch tube is electrically connected to the detection output end.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that: The signal output by the second signal terminal is adjusted according to the current signal output by the detection output terminal.

6. The pixel circuit according to any one of claims 1 to 5, characterized in that: The switch tubes other than the first switch tube in the pixel circuit are low-temperature polysilicon thin-film transistors.

7. A method for driving a pixel circuit, characterized in that: A pixel circuit as claimed in any one of claims 1 to 6; The driving cycle of the pixel circuit includes a reset phase, a sampling phase, a holding phase and a reading phase, and the driving method includes: In the reset phase, controlling the control circuit to write the low level signal provided by the fourth signal terminal into the first node; In the sampling phase, controlling the control circuit to write the high level signal provided by the fourth signal terminal into the charge storage circuit; In the holding phase, the control circuit is controlled to be in an off state so that the potential of the first node maintains the high potential in the sampling phase, and the low-level signal provided by the second signal terminal is controlled to be input to the second control terminal of the first switch tube of the control circuit to adjust the threshold voltage of the first switch tube; In the reading phase, the reading circuit is controlled to be in an on state, so that the electrical signal related to the potential of the first node is converted into a current signal and output to the detection output terminal.

8. The driving method according to claim 7, characterized in that: The method further comprises: In the reset phase and the sampling phase, the second signal terminal is controlled to output a preset voltage to the second control terminal of the first switch tube, so that the first switch tube maintains a threshold voltage of the current phase.

9. An ultrasonic imaging device, characterized in that: include: A substrate and a plurality of pixel units, each of the pixel units comprising a pixel circuit as claimed in any one of claims 1 to 6.

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