Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a first wafer; forming a bonding layer on the front surface of the first wafer; trimming the first wafer on which the bonding layer is formed to form a first step; a bonding layer covers the front surface of the first step; providing a second wafer, and bonding the trimmed first wafer to the surface of the second wafer through the bonding layer to obtain a bonding structure; thinning the first wafer for the first time from the back surface; forming a protective layer; removing the protective layer covering the surface, far away from the second wafer, of the first wafer thinned for the first time; carrying out at least two times of thinning on the first wafer after the first time of thinning; and performing wet etching on the first wafer after at least two times of thinning. The trimming treatment is performed after the bonding layer is formed, so that rapid decrease or height difference of the thickness of the wafer edge dielectric layer is reduced, meanwhile, wafer cracking in the thinning process is avoided, and the yield of the semiconductor structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensors are divided into front-illuminated image sensors and back-illuminated image sensors according to their structures. The back-illuminated image sensor has a complex process, which requires flipping the device wafer with the photodiode through a bonding process and combining it with the optical board carrier to ensure the mechanical strength of the device wafer in the subsequent thinning process.

[0003] In the bonding process, the device wafer will be pre-trimmed before pre-bonding, and then a dielectric layer will be deposited on the surface of the trimmed structure. The dielectric layer will then be further subjected to chemical mechanical polishing. However, as the CMP (Chemical Mechanical Planarization) polishing rate increases sharply at the trimmed position, the thickness of the wafer edge oxide layer of the device wafer will drop sharply. There will be a large step height or dielectric layer thickness difference at the edge of the device wafer, which will affect the bonding strength of the wafer edge. Cracks will also occur during the thinning process, affecting the product yield. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor structure and a method for preparing the same, which solves the problems of affecting the bonding strength of the wafer edge and causing cracks during the thinning process due to large height differences or dielectric layer thickness differences at the wafer edge caused by edge trimming, thereby improving the yield of the semiconductor structure.

[0005] To achieve the purpose of this application, this application provides the following technical solutions:

[0006] In a first aspect, the present application provides a method for preparing a semiconductor structure, comprising:

[0007] providing a first wafer;

[0008] forming a bonding layer on the front side of the first wafer;

[0009] Performing edge trimming on the first wafer formed with the bonding layer to form a first step; the bonding layer covers the front side of the first step;

[0010] Providing a second wafer, and bonding the first wafer after edge trimming to the surface of the second wafer via the bonding layer to obtain a bonding structure;

[0011] Performing a first thinning on the first wafer from the back side;

[0012] forming a protective layer, wherein the protective layer at least covers a surface of the first wafer away from the second wafer after the first thinning, a side wall of the first wafer after the first thinning, and a side wall of the bonding layer;

[0013] removing the protective layer covering the surface of the first wafer away from the second wafer after the first thinning;

[0014] Thinning the first wafer after the first thinning at least twice more;

[0015] Performing a first wet etching on the first wafer after the at least two thinning steps.

[0016] The method for preparing the semiconductor structure of the present application reduces the sharp drop in the thickness or height difference of the dielectric layer at the edge of the crystal by performing trimming after forming the bonding layer, thereby improving the bonding performance; at the same time, it avoids cracking during the thinning process, thereby improving the yield of the semiconductor structure. Further, after obtaining the bonding structure, in the process of performing multiple thinning processes on the obtained structure, by forming a protective layer between the steps of the multiple thinning processes, the bonding interface can be protected from being corroded by the etching solution in the subsequent wet etching process, thereby improving the quality of the bonding structure and further improving the reliability of the semiconductor structure.

[0017] In one embodiment, the thickness of the first wafer after the first thinning is smaller than the height of the first step.

[0018] In one embodiment, the thickness of the protective layer is 0.5KÅ~1.5KÅ.

[0019] In one of the embodiments, after performing a first wet etching on the first wafer after the at least two thinning steps, the preparation method further comprises: trimming the bonding structure to obtain a second step.

[0020] In one embodiment, the width of the second step is smaller than the width of the first step.

[0021] In one embodiment, after trimming the bonding structure to obtain the second step, the method further includes:

[0022] Thinning the first wafer in the second step again;

[0023] The bonding structure is subjected to a second wet etching.

[0024] In one embodiment, forming a bonding layer on the front side of the first wafer includes:

[0025] forming a bonding material layer on the front side of the first wafer;

[0026] The bonding material layer is subjected to chemical mechanical polishing to obtain the bonding layer.

[0027] In one embodiment, forming a bonding material layer on the front side of the first wafer includes:

[0028] forming a first bonding material layer on the front surface of the first wafer;

[0029] A second bonding material layer is formed on the front side of the first bonding material layer; the second bonding material layer and the first bonding material layer together constitute the bonding material layer.

[0030] In one embodiment, the thickness of the first bonding material layer is 5KÅ~10KÅ; the thickness of the second bonding material layer is 40KÅ~50KÅ.

[0031] In a second aspect, the present application further provides a semiconductor structure, which is obtained by using the semiconductor structure preparation method described in any of the above embodiments.

[0032] The semiconductor structure of the present application reduces the sharp drop in the thickness or height difference of the dielectric layer at the crystal edge by performing trimming after forming the bonding layer, thereby improving the bonding performance; at the same time, it avoids cracking during the thinning process, thereby improving the yield of the semiconductor structure. Further, after obtaining the bonding structure, in the process of performing multiple thinning processes on the obtained structure, by forming a protective layer between the steps of the multiple thinning processes, the bonding interface can be protected from being corroded by the etching solution in the subsequent wet etching process, thereby improving the quality of the bonding structure and further improving the reliability of the semiconductor structure.

[0033] In summary, the present application provides a semiconductor structure and a method for preparing the same. By performing trimming after forming a bonding layer, the unexpected effect is: reducing the sharp drop in the thickness of the dielectric layer at the edge of the crystal or the height difference, thereby improving the bonding performance; while avoiding cracking during the thinning process, thereby improving the yield of the semiconductor structure. Further, after obtaining the bonding structure, in the process of performing multiple thinning treatments on the obtained structure, by forming a protective layer between the steps of the multiple thinning treatments, the bonding interface can be protected from being corroded by the etching solution in the subsequent wet etching process, thereby improving the quality of the bonding structure and further improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] FIG1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0036] FIG2 is a flow chart of step S12 in a method for preparing a semiconductor structure provided in an embodiment;

[0037] FIG3 is a flow chart of step S121 in a method for preparing a semiconductor structure provided in an embodiment;

[0038] FIG4 is a flow chart of steps S21 to S22 in a method for preparing a semiconductor structure provided in an embodiment;

[0039] FIG5 is a schematic cross-sectional view of a structure obtained in step S11 of a method for preparing a semiconductor structure provided in an embodiment;

[0040] FIG6 is a schematic cross-sectional view of a structure obtained in step S1211 of a method for preparing a semiconductor structure provided in an embodiment;

[0041] FIG. 7 is a schematic cross-sectional view of a structure obtained in step S1212 of a method for preparing a semiconductor structure provided in an embodiment;

[0042] FIG8 is a schematic cross-sectional view of a structure obtained in step S122 of a method for preparing a semiconductor structure provided in an embodiment;

[0043] FIG9 is a schematic cross-sectional view of a structure obtained in step S13 of a method for preparing a semiconductor structure provided in an embodiment;

[0044] FIG10 is a schematic cross-sectional view of a structure obtained in step S14 of a method for preparing a semiconductor structure provided in an embodiment;

[0045] FIG11 is a schematic cross-sectional view of a structure obtained in step S15 of a method for preparing a semiconductor structure provided in an embodiment;

[0046] 12 is a schematic cross-sectional view of a structure obtained in step S16 of a method for preparing a semiconductor structure provided in an embodiment;

[0047] 13 is a schematic cross-sectional view of a structure obtained in step S17 of a method for preparing a semiconductor structure provided in an embodiment;

[0048] 14 is a schematic cross-sectional view of a structure obtained in step S18 in a method for preparing a semiconductor structure provided in an embodiment;

[0049] 15 is a schematic cross-sectional view of a structure obtained in step S19 of a method for preparing a semiconductor structure provided in an embodiment;

[0050] FIG. 16 is a schematic diagram of a cross-sectional structure of a structure obtained in step S21 in a method for preparing a semiconductor structure provided in an embodiment.

[0051] Description of Reference Numerals

[0052] 10. First wafer; 20. Bonding layer; 201. Bonding material layer; 2011. First bonding material layer; 2012. Second bonding material layer; 30. First step; 40. Second wafer; 50. Protective layer; 60. Second step. DETAILED DESCRIPTION

[0053] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0055] It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to, or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to, or "directly coupled to" other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0056] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0057] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0059] Please refer to FIG. 1 . An embodiment of the present application provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure includes the following steps: S11 to S19 .

[0060] S11: providing a first wafer.

[0061] S12: forming a bonding layer on the front side of the first wafer.

[0062] S13: trimming the first wafer with the bonding layer formed thereon to form a first step; the bonding layer covers the front side of the first step.

[0063] S14: providing a second wafer, and bonding the trimmed first wafer to the surface of the second wafer via a bonding layer to obtain a bonding structure.

[0064] S15: performing a thinning process on the first wafer from the back side.

[0065] S16: forming a protective layer, wherein the protective layer at least covers the surface of the first wafer away from the second wafer after the first thinning, the sidewall of the first wafer after the first thinning, and the sidewall of the bonding layer.

[0066] S17: removing the protective layer covering the surface of the first wafer away from the second wafer after the first thinning.

[0067] S18: Thinning the first wafer after the first thinning at least twice again.

[0068] S19: performing a first wet etching on the first wafer after at least two thinning steps.

[0069] In the embodiment of the present application, by performing trimming after forming the bonding layer, the sharp drop in the thickness or height difference of the dielectric layer at the crystal edge is reduced, thereby improving the bonding performance; at the same time, cracking is avoided during the thinning process, thereby improving the yield of the semiconductor structure. Further, after obtaining the bonding structure, in the process of performing multiple thinning processes on the obtained structure, by forming a protective layer between the multiple thinning steps, the bonding interface can be protected from being corroded by the etching solution in the subsequent wet etching process, thereby improving the quality of the bonding structure and further improving the reliability of the semiconductor structure.

[0070] Exemplarily, the thickness of the first wafer after the first thinning is less than the height of the first step.

[0071] Exemplarily, the thickness of the protective layer is 0.5KÅ~1.5KÅ.

[0072] In some embodiments, referring to FIG. 2 , in step S12 , forming a bonding layer on the front side of the first wafer may include the following steps: S121 - S122 .

[0073] S121: forming a bonding material layer on the front side of the first wafer.

[0074] S122: performing chemical mechanical polishing on the bonding material layer to obtain a bonding layer.

[0075] In some embodiments, referring to FIG. 3 , in step S121 , forming a bonding material layer on the front side of the first wafer may include the following steps: S1211 - S1212 .

[0076] S1211: forming a first bonding material layer on the front side of the first wafer.

[0077] S1212: forming a second bonding material layer on the front side of the first bonding material layer; the second bonding material layer and the first bonding material layer together constitute a bonding material layer.

[0078] Exemplarily, the thickness of the first bonding material layer is 5KÅ~10KÅ; the thickness of the second bonding material layer is 40KÅ~50KÅ.

[0079] In some embodiments, after step S19, the method for preparing a semiconductor structure further includes: step S20: trimming the bonding structure to obtain a second step.

[0080] Exemplarily, the width of the second step is smaller than the width of the first step.

[0081] In some embodiments, referring to FIG. 4 , after trimming the bonding structure to obtain the second step, the method further includes:

[0082] S21: thinning the first wafer in the second step again.

[0083] S22: performing a second wet etching on the bonding structure.

[0084] It should be understood that, although the various steps in the flowcharts of Figures 1 to 4 are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a portion of the steps in Figures 1 to 4 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages does not have to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0085] In order to more clearly illustrate the method for preparing the semiconductor device structure in some of the above embodiments, please understand the following embodiments in conjunction with FIG. 5 to FIG. 16 .

[0086] In step S11 , please refer to step S11 in FIG. 1 and FIG. 5 , a first wafer 10 is provided.

[0087] As an example, the first wafer 10 may include but is not limited to a single crystal silicon wafer; the diameter of the first wafer 10 may include but is not limited to 25 mm, 51 mm, 76 mm, 100 mm, 125 mm, 150 mm, 200 mm, 300 mm, 450 mm or above 675 mm.

[0088] As an example, the first wafer 10 may include at least one of a silicon wafer, a gallium nitride (GaN) wafer, a silicon carbide (SiC) wafer, a sapphire wafer, a silicon on insulator (SOI) wafer, a silicon on diamond (SOD) wafer, and a strained layer silicon wafer deposited on a silicon germanium wafer.

[0089] As an example, devices such as photodiodes may be formed on the front side of the first wafer 10 .

[0090] In step S12 , referring to step S12 in FIG. 1 , FIG. 2 , FIG. 3 , and FIG. 6 to FIG. 8 , a bonding layer 20 is formed on the front surface of the first wafer 10 .

[0091] In some embodiments, please continue to refer to FIG. 2 and FIG. 6 to FIG. 8 , step S12 may include step S121 to step S122 .

[0092] In step S121 , referring to FIGS. 6 and 7 , a bonding material layer 201 is formed on the front surface of the first wafer 10 .

[0093] In some specific embodiments, referring to FIG. 3 , step S121 may include steps S1211 to S1212 .

[0094] In step S1211 , referring to FIG. 7 , a first bonding material layer 201 is formed on the front surface of the first wafer 10 .

[0095] As an example, a high density plasma chemical vapor deposition process (HDP CVD) may be used but is not limited to form a first bonding material layer 2011 on the front side of the first wafer 10; the high density plasma chemical vapor deposition process can achieve excellent filling of high aspect ratio (the ratio of the depth to the width of the gap) gaps at a relatively low temperature, and the deposited first bonding material layer 2011 has the advantages of high density and low impurity defects, and has excellent adhesion to the first wafer 10; of course, in other embodiments, chemical vapor deposition (CVD) or atomic layer deposition (ALD) or any combination thereof may be used to form the first bonding material layer 2011 on the front side of the first wafer 10.

[0096] As an example, the first bonding material layer 2011 may include but is not limited to an insulating material layer. For example, the first bonding material layer 2011 may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0097] As an example, the thickness of the first bonding material layer 2011 may include but is not limited to 5KÅ~10KÅ; specifically, the thickness of the first bonding material layer 2011 may be 5KÅ, 6KÅ, 7KÅ, 8KÅ, 8.8KÅ or 10KÅ, etc.

[0098] In step S1212 , please continue to refer to FIG. 7 , a second bonding material layer 2012 is formed on the front surface of the first bonding material layer 2011 ; the second bonding material layer 2012 and the first bonding material layer 2011 together constitute the bonding material layer 201 .

[0099] As an example, the second bonding material layer 2012 can be deposited using, but not limited to, tetraethoxysilane (TEOS) as a silicon source in chemical vapor deposition; by using tetraethoxysilane as a silicon source in chemical vapor deposition, a second bonding material layer 2012 having the advantages of good coverage, good quality, high purity, good reflow characteristics and high thermal stability can be obtained; the second bonding material layer 2012 can include, but not limited to, a silicon oxide layer.

[0100] As an example, the thickness of the second bonding material layer 2012 may include but is not limited to 40KÅ~50KÅ; specifically, the thickness of the second bonding material layer 2012 may be 40KÅ, 41KÅ, 42KÅ, 43KÅ, 44KÅ, 45KÅ, 46KÅ, 47KÅ, 48KÅ, 49KÅ or 50KÅ, etc.

[0101] In step S122 , referring to FIG. 8 , chemical mechanical polishing is performed on the bonding material layer 201 to obtain the bonding layer 20 .

[0102] As an example, in step S122 , chemical mechanical polishing is performed on the bonding material layer 201 to obtain the bonding layer 20 , which may include the following steps S1221 - S1223 .

[0103] S1221 : performing chemical mechanical polishing on the second bonding material layer 2012 .

[0104] S1222 : forming a third bonding material layer (not shown) on the front side of the second bonding material layer 2012 after chemical mechanical polishing; at this time, the first bonding material layer 2011 , the second bonding material layer 2012 and the third bonding material layer together constitute the bonding material layer 201 .

[0105] S1223: Perform chemical mechanical polishing on the third bonding material layer.

[0106] As an example, in step S1221, the grinding thickness of the second bonding material layer 2012 subjected to chemical mechanical grinding may include but is not limited to 30KÅ~40KÅ. For example, the grinding thickness of the second bonding material layer 2012 subjected to chemical mechanical grinding may be 30KÅ, 31KÅ, 32KÅ, 33KÅ, 34KÅ, 35KÅ, 36KÅ, 37KÅ, 38KÅ, 39KÅ or 40KÅ, etc.

[0107] As an example, in step S1222, a high density plasma chemical vapor deposition process (HDP CVD) can be used but is not limited to form a third bonding material layer on the front side of the second bonding material layer 2012 after chemical mechanical polishing. Of course, in other embodiments, chemical vapor deposition (CVD) or atomic layer deposition (ALD) or any combination thereof can be used to form a third bonding material layer on the front side of the second bonding material layer 2012 after chemical mechanical polishing.

[0108] As an example, the thickness of the third bonding material layer may include but is not limited to 500Å~1500Å; specifically, the thickness of the third bonding material layer may be 500Å, 800Å, 1000Å, 1200Å or 1500Å, etc.

[0109] As an example, in step S1223, the grinding thickness of the third bonding material layer subjected to chemical mechanical grinding may include but is not limited to 200Å~800Å. For example, the grinding thickness of the third bonding material layer subjected to chemical mechanical grinding may be 200Å, 300Å, 400Å, 500Å, 600Å, 700Å or 800Å, etc.

[0110] It should be noted that the first bonding material layer 2011 , the second bonding material layer 2012 and the third bonding material layer (not shown) together constitute the bonding material layer 201 , and the bonding layer 20 is obtained by grinding the bonding material layer 201 .

[0111] In step S13 , referring to step S13 in FIG. 1 and FIG. 9 , the first wafer 10 formed with the bonding layer 20 is trimmed to form a first step 30 ; the bonding layer 20 covers the front surface of the first step 30 .

[0112] As an example, the first wafer 10 formed with the bonding layer 20 may be trimmed by, but not limited to, polysilicon fuse trimming, metal fuse trimming, Zener trimming or laser trimming.

[0113] As an example, the height of the first step 30 can be 130μm~160μm, for example, the height of the first step 30 can be 130μm, 140μm, 145μm, 150μm or 160μm; the distance between the edge of the first step 30 and the edge of the first wafer 10 can be 1mm~2mm, for example, the distance between the edge of the first step 30 and the edge of the first wafer 10 can be 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm, 1.9mm or 2mm.

[0114] In step S14 , referring to FIG. 10 , a second wafer 40 is provided, and the trimmed first wafer 10 is bonded to the surface of the second wafer 40 via the bonding layer 20 to obtain a bonding structure.

[0115] As an example, the first wafer 10 after edge trimming may be bonded to the surface of the second wafer 40 via the bonding layer 20 by using, but not limited to, a direct bonding process (Fusion bond) to obtain a bonding structure.

[0116] In step S15 , referring to step S15 in FIG. 1 and FIGS. 4 , 10 and 11 , the first wafer 10 is thinned for the first time from the back side.

[0117] As an example, the first wafer 10 may be thinned for the first time from the back side by using, but not limited to, a back grinding process. The back grinding process is a process of grinding the back side of the wafer thin. The purpose of the process is not only to reduce the thickness of the wafer, but also to connect the front-end and back-end processes to solve problems between the two processes. More specifically, the thickness of the first wafer after the first thinning is less than the height of the first step.

[0118] In a specific example, the back grinding process may include steps S151 and S152:

[0119] S151: Attach a protective tape to the front of the first wafer 10; during back grinding, the silicon compound will diffuse around, and the first wafer 10 may also be broken or warped due to external force during this process, and the larger the area of ​​the first wafer 10, the more susceptible it is to this phenomenon. Therefore, before back grinding, a thin UV (Ultra Violet) blue film needs to be attached to protect the first wafer 10;

[0120] S152: Grind the back side of the first wafer 10; the thickness of the first wafer 10 after the first thinning is less than the height of the first step 30; the grinding thickness of this step may include but is not limited to 620μm~669μm, for example, the grinding thickness may be 620μm, 650μm, 660μm or 669μm, etc.; after this step of grinding, the thickness of the first wafer 10 may be but is not limited to being ground from 750μm to 81μm.

[0121] In step S16, please refer to step S16 in Figure 1 and Figure 12, a protective layer 50 is formed, and the protective layer 50 at least covers the surface of the first wafer 10 away from the second wafer 40 after the first thinning, the side wall of the first wafer 10 after the first thinning, and the side wall of the bonding layer.

[0122] As an example, the protective layer 50 may be formed by deposition using, but not limited to, chemical vapor deposition using tetraethoxysilane (TEOS) as a silicon source.

[0123] As an example, the thickness of the protective layer 50 may include but is not limited to 0.5KÅ~1.5KÅ. Specifically, the thickness of the protective layer 50 may be 0.5KÅ, 1.0KÅ or 1.5KÅ. The protective layer 50 at least covers the surface of the first wafer 10 away from the second wafer 40 after the first thinning, the side wall of the first wafer 10 after the first thinning, and the side wall of the bonding layer 20. The protective layer 50 also covers the exposed front side of the second wafer 40; the protective layer 50 can protect the bonding cross section from being corroded by subsequent wet etching.

[0124] In step S17 , referring to step S17 in FIG. 1 and FIG. 13 , the protection layer 50 covering the surface of the first wafer 10 away from the second wafer 40 after the first thinning is removed.

[0125] As an example, the protection layer 50 covering the surface of the first wafer 10 away from the second wafer 40 after the first thinning may be removed by using, but not limited to, a chemical mechanical polishing process.

[0126] In step S18 , please refer to step S18 in FIG. 1 and FIG. 14 , the first wafer 10 after the first thinning is thinned at least twice more.

[0127] As an example, a grinding process such as, but not limited to, a turntable grinding process, a silicon wafer rotation grinding process, a double-sided grinding process, a TAIKO grinding process, a chemical mechanical grinding process, a polishing grinding process or a planetary disk grinding process can be used to perform a second thinning on the first wafer 10 after the first thinning; specifically, in this embodiment, a chemical mechanical grinding process is used to perform a second thinning on the first wafer 10 after the first thinning; the thickness of the second thinning can be ground from 81μm to 28μm, for example, the grinding thickness can be 41μm, 43μm, 45μm, 48μm or 53μm.

[0128] As an example, a grinding process, such as but not limited to a turntable grinding process, a silicon wafer rotation grinding process, a double-sided grinding process, a TAIKO grinding process, a chemical mechanical grinding process, a polishing grinding process or a planetary disk grinding process, can be used to perform a third thinning on the first wafer 10 after the second thinning; the thickness of the second thinning can be ground from 28μm to 25μm, for example, the grinding thickness can be 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm or 3μm.

[0129] In step S19 , referring to step S19 in FIG. 1 and FIG. 15 , a first wet etching is performed on the first wafer 10 after at least two thinnings.

[0130] As an example, wet etching is a technique for etching by immersing an etching medium in an etchant liquid; a mixture of hydrofluoric acid (HF), nitric acid (HNO3) and acetic acid (CH3COOH) (e.g., HNA etchant) can be used as an etching liquid but is not limited to performing a first wet etching on the first wafer 10 after at least two thinnings; the etching thickness of the first wet etching can be from 25 μm to 3.9 μm, for example, the etching thickness can be 5 μm, 10 μm, 15 μm, 20 μm, 21 μm or 21.1 μm; wet etching has the advantage of low-cost batch manufacturing, and 25 to 50 wafers can be etched at the same time.

[0131] In some embodiments, referring to FIG. 16 , after performing a first wet etching on the first wafer 10 after at least two thinning steps, the preparation method further includes:

[0132] Step S20 : ​​trimming the thinned bonding structure to obtain a second step 60 .

[0133] For example, the height of the second step 60 can be 20μm~40μm, for example, the height of the second step 60 can be 20μm, 25μm, 30μm, 35μm or 40μm; the distance from the edge of the second step 60 to the edge of the second wafer 40 can be 2mm~3mm, for example, the distance from the edge of the second step 60 to the edge of the second wafer 40 can be 2mm, 2.2mm, 2.4mm, 2.6mm, 2.8mm or 3mm.

[0134] In some embodiments, the width of the second step 60 is smaller than the width of the first step 30 .

[0135] In some embodiments, referring to FIG. 4 , after step S20 , the method for preparing the semiconductor structure may further include the following steps: S21 - S22 .

[0136] In step S21 , please continue to refer to FIG. 16 , the first wafer 10 in the second step 60 is thinned again.

[0137] As an example, the first wafer 10 in the second step 60 may be thinned again using, but not limited to, a chemical mechanical polishing process; the thinned thickness may be polished from 3.9 μm to 3.4 μm, for example, the polished thickness may be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm.

[0138] In step S22 , referring to FIG. 4 , a second wet etching is performed on the bonding structure.

[0139] As an example, a tetramethylammonium hydroxide (TMAH) solution may be used as an etching solution but is not limited to performing a second wet etching on the bonding structure; the etching thickness of the second wet etching may be from 3.4 μm to 3 μm, for example, the etching thickness may be 0.1 μm, 0.2 μm, 0.3 μm or 0.4 μm.

[0140] It should be noted that the etching solution used in the second wet etching is different from the etching solution used in the first wet etching.

[0141] An embodiment of the present application further provides a semiconductor structure, which can be obtained by using the method for preparing the semiconductor structure of any one of the above embodiments.

[0142] In the embodiment of the present application, by performing trimming after forming the bonding layer, the sharp drop in the thickness of the dielectric layer at the edge of the crystal is reduced or the height difference is reduced, thereby improving the bonding performance; at the same time, wafer cracking is avoided during the thinning process, thereby improving the yield of the semiconductor structure. Further, after obtaining the bonding structure, in the process of performing multiple thinning processes on the obtained structure, by forming a protective layer between the steps of the multiple thinning processes, the bonding interface can be protected from being corroded by the etching solution in the subsequent wet etching process, thereby improving the quality of the bonding structure and further improving the reliability of the semiconductor structure.

[0143] In summary, in the semiconductor structure and preparation method thereof provided in the embodiment of the present application, by performing trimming after forming the bonding layer, the unexpected effect is: reducing the sharp drop in the thickness of the dielectric layer at the crystal edge or the height difference, thereby improving the bonding performance; at the same time, avoiding cracking during the thinning process, and improving the yield of the semiconductor structure. Further, after obtaining the bonding structure, in the process of performing multiple thinning treatments on the obtained structure, by forming a protective layer between the steps of the multiple thinning treatments, the bonding interface can be protected from being corroded by the etching solution in the subsequent wet etching process, thereby improving the quality of the bonding structure, and further improving the reliability of the semiconductor structure.

[0144] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a first wafer; forming a bonding layer on the front side of the first wafer; Performing an edge trimming process on the first wafer formed with the bonding layer to form a first step; The bonding layer covers the front surface of the first step; Providing a second wafer, and bonding the first wafer after edge trimming to the surface of the second wafer via the bonding layer to obtain a bonding structure; Performing a first thinning on the first wafer from the back side; forming a protective layer, wherein the protective layer at least covers a surface of the first wafer away from the second wafer after the first thinning, a side wall of the first wafer after the first thinning, and a side wall of the bonding layer; removing the protective layer covering the surface of the first wafer away from the second wafer after the first thinning; Thinning the first wafer after the first thinning at least twice more; Performing a first wet etching on the first wafer after the at least two thinning steps.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the first wafer after the first thinning is less than the height of the first step.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the protective layer is 0.5KÅ~1.5KÅ.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: After performing the first wet etching on the first wafer after the at least two thinning steps, the preparation method further includes: trimming the bonding structure to obtain a second step.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The width of the second step is smaller than the width of the first step.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that: After trimming the bonding structure to obtain the second step, the method further includes: Thinning the first wafer in the second step again; The bonding structure is subjected to a second wet etching.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The step of forming a bonding layer on the front side of the first wafer includes: forming a bonding material layer on the front side of the first wafer; The bonding material layer is subjected to chemical mechanical polishing to obtain the bonding layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The step of forming a bonding material layer on the front side of the first wafer comprises: forming a first bonding material layer on the front surface of the first wafer; A second bonding material layer is formed on the front side of the first bonding material layer; the second bonding material layer and the first bonding material layer together constitute the bonding material layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The thickness of the first bonding material layer is 5KÅ~10KÅ; the thickness of the second bonding material layer is 40KÅ~50KÅ.

10. A semiconductor structure, characterized in that: The semiconductor structure is obtained by using the preparation method of any one of claims 1 to 9.

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