Dynamic frequency modulation method of stream multiprocessor of GPU (Graphics Processing Unit) and storage medium
By integrating the frequency division module in the GPU's stream multiprocessor SM, dynamically adjusting the clock frequency, the problem of low energy efficiency of existing GPUs is solved, and automatic adjustment of GPU frequency under different tasks is realized, improving the energy efficiency ratio and reducing energy Consumption.
Patent Information
- Application Number
- CN202411279425.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-01-14
AI Technical Summary
Existing GPUs cannot dynamically regulate frequency when handling different tasks, resulting in low energy efficiency and cannot reduce energy consumption while ensuring performance.
The frequency division module AFM is integrated into each stream multiprocessor SM of the GPU. Through the data acquisition and analysis modules DC and DA, the clock frequency is dynamically adjusted, and the frequency division coefficient is adjusted according to the number of instructions and energy consumption requirements of the task to achieve the GPU frequency. Automatic adjustment.
It improves the energy efficiency ratio of GPUs, reduces energy consumption, and provides a more efficient solution for the field of high-performance computing.
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Figure CN119311107A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of heterogeneous computing technology, for example, to a dynamic frequency modulation method and storage medium of a stream multiprocessor of a GPU. Background Art
[0002] As the demand for computer graphics processing continues to grow, GPUs (graphics processing units) are playing an increasingly important role in games, film and television production, scientific computing, artificial intelligence and other fields. With its highly parallel processing capabilities and powerful floating-point computing performance, GPUs have become a key component in the field of high-performance computing. However, as GPU performance improves, its power consumption and heat generation issues are becoming increasingly prominent. How to reduce energy consumption and improve energy efficiency while ensuring performance has become an important challenge in current GPU design.
[0003] Traditional GPUs are fixed to work in the highest performance mode. Although they can provide powerful processing capabilities, in many application scenarios, GPUs do not need to always run at the highest frequency. For example, when performing lightweight graphics rendering tasks or in idle state, the high-performance mode of the GPU will lead to resource waste and increased energy consumption. However, the existing solutions cannot dynamically adjust the frequency of the GPU according to actual task requirements, which makes the GPU energy efficiency relatively low.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0006] The embodiment of the present disclosure provides a method for dynamically adjusting the frequency of a stream multiprocessor of a GPU, including: A frequency division module AFM and an automatic frequency modulation module are integrated in each stream multiprocessor SM of the GPU. The frequency division module AFM is used to provide an independent and adjustable clock for each SM. The master clock of all SMs passes through the frequency division module inside each SM to provide clocks to each SM. AFM includes a data acquisition module DC and a data analysis module DA. DC collects the number of instructions executed by its SM in each epoch, and then divides it by the cycle of each epoch to obtain the average number of instructions per second (IPS) of the SM in each epoch. According to the IPS of the previous epoch and the average IPS of all past epochs of this task, determine whether the clock frequency of the SM to which it belongs meets the energy consumption and performance requirements. If it does not meet the requirements, make corresponding adjustments to the division coefficient of the SM division module to which it belongs.
[0007] In some embodiments, in the process of obtaining the average value of the number of instructions per second IPS of the SM in each epoch, the method further includes: A fixed number of clock cycles is set as an epoch. The period of each epoch is obtained by dividing the number of clock cycles in the epoch by the clock frequency of the SM in the epoch. After each epoch, DC sends the calculated average IPS value to DA. DA records the IPS of the currently completed epoch, updates the average IPS of all past epochs of this task, and updates the number of the currently completed epoch.
[0008] In some embodiments, the update formula of the average IPS of all past epochs is as follows: IPSave<= (Nepoch × IPSave + IPSepoch) / (Nepoch + 1); Nepoch <= Nepoch + 1; Among them, IPSepoch is the IPS of the currently completed epoch, IPSave is the average IPS of all past epochs of this task, and Nepoch is the number of the currently completed epoch.
[0009] In some embodiments, the method further comprises: When the host dispatches a computing task to the GPU, the GPU determines the required IPS range based on the energy consumption and performance requirements of the task, and sends it to the DA of all SMs that execute the task. At the same time, the host sets an initial value for the division coefficient of the division module and clears the Nepoch of the DA of each SM.
[0010] In some embodiments, the method further comprises: The host determines the number of streaming multiprocessors (SMs) to allocate based on the size of the computing task.
[0011] In some embodiments, the method further comprises: The upper and lower limits of the IPS range of the task are denoted as IPSupper and IPSlower respectively; If the IPSepoch obtained by DA and the calculated IPSave are both less than IPSlower after the epoch is executed, it proves that the IPS of the task is too small and does not meet the performance requirements. The frequency division coefficient of the frequency division module is reduced by 1 to improve the IPS of the task; If IPSepoch and IPSave are both greater than IPSupper, it proves that the IPS of the task is too large and does not meet the energy consumption requirements. The division coefficient of the division module is increased by 1 to reduce the IPS of the task.
[0012] In some embodiments, the method further comprises: If IPSepoch and IPSave are neither less than IPSlower nor greater than IPSlower, no adjustment is made to the frequency division coefficient.
[0013] The storage medium provided in the embodiment of the present disclosure stores program instructions, which, when running, execute the dynamic frequency modulation method of the stream multiprocessor of the GPU in the above embodiment.
[0014] The dynamic frequency modulation method of the stream multiprocessor of the GPU and the storage medium provided in the embodiments of the present disclosure can achieve the following technical effects: It can realize automatic adjustment of GPU frequency under different tasks, thereby improving energy efficiency, reducing energy consumption, and providing strong support for the development of high-performance computing.
[0015] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein: Figure 1 It is a flowchart of a dynamic frequency modulation method of a stream multiprocessor of a GPU provided by an embodiment of the present disclosure; Figure 2 is a structural block diagram of a clock system provided by an embodiment of the present disclosure; Figure 3 is a system structure block diagram provided by an embodiment of the present disclosure; Figure 4 is a flow chart of a system provided by an embodiment of the present disclosure; Figure 5 It is a structural schematic diagram of a dynamic frequency modulation system of a stream multiprocessor of a GPU provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0017] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0018] The terms "first", "second", etc. in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0019] Unless otherwise stated, the term "plurality" means two or more.
[0020] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.
[0021] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.
[0022] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0023] The following describes a dynamic frequency modulation method for a stream multiprocessor of a GPU and a storage medium provided by an embodiment of the present disclosure in conjunction with the accompanying drawings.
[0024] Figure 1 is a flowchart of a dynamic frequency modulation method for a stream multiprocessor of a GPU provided by an embodiment of the present disclosure, Figure 2 is a structural block diagram of a clock system provided by an embodiment of the present disclosure, Figure 3 is a system structure block diagram provided by an embodiment of the present disclosure, Figure 4 1 is a flow chart of a system provided by an embodiment of the present disclosure. Figure 2 - Figure 4 ,right Figure 1 A dynamic frequency scaling method for a streaming multiprocessor of a GPU is described.
[0025] like Figure 1 As shown, the dynamic frequency adjustment method of the stream multiprocessor of the GPU may include: S01, integrates a frequency division module AFM and an automatic frequency modulation module in each stream multiprocessor SM of the GPU. The frequency division module AFM is used to provide an independent and adjustable clock for each SM. The master clock of all SMs passes through the frequency division module inside each SM to provide clocks to each SM; S02, AFM includes a data acquisition module DC and a data analysis module DA. DC collects the number of instructions executed by its SM in each epoch, and then divides it by the cycle of each epoch to obtain the average number of instructions per second IPS of the SM in each epoch; S03, based on the IPS of the previous epoch and the average IPS of all past epochs of this task, determines whether the clock frequency of the SM to which it belongs meets the energy consumption and performance requirements. If it does not meet the requirements, the division coefficient of the division module of the SM to which it belongs is adjusted accordingly.
[0026] The present disclosure can realize automatic adjustment of GPU frequency under different tasks, thereby improving the energy efficiency ratio of the GPU, reducing energy consumption, and providing strong support for the development of the high-performance computing field.
[0027] In some embodiments, in the process of obtaining the average value of the number of instructions per second IPS of the SM in each epoch, Figure 1 The method may also include: A fixed number of clock cycles is set as an epoch. The period of each epoch is obtained by dividing the number of clock cycles in the epoch by the clock frequency of the SM in the epoch. After each epoch, DC sends the calculated average IPS value to DA. DA records the IPS of the currently completed epoch, updates the average IPS of all past epochs of this task, and updates the number of the currently completed epoch.
[0028] In some embodiments, the update formula of the average IPS of all past epochs is as follows: IPSave<= (Nepoch × IPSave + IPSepoch) / (Nepoch + 1); Nepoch <= Nepoch + 1; Among them, IPSepoch is the IPS of the currently completed epoch, IPSave is the average IPS of all past epochs of this task, and Nepoch is the number of the currently completed epoch.
[0029] In some embodiments, Figure 1 The method may also include: When the host dispatches a computing task to the GPU, the GPU determines the required IPS range based on the energy consumption and performance requirements of the task, and sends it to the DA of all SMs that execute the task. At the same time, the host sets an initial value for the division coefficient of the division module and clears the Nepoch of the DA of each SM.
[0030] In some embodiments, Figure 1 The method may also include: The host determines the number of streaming multiprocessors (SMs) to allocate based on the size of the computing task.
[0031] In some embodiments, Figure 1 The method may also include: The upper and lower limits of the IPS range of the task are denoted as IPSupper and IPSlower respectively; If the IPSepoch obtained by DA and the calculated IPSave are both less than IPSlower after the epoch is executed, it proves that the IPS of the task is too small and does not meet the performance requirements. The frequency division coefficient of the frequency division module is reduced by 1 to improve the IPS of the task; If IPSepoch and IPSave are both greater than IPSupper, it proves that the IPS of the task is too large and does not meet the energy consumption requirements. The division coefficient of the division module is increased by 1 to reduce the IPS of the task.
[0032] In some embodiments, Figure 1 The method may also include: If IPSepoch and IPSave are neither less than IPSlower nor greater than IPSlower, no adjustment is made to the frequency division coefficient.
[0033] In a specific example, it should be noted that a GPU is generally composed of multiple stream multiprocessors (SMs). In order to implement the automatic frequency modulation function for each SM to meet the requirements of different real-time tasks, a frequency division module and an automatic frequency modulation module (AFM) are integrated in each SM. The frequency division module is responsible for providing an independent and adjustable clock for each SM, such as Figure 2As shown, the master clock of all SMs provides clocks to each SM through the frequency division module inside each SM. AFM includes a data collection module (Data Collector, DC) and a data analysis module (Data Analyzer, DA). DC collects the number of instructions executed by the SM to which it belongs in each epoch, and then divides it by the cycle of each epoch to obtain the average number of instructions per second (IPS) of the SM in each epoch. Here, a fixed number of clock cycles is set as an epoch, and the cycle of each epoch is obtained by dividing the number of clock cycles in the epoch by the clock frequency of the SM in the epoch. After each epoch, DC sends the calculated IPS average value to DA. DA first records the IPS of the currently completed epoch, then updates the average IPS of all past epochs of this task, and finally updates the number of the currently completed epoch. The update formula for the average IPS of all past epochs of this task is as follows: IPSave<= (Nepoch × IPSave + IPSepoch) / (Nepoch + 1); Nepoch <= Nepoch + 1; Among them, IPSepoch is the IPS of the currently completed epoch, IPSave is the average IPS of all past epochs of this task, and Nepoch is the number of the currently completed epoch.
[0034] Based on the IPS of the previous epoch and the average IPS of all previous epochs of this task, determine whether the clock frequency of the SM to which it belongs meets the energy consumption and performance requirements. If it does not meet the requirements, make corresponding adjustments to the frequency division coefficient of the SM frequency division module to which it belongs. The method for judging whether it meets the energy consumption and performance requirements and the method for adjusting the frequency division coefficient are given in the following content. The structural block diagram of the system is shown in the figure. Figure 3 shown.
[0035] When the host dispatches a computing task to the GPU, it determines the required IPS range based on the energy consumption and performance requirements of the task, and sends it to the DA of all SMs that execute the task. At the same time, the host sets an initial value for the division coefficient of the division module and clears the Nepoch of the DA of each SM.
[0036] For the convenience of description, the upper and lower limits of the IPS range of the task are represented as IPSupper and IPSlower respectively. If the IPSepoch obtained by DA and the calculated IPSave are both less than IPSlower after the epoch is executed, it proves that the IPS of the task is too small and does not meet the performance requirements. The division coefficient of the division module is reduced by 1 to increase the IPS of the task; if IPSepoch and IPSave are both greater than IPSupper, it proves that the IPS of the task is too large and does not meet the energy consumption requirements. The division coefficient of the division module is increased by 1 to reduce the IPS of the task; for situations where the above two conditions are not met, no adjustment is made to the division coefficient. The flow chart of the system is shown as follows. Figure 4 shown.
[0037] In order to make the process of the present invention clearer, the following Figure 4 The corresponding system flow chart takes an image classification task as an example to describe the dynamic frequency modulation process of the stream multiprocessor when the GPU executes the task.
[0038] S1. The host allocates 3 SMs to the image classification task according to the task scale. According to the energy consumption and performance requirements of the classification task, the upper limit of the task IPS is set to TASK_IPS_UPPER and the lower limit is set to TASK_IPS_LOWER. S2. The host specifies the initial frequency division coefficient DIV0 for the three SMs; S3, the host transfers the code and data of the image classification task to the three SMs allocated in step S1, and inputs the values of TASK_IPS_UPPER and TASK_IPS_LOWER to the DA modules of the three SMs, sets the values of the frequency division modules of the three SMs to DIV0, and clears the Nepoch of the DA in the three SMs; S4, the host starts three SMs, and the three SMs perform computing tasks according to the set frequency. During the task execution, the DC of each SM accumulates the number of all instructions executed by the SM; At the end of S5, the DC of each SM calculates the average IPS of this epoch based on the accumulated value of the number of instructions and sends it to their respective DAs. At the same time, the accumulated value of the number of instructions is reset to zero; S6. After receiving the average IPS, the DA of each SM updates its IPSepoch, IPSave, and Nepoch values; S7, determine whether the values of IPSepoch and IPSave after each SM update are both less than TASK_IPS_LOWER or both greater than TASK_IPS_UPPER; S8. If the values of IPSepoch and IPSave are both less than TASK_IPS_LOWER, the frequency division coefficient of the corresponding SM frequency division module is reduced by 1; if the values of IPSepoch and IPSave are both greater than TASK_IPS_UPPER, the frequency division coefficient of the corresponding SM frequency division module is increased by 1; otherwise, the frequency division coefficient remains unchanged; S9. Continue the operation of the next epoch.
[0039] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.
[0040] Combination Figure 5 As shown, the embodiment of the present disclosure provides a dynamic frequency modulation system 500 for a stream multiprocessor of a GPU, including a processor 504 and a memory 501. Optionally, the system may also include a communication interface 502 and a bus 503. The processor 504, the communication interface 502, and the memory 501 may communicate with each other through the bus 503. The communication interface 502 may be used for information transmission. The processor 504 may call the logic instructions in the memory 501 to execute the dynamic frequency modulation method for the stream multiprocessor of the GPU in the above embodiment.
[0041] In addition, the logic instructions in the memory 501 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.
[0042] The memory 501 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 504 executes the functional application and data processing by running the program instructions / modules stored in the memory 501, that is, the dynamic frequency modulation method of the stream multiprocessor of the GPU in the above embodiment is implemented.
[0043] The memory 501 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 501 may include a high-speed random access memory and may also include a non-volatile memory.
[0044] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute a dynamic frequency modulation method for a stream multiprocessor of a GPU.
[0045] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.
[0046] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.
[0047] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or including (comprising) refer to the existence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or these groups. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same or similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.
[0048] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. Technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. Technicians can clearly understand that for the convenience and simplicity of description, the specific working process of the systems, devices and units described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.
[0049] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.
[0050] The flowchart and block diagram in the accompanying drawings show the possible architecture, functions and operations of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a part of the module, program segment or code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.
Claims
1. A dynamic frequency modulation method for a stream multiprocessor of a GPU, characterized in that: The method comprises: A frequency division module AFM and an automatic frequency modulation module are integrated in each stream multiprocessor SM of the GPU. The frequency division module AFM is used to provide an independent and adjustable clock for each SM. The master clock of all SMs passes through the frequency division module inside each SM to provide clocks to each SM. AFM includes a data acquisition module DC and a data analysis module DA. DC collects the number of instructions executed by its SM in each epoch, and then divides it by the cycle of each epoch to obtain the average number of instructions per second (IPS) of the SM in each epoch. According to the IPS of the previous epoch and the average IPS of all past epochs of this task, determine whether the clock frequency of the SM to which it belongs meets the energy consumption and performance requirements. If it does not meet the requirements, make corresponding adjustments to the division coefficient of the SM division module to which it belongs.
2. The method according to claim 1, characterized in that In the process of obtaining the average value of the number of instructions per second IPS of the SM in each epoch, the method further includes: A fixed number of clock cycles is set as an epoch. The period of each epoch is obtained by dividing the number of clock cycles in the epoch by the clock frequency of the SM in the epoch. After each epoch, DC sends the calculated average IPS value to DA. DA records the IPS of the currently completed epoch, updates the average IPS of all past epochs of this task, and updates the number of the currently completed epoch.
3. The method according to claim 2, characterized in that The update formula for the average IPS of all past epochs is as follows: IPSave <= (Nepoch × IPSave + IPSepoch) / (Nepoch + 1); Nepoch <= Nepoch + 1; Among them, IPSepoch is the IPS of the currently completed epoch, IPSave is the average IPS of all past epochs of this task, and Nepoch is the number of the currently completed epoch.
4. The method according to claim 1, characterized in that: The method further comprises: When the host dispatches a computing task to the GPU, the GPU determines the required IPS range based on the energy consumption and performance requirements of the task, and sends it to the DA of all SMs that execute the task. At the same time, the host sets an initial value for the division coefficient of the division module and clears the Nepoch of the DA of each SM.
5. The method according to claim 4, characterized in that The method further comprises: The host determines the number of streaming multiprocessors (SMs) to allocate based on the size of the computing task.
6. The method according to claim 4, characterized in that The method further comprises: The upper and lower limits of the IPS range of the task are denoted as IPSupper and IPSlower respectively; If the IPSepoch obtained by DA and the calculated IPSave are both less than IPSlower after the epoch is executed, it proves that the IPS of the task is too small and does not meet the performance requirements. The frequency division coefficient of the frequency division module is reduced by 1 to improve the IPS of the task; If IPSepoch and IPSave are both greater than IPSupper, it proves that the IPS of the task is too large and does not meet the energy consumption requirements. The division coefficient of the division module is increased by 1 to reduce the IPS of the task.
7. The method according to claim 6, characterized in that The method further comprises: If IPSepoch and IPSave are neither less than IPSlower nor greater than IPSlower, no adjustment is made to the frequency division coefficient.
8. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-7.