Gallium oxide junction barrier Schottky diode and preparation method thereof

Abstract

The invention discloses a gallium oxide junction barrier Schottky diode and a preparation method thereof, and relates to the technical field of Schottky diodes. The diode comprises a cathode, a gallium oxide substrate and a gallium oxide drift layer which are sequentially stacked from bottom to top, wherein the upper surface of the gallium oxide drift layer is of a boss structure; the boss structure comprises a convex part and a shoulder part; the first dielectric layer comprises a dielectric layer A of which the relative dielectric constant is greater than or equal to 9 and a dielectric layer B of which the breakdown electric field intensity is greater than or equal to 8MV / cm, which are stacked from bottom to top; the anode is positioned on the surface of the lug boss; the second dielectric layer is positioned on the surface of the lug boss and on the side surface of the anode; the metal field plate is located on the second dielectric layer; the P-type semiconductor layer covers the metal field plate, the second dielectric layer, the side surface of the convex part, the surface of the shoulder part and the surface of the first dielectric layer; and the third dielectric layer covers the side surface of the anode part, the surface of the P-type semiconductor layer and the surface of the first dielectric layer part. The device can bear higher reverse breakdown voltage.

Description

Technical Field

[0001] The invention relates to the technical field of Schottky diodes, and in particular to a gallium oxide junction barrier Schottky diode and a preparation method thereof. Background Art

[0002] Ultra-wide bandgap semiconductor-gallium oxide (Ga2O3) is a new type of high-power semiconductor material that has emerged in recent years. Among them, the bandgap width of β-Ga2O3 is 4.6-4.9eV, the critical breakdown electric field is 8MV / cm, which is more than twice the critical breakdown electric field of SiC and GaN, and the electron mobility is 250-300cm at 300K. 2 / V·s, and the saturation electron velocity is 2×10 7 cm / s. These superior physical properties result in the Baliga figure of merit of β-Ga2O3 being around 3000, much greater than that of SiC and GaN, and it has great potential for development in terms of high breakdown voltage and high power. In particular, β-Ga2O3 can be prepared by melt growth method, which provides great hope for the realization of low-cost commercial substrates, which is superior to the growth technology of SiC, GaN, AlN and diamond.

[0003] Most of the electric field of ordinary gallium oxide Schottky diodes (SBD, Schottky Barrier Diode, also known as Schottky barrier diodes) is concentrated in the area where the drift layer surface contacts the Schottky metal. The electric field on the Schottky surface will cause a more serious barrier lowering effect, which makes the Schottky diode face the problems of large reverse leakage current and low reverse blocking performance, making the withstand voltage and power quality factor of gallium oxide Schottky diodes unable to exert the potential of the material itself. In order to eliminate the negative impact of the electric field concentration effect as much as possible and improve the electric field distribution of the device, the junction termination technology is widely used and has become an important means to improve the breakdown characteristics of the device. The junction termination technology reduces the peak electric field on the semiconductor surface by constructing different device structures. Among them, the field plate structure is to first grow an oxide layer on the semiconductor surface by process means, and then extend the anode metal to the top of the oxide layer. The field plate metal is equivalent to the extension of the anode metal. Its principle is that when a reverse bias voltage is applied, a part of the electric field lines emitted by the positive charge in the depletion region at the edge of the Schottky main junction can be terminated on the field plate metal, which slows down the electric field concentration and reduces the electric field peak of the Schottky main junction. The introduction of a field plate can ease the electric field at the junction edge, but at the same time it will introduce a new high electric field at the edge of the field plate.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0005] Based on the above-mentioned deficiencies of the prior art, the purpose of the present invention is to provide a gallium oxide junction barrier Schottky diode and a preparation method thereof, aiming to solve the problem that when the electric field concentration effect of the device is solved by introducing a field plate structure, a new high electric field will be introduced at the edge of the field plate, thereby affecting the device's anti-breakdown performance.

[0006] The technical solution of the present invention is as follows:

[0007] In a first aspect of the present invention, a gallium oxide junction barrier Schottky diode is provided, wherein the gallium oxide junction barrier Schottky diode comprises a cathode, a gallium oxide substrate, and a gallium oxide drift layer which are stacked in sequence from bottom to top; the upper surface of the gallium oxide drift layer is a boss structure, and the boss structure comprises a protrusion and a shoulder;

[0008] The gallium oxide junction barrier Schottky diode further comprises:

[0009] a first dielectric layer, located on the shoulder;

[0010] an anode located on the surface of the protrusion;

[0011] A second dielectric layer is located on the surface of the protrusion and on the side of the anode;

[0012] A metal field plate, located on the second dielectric layer, and one end of the metal field plate is connected to a side surface of the anode;

[0013] A P-type semiconductor layer continuously covers the surface of the metal field plate, the side of the metal field plate, the side of the second dielectric layer, the side of the protrusion, the shoulder surface, the side of the first dielectric layer, and a part of the surface of the first dielectric layer;

[0014] A third dielectric layer continuously covers the side surface of the anode portion, the surface of the P-type semiconductor layer and the surface of the first dielectric layer;

[0015] The first dielectric layer includes a dielectric layer A and a dielectric layer B stacked from bottom to top, the relative dielectric constant of the dielectric layer A is greater than or equal to 9, and the breakdown electric field strength of the dielectric layer B is greater than or equal to 8 MV / cm.

[0016] Optionally, the gallium oxide substrate has a thickness of 500 to 650 μm;

[0017] The gallium oxide substrate is a highly doped N-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 .

[0018] Optionally, the gallium oxide drift layer has a thickness of 5 to 20 μm, and the protrusion has a height of 0.2 to 4 μm;

[0019] The gallium oxide drift layer is a low-doped N-type gallium oxide drift layer with a doping concentration of 10 16 ~5.0×10 17 cm -3 .

[0020] Optionally, the thickness of the A dielectric layer is 30-100 nm, and the thickness of the B dielectric layer is 30-400 nm;

[0021] The A dielectric layer includes an A dielectric material, and the A dielectric material includes at least one of aluminum oxide and hafnium oxide; the B dielectric layer includes a B dielectric material, and the B dielectric material includes at least one of silicon nitride and silicon dioxide.

[0022] Optionally, the second dielectric layer comprises a C dielectric layer and a D dielectric layer stacked from bottom to top, the C dielectric layer has a thickness of 30 to 100 nm, and the D dielectric layer has a thickness of 30 to 400 nm;

[0023] The C dielectric layer includes a C dielectric material, wherein the C dielectric material includes one of aluminum oxide and hafnium oxide. The D dielectric layer includes a D dielectric material, wherein the D dielectric material includes one of silicon nitride and silicon dioxide.

[0024] Optionally, the thickness of the P-type semiconductor layer is 100-400 nm;

[0025] The P-type semiconductor layer includes a P-type semiconductor, and the doping concentration of the P-type semiconductor is 10 17 ~10 19 cm -3 ;

[0026] The P-type semiconductor includes at least one of P-type nickel oxide, P-type gallium nitride, P-type gallium oxide and P-type cuprous oxide.

[0027] Optionally, the materials of the cathode, anode and metal field plate each independently include at least one of Al, Au, Ni, Pt, Cu, Ti, Ag and TiN;

[0028] The width of the metal field plate is 1-10 μm, and the width refers to the distance from one end of the metal field plate connected to the anode to the other end opposite thereto.

[0029] A second aspect of the present invention provides a method for preparing the gallium oxide junction barrier Schottky diode as described above, comprising the following steps:

[0030] providing a gallium oxide substrate;

[0031] forming a gallium oxide drift layer on the gallium oxide substrate; the upper surface of the gallium oxide drift layer is a boss structure, and the boss structure includes a protrusion and a shoulder;

[0032] forming a first dielectric layer on the shoulder, wherein the first dielectric layer comprises a dielectric layer A and a dielectric layer B stacked from bottom to top, the relative dielectric constant of the dielectric layer A is greater than or equal to 9, and the breakdown electric field strength of the dielectric layer B is greater than or equal to 8 MV / cm;

[0033] forming an anode on a surface of the protrusion;

[0034] forming a second dielectric layer on the surface of the protrusion and on the side of the anode;

[0035] forming a metal field plate on the second dielectric layer and on a side of the anode;

[0036] Forming a P-type semiconductor layer on the surface of the metal field plate, the side of the metal field plate, the side of the second dielectric layer, the side of the protrusion, the surface of the shoulder, the side of the first dielectric layer, and a partial surface of the first dielectric layer;

[0037] Forming a third dielectric layer on the side of the anode, the surface of the P-type semiconductor layer and the surface of the first dielectric layer;

[0038] A cathode is formed on a surface of the gallium oxide substrate facing away from the gallium oxide drift layer.

[0039] Optionally, the method for preparing the gallium oxide junction barrier Schottky diode specifically comprises the following steps:

[0040] Providing a gallium oxide substrate having a gallium oxide epitaxial layer on the surface;

[0041] forming a second dielectric layer precursor layer on the gallium oxide epitaxial layer; forming a first photoresist film on both sides of the second dielectric layer precursor layer to obtain a first semi-finished product;

[0042] Forming a first metal layer on the upper surface of the first semi-finished product, and stripping off the first photoresist film to obtain a second semi-finished product;

[0043] Etching both sides of the first metal layer of the second semi-finished product to a depth reaching the gallium oxide epitaxial layer, thereby forming a first groove and a gallium oxide drift layer, thereby obtaining a third semi-finished product;

[0044] Forming a dielectric layer A precursor layer and a dielectric layer B precursor layer stacked in sequence on the upper surface of the third semi-finished product, forming a second photoresist film on both end regions of the dielectric layer B precursor layer at the bottom of the first groove, then etching away the dielectric layer A precursor layer and the dielectric layer B precursor layer outside the region covered by the second photoresist film to form the dielectric layer A and the dielectric layer B, and then removing the second photoresist film to obtain a fourth semi-finished product;

[0045] forming a third photoresist film on the middle region of the first metal layer of the fourth semi-finished product and on both end regions of the B dielectric layer to obtain a fifth semi-finished product;

[0046] forming a P-type semiconductor layer precursor layer on the upper surface of the fifth semi-finished product, and then stripping off the third photoresist film while forming a P-type semiconductor layer to obtain a sixth semi-finished product;

[0047] A third dielectric layer precursor layer is formed on the upper surface of the sixth semi-finished product, and then a fourth photoresist film is formed at both ends of the third dielectric layer precursor layer, and the projection of the fourth photoresist film on the first metal layer covers a portion of the first metal layer, and then the third dielectric layer precursor layer, the first metal layer and the second dielectric layer precursor layer in the area not covered by the fourth photoresist film are etched away to form a second groove, a second dielectric layer, a third dielectric layer and a metal field plate;

[0048] Then, the fourth photoresist film is removed, an anode is formed in the second groove and on the third dielectric layer, and a cathode is formed on the side of the gallium oxide substrate away from the gallium oxide drift layer to obtain a gallium oxide junction barrier Schottky diode.

[0049] Optionally, the A dielectric layer precursor layer, the B dielectric layer precursor layer and the third dielectric layer precursor layer are each independently formed by chemical deposition or physical deposition.

[0050] Beneficial effects: The gallium oxide junction barrier Schottky diode provided by the present invention is specifically a gallium oxide junction barrier Schottky diode with a composite terminal structure of a groove and a field plate, wherein the introduction of the field plate structure solves the problem of electric field concentration at the edge of the anode of the Schottky diode, and at the same time forms a groove at the edge of the anode to alleviate the high electric field at the end of the field plate, thereby solving the problem of a high electric field at the edge of the field plate of the existing Schottky diode with a field plate structure. Furthermore, a junction barrier Schottky diode structure is formed by introducing a P-type semiconductor layer and a gallium oxide drift layer to construct a heterojunction, and the mutual depletion between the P-type semiconductor and the gallium oxide junction makes the electric field on the surface of the gallium oxide drift layer uniformly distributed, and the balanced electric field alleviates the electric field concentration at the corners of the groove, while providing lateral electric field depletion to alleviate the electric field below the anode. In addition, the presence of the P-type semiconductor layer at the corners of the groove further alleviates the electric field concentration at the corners of the groove, further improving the blocking ability of the device. Furthermore, the electric field concentration at the edge of the P-type semiconductor layer is borne by the first dielectric layer, wherein the A dielectric layer with a higher dielectric constant is used to modulate the surface electric field of the gallium oxide drift layer to make it uniformly distributed, and the B dielectric layer with a higher critical breakdown electric field is used to avoid breakdown of the first dielectric layer. In the device of the structure provided by the present invention, when forward-conducting, the conductivity modulation effect at the PN junction greatly reduces the specific on-resistance during forward conduction; in the case of surge, the contact area of ​​the P type is increased, and the ability to resist surge is increased; during dynamic avalanche breakdown, a P channel is provided, so that the electron holes generated by the avalanche can be better transmitted, and the device's ability to resist dynamic avalanche is improved. Therefore, the device of the structure provided by the present invention has a lower specific on-resistance (excellent front conduction characteristics), can withstand a higher reverse breakdown voltage, and has excellent performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 Schematic diagram of the structure of a gallium oxide substrate having a gallium oxide epitaxial layer on its surface.

[0052] Figure 2 It is a schematic diagram of sequentially forming a C dielectric layer precursor layer and a D dielectric layer precursor layer stacked on a gallium oxide epitaxial layer.

[0053] Figure 3 A schematic diagram of forming a first photoresist film on both sides of a D dielectric layer precursor layer to obtain a first semi-finished product.

[0054] Figure 4 It is a schematic diagram of forming a first metal layer on the upper surface of a first semi-finished product.

[0055] Figure 5 A schematic diagram of stripping off the first photoresist film to obtain a second semi-finished product.

[0056] Figure 6Schematic diagram of a third semi-finished product obtained by etching both sides of the first metal layer of the second semi-finished product to form a first groove.

[0057] Figure 7 It is a schematic diagram of forming a dielectric layer precursor layer A and a dielectric layer precursor layer B stacked in sequence on the upper surface of the third semi-finished product.

[0058] Figure 8 It is a schematic diagram of forming a second photoresist film on the two end regions of the B dielectric layer precursor layer on the bottom of the first groove.

[0059] Fig. 9 It is a schematic diagram of etching away the A dielectric layer precursor layer and the B dielectric layer precursor layer outside the area covered by the second photoresist film.

[0060] Fig.10 A schematic diagram of a fourth semi-finished product obtained by removing the second photoresist film.

[0061] Fig.11 A schematic diagram of a fifth semi-finished product is obtained by forming a third photoresist film on the middle region of the first metal layer and on both end regions of the B dielectric layer of the fourth semi-finished product.

[0062] Fig.12 It is a schematic diagram of forming a P-type semiconductor layer precursor layer on the upper surface of the fifth semi-finished product.

[0063] Fig.13 Schematic diagram of stripping off the third photoresist film to obtain the sixth semi-finished product.

[0064] Fig.14 It is a schematic diagram of forming a third dielectric layer precursor layer on the upper surface of the sixth semi-finished product.

[0065] Fig.15 It is a schematic diagram of forming a fourth photoresist film at both ends of the third dielectric layer.

[0066] Fig.16 It is a schematic diagram of etching away the third dielectric layer precursor layer, the first metal layer and the second dielectric layer precursor layer in the area not covered by the projection of the fourth photoresist film on the horizontal plane.

[0067] Fig.17 To remove Fig.16 Schematic diagram of the fourth photoresist film.

[0068] Fig.18 A schematic diagram of forming an anode in the second groove and on the third dielectric layer.

[0069] Fig.19 Schematic diagram of the structure of a gallium oxide junction barrier Schottky diode.

[0070] Fig. 20Schematic diagram of the structure of the gallium oxide drift layer.

[0071] Fig.21 Graph showing reverse characteristic of each Schottky diode in Example 1, Comparative Example 1 and Comparative Example 2.

[0072] Fig. 22 Surface electric field distribution curves of the Schottky diodes in Example 1, Comparative Example 1 and Comparative Example 2 are shown.

[0073] Markings in the attached drawings:

[0074] 1. cathode; 2. gallium oxide substrate; 3. gallium oxide drift layer; 31. raised portion; 32. shoulder; 3', gallium oxide epitaxial layer; 4. A dielectric layer; 4', A dielectric layer precursor layer; 40, first dielectric layer; 5. B dielectric layer; 5', B dielectric layer precursor layer; 6. P-type semiconductor layer; 6', P-type semiconductor layer precursor layer; 7. C dielectric layer; 7', C dielectric layer precursor layer; 70, second dielectric layer; 70', second dielectric layer precursor layer; 8. D dielectric layer; 8', D dielectric layer precursor layer; 9. anode; 10. metal field plate; 10', first metal layer; 11. third dielectric layer; 11', third dielectric layer precursor layer; 12. first groove; 13. second groove; a. first photoresist film; b. second photoresist film; c. third photoresist film; d. fourth photoresist film. DETAILED DESCRIPTION

[0075] The present invention provides a gallium oxide junction barrier Schottky diode and a method for preparing the same. To make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0076] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0077] The terms used herein such as “vertical”, “horizontal”, “upper”, “lower”, “left”, “right” and similar expressions are for illustrative purposes only and do not represent the only implementations.

[0078] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0079] If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features.

[0080] An embodiment of the present invention provides a gallium oxide junction barrier Schottky diode, wherein: Fig.19 and Fig. 20 As shown, the gallium oxide junction barrier Schottky diode comprises a cathode 1, a gallium oxide substrate 2, and a gallium oxide drift layer 3 which are stacked in sequence from bottom to top; the upper surface of the gallium oxide drift layer 3 is a boss structure, and the boss structure comprises a protrusion 31 and a shoulder 32 (that is, there are groove structures on both sides of the upper surface of the gallium oxide drift layer);

[0081] The gallium oxide junction barrier Schottky diode further comprises:

[0082] A first dielectric layer 40, located on the shoulder 32;

[0083] an anode 9, located on the surface of the protrusion 31;

[0084] A second dielectric layer 70 is located on the surface of the protrusion 31 and on the side of the anode 9;

[0085] A metal field plate 10 is located on the second dielectric layer 70, and one end of the metal field plate 10 is connected to a side surface of the anode 9;

[0086] The P-type semiconductor layer 6 continuously covers the surface of the metal field plate 10, the side of the metal field plate 10, the side of the second dielectric layer 70, the side of the protrusion 31, the surface of the shoulder 32, the side of the first dielectric layer 40, and a part of the surface of the first dielectric layer 40;

[0087] The third dielectric layer 11 continuously covers the side surface of the anode 9, the surface of the P-type semiconductor layer 6 and the surface of the first dielectric layer 40, and the two ends of the third dielectric layer have a groove structure;

[0088] Among them, the first dielectric layer includes an A dielectric layer 4 and a B dielectric layer 5 stacked from bottom to top, the relative dielectric constant of the A dielectric layer (the value of the relative dielectric constant is equal to the ratio of the capacitance of a capacitor of the same size made with the A dielectric layer material as the medium to that made with vacuum as the medium) is greater than or equal to 9, and the breakdown electric field strength of the B dielectric layer is greater than or equal to 8MV / cm.

[0089] The gallium oxide junction barrier Schottky diode provided by the embodiment of the present invention is specifically a gallium oxide junction barrier Schottky diode with a trench and field plate composite terminal structure, which has both the excellent front conduction characteristics of the Schottky diode and the reverse withstand voltage characteristics of the PN junction barrier. When forward conducting, because the front working voltage of the Schottky barrier is less than the PN junction barrier opening voltage, it is mainly the Schottky barrier that is turned on, and the current flows to the cathode through the Schottky barrier; when reverse cutoff, due to the shielding of the PN junction barrier, the reverse voltage of the Schottky contact is blocked, and the Schottky contact is protected. The reverse cutoff is mainly completed by the PN junction barrier, so the structure has the advantages of high withstand voltage and low reverse leakage current.

[0090] In the embodiment of the present invention, the introduction of the field plate structure can make a part of the electric field lines emitted by the positive charge in the depletion region at the edge of the Schottky main junction terminate on the field plate metal, which reduces the electric field concentration, suppresses the electric field peak on the surface of the gallium oxide drift layer at the edge of the anode, solves the problem of electric field concentration at the edge of the anode of the Schottky diode, and forms a groove at the edge of the anode, resulting in the expansion of the depletion region, reducing the high electric field at the end of the field plate, and improving the voltage resistance performance of the device. In addition, the present invention also reduces the requirements for etching accuracy. Therefore, the present invention simultaneously solves the problems of high electric field at the edge of the field plate of the existing Schottky diode with a field plate structure and high requirements for etching accuracy of the groove.

[0091] Furthermore, by introducing a P-type semiconductor layer and a gallium oxide drift layer to construct a heterojunction to form a junction barrier Schottky diode structure, and combining with the trench at the same time, a trench junction barrier Schottky diode (TJBS) is formed. The mutual depletion between the P-type semiconductor and the gallium oxide junction makes the electric field on the surface of the gallium oxide drift layer evenly distributed, and the balanced electric field alleviates the electric field concentration at the corners of the trench, while providing lateral electric field depletion to alleviate the electric field under the anode. In addition, the presence of the P-type semiconductor layer at the corners of the trench further alleviates the electric field concentration at the corners of the trench, further improving the blocking ability of the device.

[0092] Furthermore, the electric field concentration at the edge of the P-type semiconductor layer is borne by the first dielectric layer, wherein the A dielectric layer with a higher dielectric constant is used to modulate the surface electric field of the gallium oxide drift layer to make it uniformly distributed, and the B dielectric layer with a higher critical breakdown electric field is used to avoid breakdown of the first dielectric layer. In the device of the structure provided by the present invention, when forward-conducting, the conductivity modulation effect at the PN junction greatly reduces the specific on-resistance during forward conduction; in the case of a surge, the contact area of ​​the P type is increased, and the ability to resist surges is increased. At the same time, during dynamic avalanche breakdown, a P channel is provided, so that the electron holes generated by the avalanche can be better transmitted, and the device's ability to resist dynamic avalanches is improved. Therefore, the device of the structure provided in an embodiment of the present invention has a lower specific on-resistance (excellent front conduction characteristics), can withstand a higher reverse breakdown voltage, and has excellent performance.

[0093] In the embodiment of the present invention, the thickness of the gallium oxide substrate can be set according to actual needs. In some implementations, the thickness of the gallium oxide substrate is 500-650 μm, for example, 500 μm, 510 μm, 520 μm, 530 μm, 540 μm, 550 μm, 560 μm, 570 μm, 580 μm, 590 μm, 600 μm, 610 μm, 620 μm, 630 μm, 640 μm or 650 μm, etc.

[0094] In some embodiments, the gallium oxide substrate is a highly doped N-type gallium oxide substrate, and the doping concentration (i.e., the effective electron concentration activated after doping, the same below) is 10 18 ~10 20 cm -3 In some specific embodiments, the highly doped N-type gallium oxide substrate is a highly doped N-type β-Ga2O3 substrate doped with at least one of Si, Sn, Ge, V, Nb, Ta, Mo, W, and Sb.

[0095] In the embodiment of the present invention, the thickness of the gallium oxide drift layer and the thickness of the protrusion can be set according to actual needs. In some embodiments, the thickness of the gallium oxide drift layer is 5 to 20 μm, for example, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm, etc., and the height of the protrusion is 0.2 to 4 μm, for example, it can be 0.2 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm or 4 μm, etc.

[0096] In some embodiments, the gallium oxide drift layer is a low-doped N-type gallium oxide drift layer, and the doping concentration (ie, the effective electron concentration activated after doping) is 10 16~5.0×10 17 cm -3 In some specific embodiments, the low-doped N-type gallium oxide substrate is a low-doped N-type β-Ga2O3 drift layer doped with at least one of Si, Sn, Ge, V, Nb, and Ta.

[0097] In an embodiment of the present invention, the thicknesses of the A dielectric layer and the B dielectric layer can be set according to actual needs. In some embodiments, the thickness of the A dielectric layer is 30 to 100 nm (for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, etc.), and the thickness of the B dielectric layer is 30 to 400 nm (for example, 30 nm, 50 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm or 400 nm, etc.).

[0098] In some embodiments, the A dielectric layer includes an A dielectric material, which includes at least one of aluminum oxide (Al2O3) and hafnium oxide (HfO2), but is not limited thereto; the B dielectric layer includes a B dielectric material, which includes at least one of silicon nitride (Si3N4) and silicon dioxide (SiO2), but is not limited thereto.

[0099] In some embodiments, the second dielectric layer includes a C dielectric layer and a D dielectric layer stacked from bottom to top, wherein the thicknesses of the C dielectric layer and the D dielectric layer can be set according to actual needs. In some specific embodiments, the thickness of the C dielectric layer is 30 to 100 nm (for example, it can be 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, etc.), and the thickness of the D dielectric layer is 30 to 400 nm (for example, it can be 30 nm, 50 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm or 400 nm, etc.).

[0100] In some embodiments, the C dielectric layer includes a C dielectric material, which includes one of aluminum oxide and hafnium oxide, but is not limited thereto; the D dielectric layer includes a D dielectric material, which includes one of silicon nitride and silicon dioxide, but is not limited thereto.

[0101] In the embodiment of the present invention, the thickness of the P-type semiconductor layer can be set according to actual needs. In some embodiments, the thickness of the P-type semiconductor layer is 100-400 nm, for example, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm or 400 nm. Fig.19 and Fig. 20 As shown, the P-type semiconductor layer includes 7 parts, namely, a part covering the surface of the metal field plate 10, a part covering the side of the metal field plate 10, a part covering the side of the second dielectric layer 70, a part covering the side of the protrusion 31, a part covering the surface of the shoulder 32, and a part covering the side of the first dielectric layer 40 and a part of the surface of the first dielectric layer 40. The thickness of each of the 7 parts is 100 to 400 nm.

[0102] In some embodiments, the P-type semiconductor layer includes a P-type semiconductor, and the P-type semiconductor includes at least one of P-type nickel oxide, P-type gallium nitride, P-type gallium oxide, and P-type cuprous oxide, but is not limited thereto. The doping concentration of the P-type semiconductor (i.e., the effective hole concentration activated after doping) is 10 17 ~10 19 cm -3 .

[0103] In some embodiments, the materials of the cathode, the anode, and the metal field plate each independently include at least one of Al, Au, Ni, Pt, Cu, Ti, Ag, and TiN, but are not limited thereto.

[0104] In some embodiments, the width of the metal field plate is 1 to 10 μm, where the width refers to the distance from one end of the metal field plate connected to the anode to the other opposite end, for example, it can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc.

[0105] In some embodiments, the third dielectric layer includes silicon dioxide, but is not limited thereto.

[0106] The embodiment of the present invention further provides a method for preparing a gallium oxide junction barrier Schottky diode, which comprises the following steps:

[0107] providing a gallium oxide substrate;

[0108] forming a gallium oxide drift layer on the gallium oxide substrate; the upper surface of the gallium oxide drift layer is a boss structure, and the boss structure includes a protrusion and a shoulder;

[0109] forming a first dielectric layer on the shoulder, wherein the first dielectric layer comprises a dielectric layer A and a dielectric layer B stacked from bottom to top, the relative dielectric constant of the dielectric layer A is greater than or equal to 9, and the breakdown electric field strength of the dielectric layer B is greater than or equal to 8 MV / cm;

[0110] forming an anode on a surface of the protrusion;

[0111] forming a second dielectric layer on the surface of the protrusion and on the side of the anode;

[0112] forming a metal field plate on the second dielectric layer and on a side of the anode;

[0113] Forming a P-type semiconductor layer on the surface of the metal field plate, the side of the metal field plate, the side of the second dielectric layer, the side of the protrusion, the surface of the shoulder, the side of the first dielectric layer, and a partial surface of the first dielectric layer;

[0114] Forming a third dielectric layer on the side of the anode, the surface of the P-type semiconductor layer and the surface of the first dielectric layer;

[0115] A cathode is formed on a surface of the gallium oxide substrate facing away from the gallium oxide drift layer.

[0116] In some embodiments, Figures 1 to 19 As shown, the method for preparing the gallium oxide junction barrier Schottky diode specifically includes the following steps:

[0117] S1, such as Figure 1 As shown, a gallium oxide substrate 2 having a gallium oxide epitaxial layer 3' on its surface is provided;

[0118] S2, such as Figures 2 to 3 As shown, a second dielectric layer precursor layer 70' is formed on the gallium oxide epitaxial layer 3'; a first photoresist film a is formed on both sides of the second dielectric layer precursor layer 70' to obtain a first semi-finished product;

[0119] In some embodiments, the second dielectric layer precursor layer 70' includes a C dielectric layer precursor layer 7' and a D dielectric layer precursor layer 8' which are stacked. Therefore, step S2 specifically includes: sequentially growing a C dielectric material and a D dielectric material on the gallium oxide epitaxial layer 3' to form a C dielectric layer precursor layer 7' and a D dielectric layer precursor layer 8' which are stacked in sequence; forming a first photoresist film a on both sides of the D dielectric layer precursor layer 8' to obtain a first semi-finished product;

[0120] S3, such as Figures 4 to 5 As shown, a first metal layer 10' is formed on the upper surface of the first semi-finished product (the surface includes the surface of the first photoresist film a and the surface of the exposed D dielectric layer precursor layer 8'), and after the first photoresist film a is stripped off, a second semi-finished product is obtained;

[0121] S4, such as Figure 6 As shown, both sides of the first metal layer 10' of the second semi-finished product are etched to a depth reaching the gallium oxide epitaxial layer 3', and a gallium oxide drift layer 3 is formed while forming the first groove 12 (that is, the gallium oxide drift layer 3 is formed by etching both sides of the gallium oxide epitaxial layer 3', and the upper surface of the gallium oxide drift layer is a boss structure, and the boss structure includes a protrusion and a shoulder), and a third semi-finished product is obtained;

[0122] S5, such as Figures 7 to 10 As shown, a dielectric layer A precursor layer 4' and a dielectric layer B precursor layer 5' are sequentially stacked on the upper surface of the third semi-finished product (the surface includes the shoulder surface of the gallium oxide drift layer, the side surface of the protruding portion, the side surface of the C dielectric layer precursor layer 7' and the D dielectric layer precursor layer 8', and the side surface and surface of the first metal layer 10'); a second photoresist film b is formed on the two end regions of the B dielectric layer precursor layer 5' at the bottom of the first groove, and then the dielectric layer A precursor layer 4' and the dielectric layer B precursor layer 5' in the region not covered by the second photoresist film b are etched away, and at the same time, the dielectric layer A 4 and the dielectric layer B 5 are formed (that is, the dielectric layer A 4 and the dielectric layer B 5 are formed by partially etching the dielectric layer A precursor layer 4' and the dielectric layer B precursor layer 5'), and then the second photoresist film b is removed to obtain a fourth semi-finished product;

[0123] S6, such as Fig.11 As shown, a third photoresist film c is formed on the middle region of the first metal layer 10' of the fourth semi-finished product and on both end regions of the B dielectric layer 5 to obtain a fifth semi-finished product;

[0124] The two end regions of the B dielectric layer 5 are also partial regions of the B dielectric layer 5 that are away from the first metal layer 10 ′.

[0125] S7, such as Figure 12 to Figure 13 As shown, a P-type semiconductor layer precursor layer 6' is formed on the upper surface of the fifth semi-finished product (the surface includes the surface of the third photoresist film c, the surface of the B dielectric layer 5, the side surfaces of the A dielectric layer 4 and the B dielectric layer 5, the shoulder surface, the side surface of the protrusion, the C dielectric layer precursor layer 7' and the D dielectric layer precursor layer 8', and the side surface of the first metal layer 10', and the surface of the first metal layer 10'), and then the third photoresist film c is stripped off while forming the P-type semiconductor layer 6 (that is, the P-type semiconductor layer 6 is formed by partially etching the P-type semiconductor layer precursor layer 6'), to obtain a sixth semi-finished product;

[0126] S8, such as Figures 14 to 19As shown, a third dielectric layer precursor layer 11' is formed on the upper surface of the sixth semi-finished product (the surface includes the B dielectric layer 5, the surface of the P-type semiconductor layer 6 and the surface of the first metal layer 10'), and then a fourth photoresist film d is formed at both ends of the third dielectric layer precursor layer 11', and the projection of the fourth photoresist film d on the first metal layer 10' covers part of the first metal layer 10', and then the third dielectric layer precursor layer 11', the first metal layer 10' and the second dielectric layer precursor layer (including the C dielectric layer precursor layer 7' and the D dielectric layer precursor layer 8' which are stacked) in the area not covered by the fourth photoresist film d are formed. The second groove 13, the third dielectric layer 11, the metal field plate 10, the D dielectric layer 8 and the C dielectric layer 7 are formed by partially etching the third dielectric layer precursor layer 11', the first metal layer 10' and the second dielectric layer precursor layer to form the second groove 13, the third dielectric layer 11, the metal field plate 10, the D dielectric layer 8 and the C dielectric layer 7), and then the fourth photoresist film d is removed, an anode 9 is formed in the second groove 13 and on the third dielectric layer 11, and a cathode 1 is formed on the side of the gallium oxide substrate 2 away from the gallium oxide drift layer 3 to obtain a gallium oxide junction barrier Schottky diode.

[0127] In step S2, in some embodiments, the formation method of the A dielectric layer precursor layer and the B dielectric layer precursor layer includes one of chemical deposition or physical deposition, specifically plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering deposition, pulsed laser deposition, electron beam evaporation deposition or atomic layer deposition, etc.

[0128] In step S3, in some embodiments, the method for forming the first metal layer includes one of chemical deposition or physical deposition, specifically plasma enhanced chemical vapor deposition, magnetron sputtering deposition, pulsed laser deposition, electron beam evaporation deposition or atomic layer deposition, etc.

[0129] The first metal layer includes a first metal material, and the first metal material includes at least one of Al, Au, Ni, Pt, Cu and TiN, but is not limited thereto.

[0130] In step S4, the etching includes wet etching, ICP etching (inductively coupled plasma etching) or RIE etching (inverse particle etching) and the like.

[0131] In step S5, the formation methods of the A dielectric layer precursor layer and the B dielectric layer precursor layer are each independently one of chemical deposition or physical deposition, specifically plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering deposition, pulsed laser deposition, electron beam evaporation deposition or atomic layer deposition, etc.

[0132] In step S7, in some embodiments, the method for forming the P-type semiconductor layer precursor layer includes one of chemical deposition or physical deposition, specifically plasma enhanced chemical vapor deposition, magnetron sputtering deposition, pulsed laser deposition, electron beam evaporation deposition or atomic layer deposition, etc.

[0133] In step S8, in some embodiments, the method for forming the third dielectric layer precursor layer includes one of chemical deposition or physical deposition, specifically magnetron sputtering deposition, pulsed laser deposition, electron beam evaporation deposition, or atomic layer deposition, etc. The method for forming the anode includes one of chemical deposition or physical deposition, specifically plasma enhanced chemical vapor deposition, magnetron sputtering deposition, pulsed laser deposition, electron beam evaporation deposition, or atomic layer deposition, etc. The method for forming the cathode includes one of chemical deposition or physical deposition, specifically plasma enhanced chemical vapor deposition, magnetron sputtering deposition, pulsed laser deposition, electron beam evaporation deposition, or atomic layer deposition, etc.

[0134] The present invention will be further described below by means of specific examples.

[0135] Example 1

[0136] This embodiment provides a gallium oxide junction barrier Schottky diode with a trench and field plate composite terminal structure, such as Fig.19 and Fig. 20 As shown, it includes a cathode 1, a gallium oxide substrate 2, and a gallium oxide drift layer 3 which are stacked in sequence from bottom to top; the upper surface of the gallium oxide drift layer 3 is a boss structure, and the boss structure includes a protrusion 31 and a shoulder 32;

[0137] The gallium oxide junction barrier Schottky diode further comprises:

[0138] A first dielectric layer 40, located on the shoulder 32;

[0139] an anode 9, located on the surface of the protrusion 31;

[0140] A second dielectric layer 70 is located on the surface of the protrusion 31 and on the side of the anode 9;

[0141] A metal field plate 10 is located on the second dielectric layer 70, and one end of the metal field plate 10 is connected to a side surface of the anode 9;

[0142] The P-type semiconductor layer 6 continuously covers the surface of the metal field plate 10, the side of the metal field plate 10, the side of the second dielectric layer 70, the side of the protrusion 31, the surface of the shoulder 32, the side of the first dielectric layer 40, and a part of the surface of the first dielectric layer 40;

[0143] The third dielectric layer 11 continuously covers the side surface of the anode 9, the surface of the P-type semiconductor layer 6 and the surface of the first dielectric layer 40;

[0144] The thickness of the gallium oxide drift layer is 10 μm, and the gallium oxide drift layer is a Si-doped low-doped N-type β-Ga2O3 drift layer with a doping concentration of 1.5×10 16 cm -3 The thickness of the protrusion (i.e., the height of the protrusion) is 570 nm; the thickness of the gallium oxide substrate is 500 μm, and the gallium oxide substrate is a Si-doped highly doped N-type β-Ga2O3 substrate with a doping concentration of 5.9×10 18 cm -3 .

[0145] The first dielectric layer 40 includes a dielectric layer A 4 and a dielectric layer B 5 stacked from bottom to top, wherein the dielectric layer A has a thickness of 30 nm, is made of Al2O3, and has a relative dielectric constant of 9.4; the dielectric layer B has a thickness of 200 nm, is made of Si3N4, and has a breakdown electric field strength of 11 MV / cm;

[0146] The second dielectric layer 70 includes a C dielectric layer 7 and a D dielectric layer 8 stacked from bottom to top, wherein the C dielectric layer has a thickness of 30 nm and is made of Al2O3; the D dielectric layer has a thickness of 200 nm and is made of Si3N4;

[0147] The thickness of the P-type semiconductor layer is 200 nm (the maximum thickness of each part is 200 nm), the material is P-type NiO, and the doping concentration is 1.5×10 18 cm -3 ;

[0148] The thickness of the third dielectric layer is 300nm (including three parts, namely, a part covering the side of the anode part, a part covering the surface of the P-type semiconductor layer, and a part covering the surface of the first dielectric layer part, and the maximum thickness of each part is 300nm), and the material is SiO2;

[0149] The thickness of the anode is 200nm, and the material is a stacked Ni layer (thickness is 100nm) and an Al layer (thickness is 100nm);

[0150] The metal field plate has a thickness of 200 nm and a width of 5 μm, and is made of stacked Ni (100 nm thick) and Al (100 nm thick).

[0151] The thickness of cathode 1 is 200 nm, and the material of cathode is a stacked Ti layer (thickness is 100 nm), a Ni layer (thickness is 50 nm) and an Ag layer (thickness is 50 nm);

[0152] This embodiment provides a method for preparing a gallium oxide junction barrier Schottky diode with a trench and field plate composite terminal structure, wherein: Figures 1 to 19 As shown, the method for preparing the gallium oxide junction barrier Schottky diode specifically includes the following steps:

[0153] (1) Figure 1 As shown, a gallium oxide substrate 2 having a gallium oxide epitaxial layer 3' on its surface is provided;

[0154] The thickness of the gallium oxide epitaxial layer is 10 μm, and the gallium oxide epitaxial layer is specifically a Si-doped low-doped N-type β-Ga2O3 drift layer with a doping concentration of 1.5×10 16 cm -3 The thickness of the gallium oxide substrate is 500 μm. The gallium oxide substrate is specifically a Si-doped highly doped N-type β-Ga2O3 substrate with a doping concentration of 5.9×10 18 cm -3 .

[0155] (2) Figure 2 As shown, a C dielectric layer precursor layer 7' and a D dielectric layer precursor layer 8' are stacked and formed in sequence on the gallium oxide epitaxial layer 3' by a PECVD method;

[0156] The thickness of the C dielectric layer precursor layer is 30 nm, and the material is Al2O3; the thickness of the D dielectric layer precursor layer is 200 nm, and the material is Si3N4.

[0157] (3) Figure 3 As shown, photoresist is coated on the surface of the D dielectric layer precursor layer 8', and a standard photolithography process is used for etching to expose the D dielectric layer precursor layer 8' in the middle, and a first photoresist film a is formed on both sides of the D dielectric layer precursor layer 8' to obtain a first semi-finished product;

[0158] (4) Figure 4 As shown, the first metal layer 10' is formed on the upper surface of the first semi-finished product (the surface includes the surface of the first photoresist film a and the surface of the exposed D dielectric layer precursor layer 8') by electron beam evaporation;

[0159] The thickness of the first metal layer is 200 nm (after the following processing, the remaining part of the first metal layer is used as a metal field plate), and the first metal layer is a stacked Ni layer (100 nm thick) and an Al layer (100 nm thick).

[0160] (5) Figure 5 As shown, the first photoresist film a is peeled off to obtain a second semi-finished product;

[0161] (6) Figure 6As shown, ICP etching is performed on both sides of the first metal layer 10' of the second semi-finished product, and the etching depth reaches the gallium oxide epitaxial layer 3', forming the first groove 12 and also forming the gallium oxide drift layer 3, thereby obtaining a third semi-finished product;

[0162] Wherein, the depth of the second groove is 1 μm;

[0163] (7) Figure 7 As shown, a dielectric layer precursor layer A 4' and a dielectric layer precursor layer B 5' are sequentially stacked on the upper surface of the third semi-finished product (the surface includes the shoulder surface of the gallium oxide drift layer 3, the side surface of the protruding portion, the side surfaces of the C dielectric layer precursor layer 7' and the D dielectric layer precursor layer 8', and the side surface and surface of the first metal layer 10') by using a PECVD method;

[0164] The thickness of the precursor layer of the A dielectric layer is 30 nm, and the material is Al2O3; the thickness of the precursor layer of the B dielectric layer is 200 nm, and the material is Si3N4.

[0165] (8) Figure 8 As shown, photoresist is coated on the upper surface of the semi-finished product obtained in step (7), and photolithography is performed using a standard photolithography process to form a second photoresist film b on both end regions of the B dielectric layer precursor layer 5' at the bottom of the first groove.

[0166] (9) Fig. 9 As shown, the A dielectric layer precursor layer 4' and the B dielectric layer precursor layer 5' outside the area covered by the second photoresist film b are etched away by BOE solution (buffered oxide etching solution, wherein 49% HF aqueous solution: 40% NH4F aqueous solution = 1:6), and at the same time, the A dielectric layer 4 and the B dielectric layer 5 are formed.

[0167] (10) Fig.10 As shown, the second photoresist film b is then removed to obtain a fourth semi-finished product;

[0168] (11) Fig.11 As shown, a photoresist is coated on the upper surface of the fourth semi-finished product, and a standard photolithography process is used for etching to form a third photoresist film c (i.e., a growth pattern of a P-type semiconductor layer is formed) in the middle area of ​​the first metal layer 10' of the fourth semi-finished product and on both end areas of the B dielectric layer 5, thereby obtaining a fifth semi-finished product;

[0169] (12) Fig.12As shown, a P-type semiconductor layer precursor layer 6' is formed on the upper surface of the fifth semi-finished product (the surface includes the surface of the third photoresist film c, the surface of the B dielectric layer 5, the side surfaces of the A dielectric layer 4 and the B dielectric layer 5, the shoulder surface, the side surface of the protrusion, the C dielectric layer precursor layer 7' and the D dielectric layer precursor layer 8', and the side surface and surface of the first metal layer 10') by magnetron sputtering;

[0170] The thickness of the P-type semiconductor layer precursor layer is 200 nm, the material is P-type NiO, and the doping concentration is 1.5×10 18 cm -3 .

[0171] (13) Fig.13 As shown, the third photoresist film c is stripped off and a P-type semiconductor layer 6 is formed at the same time, thereby obtaining a sixth semi-finished product;

[0172] (14) Fig.14 As shown, a third dielectric layer precursor layer 11' is formed on the upper surface of the sixth semi-finished product (the surface includes the surface of the B dielectric layer 5, the surface of the P-type semiconductor layer 6 and the surface of the first metal layer 10') by a PECVD method;

[0173] The thickness of the third medium precursor layer is 300 nm, and the material is SiO2.

[0174] (15) Fig.15 As shown, photoresist is coated on the upper surface of the third dielectric layer precursor layer 11', and etching is performed using a standard photolithography process to expose the middle area of ​​the third dielectric layer precursor layer 11', and a fourth photoresist film d (forming an anode pattern) is formed at both ends of the third dielectric layer precursor layer 11', and the projection of the fourth photoresist film d on the first metal layer 10' covers part of the first metal layer 10'.

[0175] (16) Fig.16 As shown, by wet etching, the third dielectric layer precursor layer 11', the first metal layer 10', the C dielectric layer precursor layer 7' and the D dielectric layer precursor layer 8' in the uncovered area projected by the fourth photoresist film d on the horizontal plane are etched away to form a second groove 13, the third dielectric layer 11, the metal field plate 10 (with a width of 5 μm), the D dielectric layer 8 and the C dielectric layer 7.

[0176] (17) Fig.17 As shown, the fourth photoresist film d is then removed.

[0177] (18) Fig.18 As shown, an anode 9 is formed in the second groove 13 and on the third dielectric layer 11 by electron beam evaporation;

[0178] The thickness of the anode is 200 nm, and the material is a stacked Ni layer (100 nm thick) and an Al layer (100 nm thick), and the Ni layer is attached to the gallium oxide drift layer.

[0179] (19) Fig.19 As shown, an electron beam evaporation method is used to form a cathode 1 on the side of the gallium oxide substrate 2 away from the gallium oxide drift layer 3 to obtain the gallium oxide junction barrier Schottky diode;

[0180] The thickness of the cathode is 200 nm, and the material of the cathode is a stacked Ti layer (100 nm thick), a Ni layer (50 nm thick) and an Ag layer (50 nm thick), and the Ti layer is attached to the gallium oxide substrate.

[0181] Comparative Example 1

[0182] This comparative example 1 provides a vertical gallium oxide Schottky diode of conventional structure, which is different from the gallium oxide junction barrier Schottky diode with a groove and field plate composite terminal in Example 1 only in that: Comparative example 1 is a vertical Schottky diode of conventional structure that does not utilize the composite junction termination technology (it does not contain a groove and field plate composite terminal, does not contain a heterojunction constructed using a P-type semiconductor and a gallium oxide drift layer, and does not contain the first dielectric layer and the second dielectric layer of the shoulder of the boss structure).

[0183] Comparative Example 2

[0184] This comparative example 2 provides a gallium oxide Schottky diode with a groove and field plate composite terminal structure, which is different from the gallium oxide junction barrier Schottky diode with a groove and field plate composite terminal structure in Example 1 only in that comparative example 2 does not use a P-type semiconductor and a gallium oxide drift layer to construct a heterojunction and the first dielectric layer and the second dielectric layer of the shoulder of the boss structure.

[0185] The reverse characteristic curves of the Schottky diodes in Example 1, Comparative Example 1 and Comparative Example 2 are as follows: Fig.21As shown, the withstand voltage performance of the gallium oxide junction barrier Schottky diode with a composite terminal structure of the groove and field plate in Example 1, the gallium oxide Schottky diode with a composite terminal of the groove and field plate in Comparative Example 2, and the vertical gallium oxide Schottky diode with a conventional structure in Comparative Example 1 can be compared. The withstand voltage of the gallium oxide Schottky diode with a composite terminal of the groove and field plate (Comparative Example 2) is 2468V, and the withstand voltage of the vertical gallium oxide Schottky diode with a conventional structure (Comparative Example 1) is only 1269V. The withstand voltage of the gallium oxide junction barrier Schottky diode with a composite terminal structure of the groove and field plate (Example 1) using P-type NiO is 3182V. Compared with the gallium oxide Schottky diode with a composite terminal structure of the groove and field plate, the breakdown voltage is increased by 29%, and compared with the vertical gallium oxide diode with a conventional structure, the breakdown voltage is increased by 151%. At the same time, due to the addition of P-type NiO, the leakage current of the device is smaller.

[0186] The surface electric field distribution curves of the Schottky diodes in Example 1, Comparative Example 1 and Comparative Example 2 are as follows: Fig. 22 As shown, the surface electric field distribution of the drift region when the gallium oxide junction barrier Schottky diode of the groove and field plate composite terminal structure with the composite dielectric layer structure of the A dielectric layer and the B dielectric layer introduced in Example 1, the gallium oxide Schottky diode of the groove and field plate composite terminal structure in Comparative Example 2 and the gallium oxide Schottky diode of the conventional structure in Comparative Example 1 are broken down can be compared. It can be seen that the vertical gallium oxide Schottky diode of the conventional structure (Comparative Example 1) is mainly borne by the anode Schottky junction; the surface of the gallium oxide Schottky diode of the groove and field plate composite terminal structure (Comparative Example 2) is mainly borne by the anode Schottky junction and the trench etching corner; and the gallium oxide junction barrier Schottky diode (Example 1) using the groove and field plate composite terminal of P-type NiO, the mutual depletion between the NiO / Ga2O3 junctions on the sidewall of the groove provides lateral electric field depletion, so that the surface electric field is evenly distributed, and at the same time, the electric field peak at the anode edge and the etching corner is alleviated.

[0187] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A gallium oxide junction barrier Schottky diode, characterized in that: The gallium oxide junction barrier Schottky diode comprises a cathode, a gallium oxide substrate, and a gallium oxide drift layer which are stacked in sequence from bottom to top; the upper surface of the gallium oxide drift layer is a boss structure, and the boss structure comprises a protrusion and a shoulder; The gallium oxide junction barrier Schottky diode further comprises: A first dielectric layer, located on the shoulder; an anode located on the surface of the protrusion; A second dielectric layer is located on the surface of the protrusion and on the side of the anode; A metal field plate, located on the second dielectric layer, and one end of the metal field plate is connected to a side surface of the anode; A P-type semiconductor layer continuously covers the surface of the metal field plate, the side of the metal field plate, the side of the second dielectric layer, the side of the protrusion, the shoulder surface, the side of the first dielectric layer, and a partial surface of the first dielectric layer; A third dielectric layer continuously covers the side surface of the anode portion, the surface of the P-type semiconductor layer and the surface of the first dielectric layer; The first dielectric layer includes a dielectric layer A and a dielectric layer B stacked from bottom to top, the relative dielectric constant of the dielectric layer A is greater than or equal to 9, and the breakdown electric field strength of the dielectric layer B is greater than or equal to 8 MV / cm.

2. The gallium oxide junction barrier Schottky diode according to claim 1, characterized in that: The thickness of the gallium oxide substrate is 500-650 μm; The gallium oxide substrate is a highly doped N-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 .

3. The gallium oxide junction barrier Schottky diode according to claim 1, characterized in that: The thickness of the gallium oxide drift layer is 5 μm to 20 μm, and the height of the protrusion is 0.2 to 4 μm; The gallium oxide drift layer is a low-doped N-type gallium oxide drift layer with a doping concentration of 10 16 ~5.0×10 17 cm -3 .

4. The gallium oxide junction barrier Schottky diode according to claim 1, characterized in that: The thickness of the A dielectric layer is 30-100 nm, and the thickness of the B dielectric layer is 30-400 nm; The A dielectric layer includes an A dielectric material, and the A dielectric material includes at least one of aluminum oxide and hafnium oxide; the B dielectric layer includes a B dielectric material, and the B dielectric material includes at least one of silicon nitride and silicon dioxide.

5. The gallium oxide junction barrier Schottky diode according to claim 1, characterized in that: The second dielectric layer comprises a C dielectric layer and a D dielectric layer stacked from bottom to top, the C dielectric layer has a thickness of 30 to 100 nm, and the D dielectric layer has a thickness of 30 to 400 nm; The C dielectric layer includes a C dielectric material, wherein the C dielectric material includes one of aluminum oxide and hafnium oxide. The D dielectric layer includes a D dielectric material, wherein the D dielectric material includes one of silicon nitride and silicon dioxide.

6. The gallium oxide junction barrier Schottky diode according to claim 1, characterized in that: The thickness of the P-type semiconductor layer is 100-400 nm; The P-type semiconductor layer includes a P-type semiconductor, and the doping concentration of the P-type semiconductor is 10 17 ~10 19 cm -3 ; The P-type semiconductor includes at least one of P-type nickel oxide, P-type gallium nitride, P-type gallium oxide and P-type cuprous oxide.

7. The gallium oxide junction barrier Schottky diode according to claim 1, characterized in that: The materials of the cathode, anode and metal field plate each independently include at least one of Al, Au, Ni, Pt, Cu, Ti, Ag and TiN; The width of the metal field plate is 1-10 μm, and the width refers to the distance from one end of the metal field plate connected to the anode to the other end opposite thereto.

8. A method for preparing the gallium oxide junction barrier Schottky diode according to claim 1, characterized in that: The steps include: providing a gallium oxide substrate; forming a gallium oxide drift layer on the gallium oxide substrate; the upper surface of the gallium oxide drift layer is a boss structure, and the boss structure includes a protrusion and a shoulder; forming a first dielectric layer on the shoulder, wherein the first dielectric layer comprises a dielectric layer A and a dielectric layer B stacked from bottom to top, the relative dielectric constant of the dielectric layer A is greater than or equal to 9, and the breakdown electric field strength of the dielectric layer B is greater than or equal to 8 MV / cm; forming an anode on a surface of the protrusion; forming a second dielectric layer on the surface of the protrusion and on the side of the anode; forming a metal field plate on the second dielectric layer and on a side of the anode; Forming a P-type semiconductor layer on the surface of the metal field plate, the side of the metal field plate, the side of the second dielectric layer, the side of the protrusion, the surface of the shoulder, the side of the first dielectric layer, and a partial surface of the first dielectric layer; Forming a third dielectric layer on the side of the anode, the surface of the P-type semiconductor layer and the surface of the first dielectric layer; A cathode is formed on a surface of the gallium oxide substrate facing away from the gallium oxide drift layer.

9. The method for preparing a gallium oxide junction barrier Schottky diode according to claim 8, characterized in that: The method for preparing the gallium oxide junction barrier Schottky diode specifically comprises the following steps: Providing a gallium oxide substrate having a gallium oxide epitaxial layer on the surface; forming a second dielectric layer precursor layer on the gallium oxide epitaxial layer; forming a first photoresist film on both sides of the second dielectric layer precursor layer to obtain a first semi-finished product; Forming a first metal layer on the upper surface of the first semi-finished product, and stripping off the first photoresist film to obtain a second semi-finished product; Etching both sides of the first metal layer of the second semi-finished product to a depth reaching the gallium oxide epitaxial layer, thereby forming a first groove and a gallium oxide drift layer, thereby obtaining a third semi-finished product; Forming a dielectric layer A precursor layer and a dielectric layer B precursor layer stacked in sequence on the upper surface of the third semi-finished product, forming a second photoresist film on both end regions of the dielectric layer B precursor layer at the bottom of the first groove, then etching away the dielectric layer A precursor layer and the dielectric layer B precursor layer in regions not covered by the second photoresist film to form the dielectric layer A and the dielectric layer B, and then removing the second photoresist film to obtain a fourth semi-finished product; forming a third photoresist film on the middle region of the first metal layer of the fourth semi-finished product and on both end regions of the B dielectric layer to obtain a fifth semi-finished product; forming a P-type semiconductor layer precursor layer on the upper surface of the fifth semi-finished product, and then stripping off the third photoresist film while forming a P-type semiconductor layer to obtain a sixth semi-finished product; A third dielectric layer precursor layer is formed on the upper surface of the sixth semi-finished product, and then a fourth photoresist film is formed at both ends of the third dielectric layer precursor layer, and the projection of the fourth photoresist film on the first metal layer covers a portion of the first metal layer, and then the third dielectric layer precursor layer, the first metal layer and the second dielectric layer precursor layer in the area not covered by the fourth photoresist film are etched away to form a second groove, a second dielectric layer, a third dielectric layer and a metal field plate; Then, the fourth photoresist film is removed, an anode is formed in the second groove and on the third dielectric layer, and a cathode is formed on the side of the gallium oxide substrate away from the gallium oxide drift layer to obtain a gallium oxide junction barrier Schottky diode.

10. The preparation method according to claim 9, characterized in that: The A dielectric layer precursor layer, the B dielectric layer precursor layer and the third dielectric layer precursor layer are each independently formed by chemical deposition or physical deposition.

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