Anisotropic dielectric layer transistor and preparation method thereof

Abstract

The invention belongs to the related technical field of semiconductor devices, and discloses an anisotropic dielectric layer transistor and a preparation method thereof. The transistor comprises a substrate, a grid electrode, a source electrode, a drain electrode, a conducting channel and a dielectric layer, the substrate serves as a carrier of the conducting channel, the dielectric layer is stacked above the conducting channel and coincides with the armchair crystal orientation of the conducting channel, the source electrode and the drain electrode are arranged on the two sides of the conducting channel, and the source electrode and the drain electrode are arranged on the substrate. The grid electrode is arranged on the dielectric layer, and the dielectric layer is of a low-symmetry crystal structure and is anisotropic in a horizontal plane. The invention further discloses a preparation method of the transistor. According to the invention, the leakage current is reduced, the electrical performance of the conducting channel is improved, the channel material is induced to generate obvious anisotropic electrical response, and the transistor shows better electrical performance.

Description

Technical Field

[0001] The present invention belongs to the technical field related to semiconductor devices, and more specifically, relates to an anisotropic dielectric layer transistor and a preparation method thereof. Background Art

[0002] As the size of silicon-based field-effect transistors continues to shrink along with Moore's Law, their electrical performance has declined due to the short channel effect, making it difficult to meet the growing demand for chips. Two-dimensional semiconductor materials have become ideal channel materials for the next generation of integrated circuit chips due to their advantages such as atomic-level thickness, high carrier mobility and suppression of short channel effects. However, after the two-dimensional semiconductor channel material is integrated with traditional dielectric materials (SiO2), the dangling bonds and disordered states on the surface of the dielectric material will affect the electrical properties of the two-dimensional semiconductor channel material, making it difficult to exhibit its intrinsic excellent performance.

[0003] Compared with traditional oxide dielectric materials, the surface of van der Waals dielectric materials is atomically flat and has no dangling bonds. They are considered to be ideal dielectric layers that are compatible with two-dimensional semiconductor channel materials. After screening and exploration, a series of van der Waals dielectric layers have been developed one after another, such as hexagonal boron nitride (h-BN), calcium fluoride (CaF2), strontium titanate (SrTiO3), antimony oxide (Sb2O3), etc. As the research deepened, it was found that these van der Waals dielectric layers all belong to highly symmetric crystal structures, and their intrinsic isotropy makes it difficult to further achieve the anisotropy regulation of the two-dimensional semiconductor channel. Therefore, the development of van der Waals dielectric layers with low crystal symmetry not only provides new degrees of freedom for the performance regulation of two-dimensional semiconductor electronic devices, but also helps to further promote the design and development of new multifunctional electronic devices. Summary of the invention

[0004] In view of the above defects or improvement needs of the prior art, the present invention provides an anisotropic dielectric layer transistor and a preparation method to solve the problem that the anisotropy of the conductive channel in a two-dimensional semiconductor electronic device is difficult to control.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present invention, there is provided an anisotropic dielectric layer transistor, which includes a substrate, a gate, a source electrode, a drain electrode, a conductive channel and a dielectric layer, wherein the substrate serves as a carrier of the conductive channel, the dielectric layer is stacked above the conductive channel, the armchair crystal orientations of the dielectric layer and the conductive channel coincide, the source electrode and the drain electrode are arranged on both sides of the conductive channel, and the gate is arranged on the dielectric layer, wherein the dielectric layer has a low-symmetry crystal structure and is anisotropic in a horizontal plane.

[0006] Further preferably, the dielectric layer is made of a material having a C2 rotational symmetry crystal structure.

[0007] Further preferably, the material of the dielectric layer is one of gallium indium sulfide, molybdenum oxide, vanadium oxide chloride, bismuth selenium oxide and chromium sulfide bromide.

[0008] Further preferably, the thickness of the dielectric layer is 10 nm to 100 nm.

[0009] Further preferably, the dielectric constant of the dielectric layer is greater than 10.

[0010] Further preferably, the conductive channel is made of a material having C3 rotational symmetry, and has a thickness of 1 nm to 20 nm.

[0011] Further preferably, the material with C3 rotational symmetry is molybdenum sulfide, molybdenum selenide, molybdenum telluride, tungsten sulfide, tungsten selenide or graphene.

[0012] Further preferably, the gate, source electrode and drain electrode each include two layers, one layer is a metal electrode that can achieve ohmic contact with the conductive channel, and the other layer is a protective layer to prevent oxidation of the metal electrode, the thickness of the metal electrode is 5nm to 10nm, and the thickness of the protective layer is 50nm to 100nm respectively.

[0013] Further preferably, the substrate is an insulating rigid or flexible substrate.

[0014] According to another aspect of the present invention, there is provided a method for preparing the anisotropic dielectric layer transistor as described above, the method comprising the following steps:

[0015] preparing a conductive channel and a dielectric layer respectively;

[0016] respectively detecting the crystal directions of the conductive channel and the dielectric layer, and then stacking the dielectric layer and the conductive channel along the armchair crystal direction and then placing them on the substrate;

[0017] A source electrode and a drain electrode are respectively arranged on both sides of the conductive channel, and a gate is arranged on the dielectric layer, so as to obtain the desired transistor.

[0018] In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:

[0019] 1. The present invention adopts a dielectric layer with a low-symmetry crystal structure, which is anisotropic in the horizontal plane, so that the anisotropy of the conductive channel can be regulated. This is because after the anisotropic dielectric layer and the conductive channel are stacked and contacted along the armchair crystal direction, the isotropy of the conductive channel is destroyed under the action of symmetry coupling, generating anisotropy, thereby regulating the anisotropy of the conductive channel;

[0020] 2. The dielectric layer of the present invention uses a material having a C2 rotationally symmetric crystal structure because the C2 rotationally symmetric material can be symmetrically coupled with the C3 rotationally symmetric conductive channel, thereby generating a C1 symmetry with a lower symmetry, i.e., anisotropy;

[0021] 3. The thickness of the dielectric layer used in the present invention is 10nm to 100nm. If it is too thin, it is easy to leak electricity. If it is too thick, the capacitance is small, which affects the control performance of the dielectric layer. The thickness of the conductive channel is 1nm to 20nm. If the dielectric layer is too thick, it is difficult to achieve the control of the anisotropy of the conductive channel.

[0022] 4. The anisotropic dielectric layer transistor provided by the present invention, under the regulation of the dielectric layer, not only reduces the leakage current and improves the electrical performance of the conductive channel, but also its own low symmetry lattice can induce the channel material to produce a significant anisotropic electrical response, and the transistor exhibits good electrical performance, including low leakage current (<10 -12 A) High on / off ratio (>10 6 ), small subthreshold swing (71.6mV dec -1 ) and high anisotropic conductivity ratio (>10 6 ). BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic structural diagram of an anisotropic dielectric layer transistor constructed according to a preferred embodiment of the present invention;

[0024] Figure 2 It is a capacitance measurement and dielectric constant extraction curve of a capacitor with a dielectric layer of GaInS3 constructed according to a preferred embodiment of the present invention;

[0025] Figure 3 The anisotropic characterization of the dielectric layer of GaInS3 according to the preferred embodiment of the present invention, wherein (a) is the polarized optical absorption spectrum of GaInS3 at different wavelengths, and (b) is the polar coordinate diagram of the extracted optical absorbance at a wavelength of 370 nm;

[0026] Figure 4 is an anisotropic optical characterization of a MoS2 / GaInS3 heterojunction constructed according to the preferred embodiment 1 of the present invention, wherein (a) is an optical photograph of a MoS2 / GaInS3 heterojunction, wherein number 1 represents a region with only MoS2, and number 2 represents a region of the MoS2 / GaInS3 heterojunction; (b) is photoluminescence (PL) polar coordinate data of a region with only MoS2; (c) is regional PL polar coordinate data of a MoS2 / GaInS3 heterojunction;

[0027] Figure 5The electrical performance characterization of a transistor constructed according to the preferred embodiment 1 of the present invention with MoS2 as the conductive channel and GaInS3 as the dielectric layer. Among them, (a) is the transfer characteristic output curve, and (b) is the extracted subthreshold swing curve;

[0028] Figure 6 1 is a conductivity curve extracted in different directions of the transistor constructed according to the preferred embodiment 1 of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] like Figure 1 As shown, a field effect transistor based on anisotropic dielectric layer includes an insulating substrate, a conductive channel material, a dielectric layer, a gate and source and drain electrodes.

[0031] In one embodiment of the present invention, the dielectric layer is planar anisotropic, that is, a low-symmetry crystal structure, and has in-plane anisotropic physical properties. Among the seven crystal systems, four crystal systems (cubic, tetragonal and hexagonal systems) are isotropic in the plane, and three crystal systems (orthorhombic, monoclinic and triclinic systems) are low-symmetric and exhibit in-plane anisotropy.

[0032] In one embodiment of the present invention, the thickness of the conductive channel material is 1nm to 20nm. If the conductive channel is too thick, it is difficult to induce anisotropy. The thickness of the dielectric layer of the anisotropic structure is 10nm to 100nm. The dielectric layer of the anisotropic structure can maintain high capacitance at this thickness, thereby improving the gate control performance.

[0033] In one embodiment of the present invention, the dielectric layer is gallium indium sulfide GaInS3 with C2 rotational symmetry, which is an orthorhombic system with a space group of Cmc21. The ratio of elements in GaInS3 is adjustable within the range of Ga 1-x In 1+x S3 (x = 0-0.4).

[0034] In one embodiment of the present invention, the dielectric layer is molybdenum oxide MoO3 with C2 rotational symmetry, which is an orthorhombic system and has a space group of Pnma.

[0035] In one embodiment of the present invention, the dielectric layer is vanadium oxychloride VOCl with C2 rotational symmetry, which is an orthorhombic system and has a space group of Pmmn.

[0036] In one embodiment of the present invention, the dielectric layer is bismuth selenium oxide Bi2SeO5 with C2 rotational symmetry, which is an orthorhombic crystal system and has a space group of Abm2.

[0037] In one embodiment of the present invention, the dielectric layer is chromium sulfide bromide CrSBr with C2 rotational symmetry, which is an orthorhombic system and has a space group of Pmmn.

[0038] Theoretically, any dielectric layer with C2 symmetry can regulate the anisotropy of the channel.

[0039] In one embodiment of the present invention, the dielectric constant of the dielectric layer is greater than 10, and a high dielectric constant has good gate control capability.

[0040] In one embodiment of the present invention, the conductive channel material is MoS2, MoSe2, MoTe2, WS2, WSe2, graphene, etc. The above channel materials are all two-dimensional materials with isotropy. The thickness of the conductive channel is 1nm to 20nm. If the thickness of the channel is too high, it is difficult to induce anisotropy.

[0041] In one embodiment of the present invention, the substrate is a Si / SiO2 insulating substrate.

[0042] In one embodiment of the present invention, the source electrode, the drain electrode and the gate electrode are selected from metal electrodes that are in ohmic contact with the channel material, including two layers, one layer is a metal electrode that can achieve ohmic contact with the conductive channel, and the other layer is a protective layer to prevent the metal electrode from being oxidized. The thickness of the metal electrode is 5nm to 10nm, and the thickness of the protective layer is 50nm to 100nm. For example, Bi / Au, In / Au, Sb / Au, Ti / Au, etc., wherein Au is used as a protective layer. The preparation method of the above-mentioned anisotropic dielectric layer transistor is as follows:

[0043] (1) Preparation of dielectric layer and conductive channel materials; the methods for preparing the dielectric layer and the conductive channel are all existing methods, for example, the dielectric layer is prepared by mechanical stripping or chemical vapor deposition.

[0044] (2) respectively detecting the crystal directions of the conductive channel and the dielectric layer, and then stacking the dielectric layer and the conductive channel on the substrate along the armchair crystal direction;

[0045] (3) The source and drain metal electrodes are prepared on the conductive channel material respectively, and the gate is prepared on the dielectric layer, so as to obtain the field effect transistor.

[0046] The present invention will be further described below with reference to specific embodiments.

[0047] Example 1

[0048] MoS2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~1nm, and the dielectric layer material was GaInS3 with C2 rotational symmetry with a thickness of ~40nm and a dielectric constant of ~12;

[0049] Measure the crystal orientation of the dielectric layer and the conductive channel, transfer the conductive channel to the insulating substrate of the Si wafer with 300nm SiO2 using PDMS, and then transfer the dielectric layer to the conductive channel to ensure that the dielectric layer and the conductive channel are stacked along the armchair crystal orientation;

[0050] The source electrode and drain electrode are deposited on both sides of the conductive channel by a coating apparatus, and the gate is deposited on the dielectric layer. The material of the source electrode and the drain electrode is Ti / Au with a thickness of 10nm / 50nm, and the material of the gate is Ti / Au with a thickness of 10nm / 50nm. The deposition rate is

[0051] Example 2

[0052] MoSe2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~1nm, and the dielectric layer material was MoO3 with C2 rotational symmetry with a thickness of ~30nm and a dielectric constant of ~30;

[0053] Measuring the crystal directions of the dielectric layer and the conductive channel, transferring the conductive channel to the above substrate using PDMS, and then transferring the dielectric layer to the conductive channel to ensure that the dielectric layer and the conductive channel are stacked along the armchair crystal direction;

[0054] The source electrode and drain electrode are deposited on both sides of the conductive channel by a coating apparatus, and the gate is deposited on the dielectric layer. The material of the source electrode and the drain electrode is Bi / Au with a thickness of 5 / 50nm, and the material of the gate is Bi / Au with a thickness of 5 / 50nm. The deposition rate is

[0055] Example 3

[0056] MoTe2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~3nm, and the dielectric layer material was VOCl with C2 rotational symmetry with a thickness of ~35nm and a dielectric constant of ~11;

[0057] Using the method in Example 1-2, transferring the channel material and the dielectric layer onto the substrate;

[0058] Using the method in Example 1-2, the gate, source electrode and drain electrode are deposited on the dielectric layer. The material is In / Au with a thickness of 10nm / 50nm. The material of the gate is In / Au with a thickness of 10nm / 50nm. The deposition rate is

[0059] Example 4

[0060] WS2 was prepared as the conductive channel by mechanical stripping, with a thickness of ~1nm, and the dielectric layer material was GaInS3 with C2 rotational symmetry, with a thickness of ~55nm and a dielectric constant of ~12;

[0061] Using the method in Example 1-2, transferring the channel material and the dielectric layer onto the substrate;

[0062] Using the method in Example 1-2, the gate electrode, the source electrode and the drain electrode are made of Bi / Au with a thickness of 10nm / 50nm, and the gate electrode is made of Bi / Au with a thickness of 10nm / 50nm. The deposition rate is

[0063] Example 5

[0064] WSe2 was prepared as the conductive channel by mechanical stripping method with a thickness of ~5nm, and the dielectric layer material was Bi2SeO5 with C2 rotational symmetry with a thickness of ~10nm and a dielectric constant of ~12;

[0065] Using the method in Example 1-2, transferring the channel material and the dielectric layer onto the substrate;

[0066] Using the method in Example 1-2, the gate, source electrode and drain electrode are deposited on the dielectric layer. The material is In / Au with a thickness of 5nm / 50nm. The material of the gate is In / Au with a thickness of 5nm / 50nm. The deposition rate is

[0067] Example 6

[0068] Graphene was prepared as a conductive channel by mechanical exfoliation with a thickness of ~1 nm, and the dielectric layer material was CrSBr with C2 rotational symmetry with a thickness of ~45 nm and a dielectric constant of ~18;

[0069] Using the method in Example 1-2, transferring the channel material and the dielectric layer onto the substrate;

[0070] Using the method in Example 1-2, the gate, source electrode and drain electrode are deposited on the dielectric layer. The material is In / Au with a thickness of 5nm / 50nm. The material of the gate is In / Au with a thickness of 5nm / 50nm. The deposition rate is

[0071] Example 7

[0072] WSe2 was prepared as the conductive channel by mechanical stripping, with a thickness of ~5nm, and the dielectric layer material was GaInS3 with C2 rotational symmetry, with a thickness of ~100nm and a dielectric constant of ~12;

[0073] Using the method in Example 1-2, transferring the channel material and the dielectric layer onto the substrate;

[0074] Using the method in Example 1-2, the gate electrode, the source electrode and the drain electrode are deposited on the dielectric layer. The material of the gate electrode is Ti / Au, and the thickness is 5nm / 50nm. The material of the gate electrode is Ti / Au, and the thickness is 5nm / 50nm. The deposition rate is

[0075] Example 8

[0076] MoTe2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~10nm, and the dielectric layer material was GaInS3 with C2 rotational symmetry with a thickness of ~65nm and a dielectric constant of ~12;

[0077] Using the method in Example 1-2, transferring the channel material and the dielectric layer onto the substrate;

[0078] Using the method in Example 1-2, the gate electrode, the source electrode and the drain electrode are made of Bi / Au with a thickness of 5nm / 50nm, and the gate electrode is made of Bi / Au with a thickness of 5nm / 50nm. The deposition rate is

[0079] Example 9

[0080] WSe2 was prepared as the conductive channel by mechanical stripping, with a thickness of ~15nm, and the dielectric layer material was GaInS3 with C2 rotational symmetry, with a thickness of ~70nm and a dielectric constant of ~12;

[0081] Using the method in Example 1-2, transferring the channel material and the dielectric layer onto the substrate;

[0082] Using the method in Example 1-2, the gate, source electrode and drain electrode are deposited on the dielectric layer. The material is Bi / Au with a thickness of 8nm / 100nm. The material of the gate is Bi / Au with a thickness of 9nm / 100nm. The deposition rate is

[0083] Example 10

[0084] MoS2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~20nm, and the dielectric layer material was CrSBr with C2 rotational symmetry with a thickness of ~50nm and a dielectric constant of ~19;

[0085] Using the method in Example 1-2, transferring the channel material and the dielectric layer onto the substrate;

[0086] Using the method in Example 1-2, the gate, source electrode and drain electrode are deposited on the dielectric layer. The material of the gate is Ti / Au with a thickness of 10nm / 100nm. The material of the gate is Ti / Au with a thickness of 10nm / 100nm. The deposition rate is

[0087] Figure 2 The capacitance measurement and dielectric constant curve of the capacitor with GaInS3 as the dielectric layer are shown in the schematic diagram and optical photograph. As shown in the schematic diagram and optical photograph, a capacitor with Ti-Au / GaInS3 / Au structure was prepared to test the capacitance of GaInS3. In the voltage range of -3 to 3V and the frequency of 1kHz to 1MHz, GaInS3 showed a stable capacitance value of ~1.2pF, and further extracted its relative dielectric constant of ~12.0, which is much larger than the traditional dielectric layer SiO2 (~4.0) and two-dimensional BN (~5.0).

[0088] Figure 3 It is an anisotropic characterization of the dielectric layer GaInS3. The in-plane anisotropic absorption of the dielectric layer GaInS3 is analyzed by polarized optical absorption spectroscopy. According to the absorption spectrum at a wavelength of 300-800nm, it can be observed that GaInS3 has obvious angle-dependent absorption in the ultraviolet band. Through extraction and fitting, the anisotropic absorption ratio of GaInS3 at a wavelength of 370nm is ~1.5, which proves that GaInS3 has in-plane anisotropy.

[0089] Figure 4 It is a representation of the anisotropy of the conductive channel material after the conductive channel material and the dielectric layer material in Example 1 are stacked along the armchair crystal direction. Figure 4 As shown in (a), this is a light microscopy photograph of a heterojunction of MoS2 and GaInS3 stacked along the armchair direction. Figure 4 (b) is the polarized photoluminescence (PL) data collected from area number 1 (i.e., only MoS2); Figure 4 (c) is the polarized PL data collected in the number 2 region (i.e., the region where MoS2 and GaInS3 are stacked). According to the comparison, when MoS2 and GaInS3 are stacked along the armchair direction, an obvious anisotropic optical response occurs.

[0090] Figure 5 The transfer characteristic output curve and subthreshold swing curve of the anisotropic dielectric layer transistor in Example 1. Under the modulation of the GaInS3 dielectric layer, the MoS2 transistor exhibits excellent electrical properties, such as low leakage current (<10 -12 A) High on / off ratio (>106 ), small subthreshold swing (71.6mV dec -1 ).

[0091] Figure 6 The transfer characteristic output curves of the anisotropic dielectric layer transistor in Example 1 in different directions. Under the control of the anisotropic GaInS3 dielectric layer, the conductivity ratio of the MoS2 transistor in the armchair direction (AC) and the zigzag direction (ZZ) is as high as 10 6 , which is much higher than the anisotropy ratio reported for current two-dimensional materials.

[0092] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An anisotropic dielectric layer transistor, characterized in that: The transistor includes a substrate, a gate, a source electrode, a drain electrode, a conductive channel and a dielectric layer, wherein the substrate serves as a carrier of the conductive channel, the dielectric layer is stacked above the conductive channel, the armchair crystal orientations of the dielectric layer and the conductive channel coincide, the source electrode and the drain electrode are arranged on both sides of the conductive channel, and the gate is arranged on the dielectric layer, wherein the dielectric layer has a low-symmetry crystal structure and is anisotropic in a horizontal plane.

2. The anisotropic dielectric layer transistor according to claim 1, characterized in that: The dielectric layer is made of a material having a C2 rotational symmetry crystal structure.

3. The anisotropic dielectric layer transistor according to claim 2, characterized in that: The material of the dielectric layer is one of gallium indium sulfide, molybdenum oxide, chlorinated vanadium oxide, bismuth selenium oxide and brominated chromium sulfide.

4. An anisotropic dielectric layer transistor according to claim 1 or 2, characterized in that: The thickness of the dielectric layer is 10nm-100nm.

5. An anisotropic dielectric layer transistor as claimed in claim 1 or 2, characterized in that: The dielectric constant of the dielectric layer is greater than 10.

6. An anisotropic dielectric layer transistor as claimed in claim 1 or 2, characterized in that: The conductive channel is made of a material with C3 rotational symmetry and has a thickness of 1 nm to 20 nm.

7. The anisotropic dielectric layer transistor according to claim 6, characterized in that: The material with C3 rotational symmetry is molybdenum sulfide, molybdenum selenide, molybdenum telluride, tungsten sulfide, tungsten selenide or graphene.

8. An anisotropic dielectric layer transistor as claimed in claim 1 or 2, characterized in that: The gate, source electrode and drain electrode each include two layers, one layer is a metal electrode that can achieve ohmic contact with the conductive channel, and the other layer is a protective layer to prevent the metal electrode from oxidation. The thickness of the metal electrode is 5nm to 10nm, and the thickness of the protective layer is 50nm to 100nm respectively.

9. An anisotropic dielectric layer transistor as claimed in claim 1 or 2, characterized in that: The substrate is an insulating rigid or flexible substrate.

10. A method for preparing an anisotropic dielectric layer transistor according to any one of claims 1 to 9, characterized in that: The preparation method comprises the following steps: preparing a conductive channel and a dielectric layer respectively; respectively detecting the crystal directions of the conductive channel and the dielectric layer, and then stacking the dielectric layer and the conductive channel along the armchair crystal direction and then placing them on the substrate; A source electrode and a drain electrode are respectively arranged on both sides of the conductive channel, and a gate is arranged on the dielectric layer, so as to obtain the desired transistor.

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