Semiconductor dynamic capacitance test system

Abstract

A semiconductor dynamic capacitance test system belongs to the technical field of semiconductor device characteristic measurement. The invention aims to solve the problem of poor linearity of the existing dynamic capacitance test platform for the semiconductor device. Comprising the following steps: generating a temperature control signal target value and detecting a control enable voltage signal through a controller; the temperature control module enables the detection platform to reach a temperature control signal target value; a reference direct-current voltage signal and a target sine voltage signal are generated by an integrated circuit chip according to a detection control enabling voltage signal through an integrated detection preceding-stage interface circuit and are loaded to the two ends of the capacitor to be detected; the capacitor to be detected is arranged on the detection platform; and meanwhile, voltage waveforms at the two ends of the capacitor to be detected are collected through the integrated detection pre-stage interface circuit, and the voltage waveforms are processed to obtain a capacitance measurement value. The method is used for testing the dynamic capacitance of the semiconductor.

Description

Technical Field

[0001] The invention relates to a semiconductor dynamic capacitance testing system, belonging to the technical field of semiconductor device characteristic measurement. Background Art

[0002] In the field of semiconductor components, the linearity, temperature characteristics and frequency characteristics of device capacitance or parasitic capacitance are important parts of semiconductor component parameter testing. The results of such tests can guide laboratories or semiconductor process manufacturers to determine the performance of semiconductor components manufactured using different materials or processes, or help analyze the reasons for the failure of semiconductor devices or integrated circuits at different temperatures, and guide the improvement of the performance of semiconductor devices and circuits. In addition, for MOS or BJT semiconductor devices, by using different models in semiconductor device physics, the process parameters such as doping concentration, carrier lifetime, gate oxide thickness, interface trap density, etc. can be inferred based on their dynamic parasitic capacitance at a certain frequency, which is conducive to analyzing the reliability of the device; for capacitor devices in integrated circuits, the performance indicators such as linearity and temperature characteristics of capacitor devices can be summarized from the capacitance test results. Accurately measuring these process parameters will benefit the entire production chain, for example, accurate device models can be established, the credibility of simulations can be improved, and the yield rate of wafer production can be improved.

[0003] At present, semiconductor dynamic capacitance testers are mainly developed in the direction of high resolution. When measuring semiconductor dynamic capacitance, an AC sinusoidal signal is usually superimposed with a DC bias and input to both ends of the capacitor to be tested, coupling the capacitor to the amplitude of the sinusoidal signal. After demodulation and appropriate filtering, a DC quantity representing the AC amplitude on both sides of the capacitor is obtained. After appropriate amplification, the DC quantity is converted into digital information that can be processed by the computer through the ADC, returned to the microcontroller test result input port for detection, and finally outputs the test result represented by a digital quantity.

[0004] The linearity of the semiconductor device dynamic capacitance characteristic measurement system is a key parameter that affects the performance of the test system. The existing semiconductor dynamic capacitance test platform has problems such as low resolution, low linearity and large size. Summary of the invention

[0005] Aiming at the problem of poor linearity of existing semiconductor device dynamic capacitance testing platforms, the present invention provides a semiconductor dynamic capacitance testing system.

[0006] A semiconductor dynamic capacitance testing system of the present invention comprises: A controller, used to generate a temperature control signal target value and a detection control enable voltage signal according to a detection instruction; and also used to receive a capacitance measurement value and a temperature measurement value; The temperature control module is used to heat the detection platform according to the target value of the temperature control signal, and make the detection platform reach the target value of the temperature control signal through an internal closed-loop control method; at the same time, the actual temperature of the detection platform is detected to obtain the temperature measurement value; The integrated detection front-end interface circuit is used to generate a reference DC voltage signal and a target sinusoidal voltage signal according to the detection control enable voltage signal using an integrated circuit chip and load them to the capacitor to be tested. The capacitor to be measured Set on the detection platform; the integrated detection front-end interface circuit is also used to collect the capacitance to be tested The voltage waveform at both ends is processed to obtain the capacitance measurement value.

[0007] According to the semiconductor dynamic capacitance test system of the present invention, the temperature control module includes a temperature sensor, a temperature ADC module, a temperature PID control module, a power drive module, a fan and a resistance wire. The temperature sensor is used to obtain the temperature measurement value of the detection platform in analog form, and the analog temperature measurement value is converted into a digital temperature measurement value through the temperature ADC module; the temperature PID control module obtains a temperature control signal according to the difference between the temperature control signal target value and the digital temperature measurement value, and the power drive module drives the fan or resistance wire according to the temperature control signal to cool down or heat up the detection platform to reach the temperature control signal target value.

[0008] According to the semiconductor dynamic capacitance test system of the present invention, the integrated detection front-stage interface circuit includes a load signal generating module, a capacitance detection and amplification circuit and a capacitance ADC module. The bracket loading signal generating module generates a target sinusoidal voltage signal through a resonant crystal based on the detection control enabling voltage signal and PID control, and generates a reference DC voltage signal at the same time; then generates a square wave signal with the same phase and frequency as the target sinusoidal voltage signal based on the target sinusoidal voltage signal, and multiplies the frequency to obtain a high-frequency clock signal as the clock of the capacitor ADC module; Capacitor detection and amplification circuit, used to add the target sinusoidal voltage signal and the reference DC voltage signal and load them to the capacitor to be tested Two ends; detect the capacitance to be tested The voltage waveform at both ends is demodulated by a square wave signal obtained by a loading signal generating module to obtain a DC analog voltage representing the capacitance value; The capacitance ADC module, driven by the high-frequency clock signal generated by the loading signal generating module, converts the DC analog voltage into a digital form to obtain a capacitance measurement value.

[0009] According to the semiconductor dynamic capacitance test system of the present invention, the loading signal generating module includes a resonant crystal, a gain module G1, a gain module G2, a phase-locked loop PLL, an amplitude detection module, a low-pass filter LPF, a loading signal PID controller, a gain module G3 and a gain module G4. The gain module G1 detects the movement of the resonant crystal as a sinusoidal voltage signal, and obtains the original DC voltage signal representing the sinusoidal voltage signal after passing through the amplitude detection module and the low-pass filter LPF; The detection control enable voltage signal is passed through the gain module G3 to obtain a target DC voltage signal, the original DC voltage signal is subtracted from the target DC voltage signal to obtain an amplitude increment, and the amplitude increment is input into the resonant crystal after passing through the loading signal PID controller and the gain module G2 to realize positive feedback, so that the sinusoidal voltage signal output by the resonant crystal is finally stabilized to the target sinusoidal voltage signal; The target sinusoidal voltage signal output by the resonant crystal is passed through the gain module G1 and the phase-locked loop PLL to obtain a square wave signal with the same phase and frequency as the target sinusoidal voltage signal. times the high frequency clock signal; The detection control enable voltage signal is outputted as a reference DC voltage signal Vdc via the gain module G4.

[0010] According to the semiconductor dynamic capacitance test system of the present invention, the capacitance detection part of the capacitance detection and amplification circuit includes a variable resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a variable resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, an operational amplifier AMP1, an operational amplifier AMP2, an operational amplifier AMP3, an operational amplifier AMP4, a capacitor C1 and a capacitor C2, One end of the variable resistor R1 is connected to the target sinusoidal voltage signal, one end of the resistor R2 is connected to the reference DC voltage signal Vdc, the other end of the resistor R1 is connected to the other end of the resistor R2, and is also connected to the inverting input of the operational amplifier AMP1, and the non-inverting input of the operational amplifier AMP1 is grounded via the resistor R3; the inverting input of the operational amplifier AMP1 is connected to the output of the operational amplifier AMP1 via the resistor R4, and the output of the operational amplifier AMP1 is connected to the capacitor to be measured through the probe one end; The inverting input terminal of the operational amplifier AMP2 is connected to the capacitor to be tested through a probe At the other end, the inverting input of the op amp AMP2 is connected to the output of the op amp AMP2 through the capacitor C2, and the resistor R6 is connected in parallel with the capacitor C2; the non-inverting input of the op amp AMP2 is grounded through the capacitor C1, and the resistor R5 is connected in parallel with the capacitor C1; the output of the op amp AMP2 is connected to the inverting input of the op amp AMP3 through the variable resistor R7, the inverting input of the op amp AMP3 is connected to the output of the op amp AMP3 through the resistor R9, and the non-inverting input of the op amp AMP3 is grounded through the resistor R8; the output of the op amp AMP3 is used as the capacitor to be measured The positive output terminal a of the voltage waveform at both ends; The output of the op amp AMP3 is connected to the inverting input of the op amp AMP4 via resistor R10, the inverting input of the op amp AMP4 is connected to the output of the op amp AMP4 via resistor R11, and the inverting input of the op amp AMP4 is grounded via resistor R12; the output of the op amp AMP4 is used as the capacitor to be measured. The negative pole of the voltage waveform at both ends is output terminal b.

[0011] According to the semiconductor dynamic capacitance test system of the present invention, the amplification part of the capacitance detection and amplification circuit includes a switch S1, a switch S2, an inverter N1, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an operational amplifier AMP5 and an operational amplifier AMP6, One end of the switch S1 is connected to the positive output end a of the voltage waveform, one end of the switch S2 is connected to the negative output end b of the voltage waveform, the other end of the switch S1 is connected to the other end of the switch S2, the control end of the switch S1 is connected to the square wave signal, and the square wave signal is connected to the control end of the switch S2 after being inverted by the inverter N1; The other end of the switch S1 is connected to one end of the resistor R14 via the resistor R13, and one end of the resistor R14 is grounded via the capacitor C3; the other end of the resistor R14 is connected to the inverting input end of the operational amplifier AMP5 via the resistor R15, and the other end of the resistor R14 is connected to the output end of the operational amplifier AMP5 via the resistor R16, and the inverting input end of the operational amplifier AMP5 is connected to the output end of the operational amplifier AMP5 via the capacitor C5; the non-inverting input end of the operational amplifier AMP5 is grounded via the resistor R21; the output end of the operational amplifier AMP5 is connected to the non-inverting input end of the operational amplifier AMP6 via the resistor R17, and the inverting input end of the operational amplifier AMP6 is grounded via the resistor R18, and the inverting input end of the operational amplifier AMP6 is connected to the output end of the operational amplifier AMP6 via the resistor R19, and the output end of the operational amplifier AMP6 is connected to one end of the resistor R20, and the other end of the resistor R20 outputs a DC analog voltage representing the capacitance value; the other end of the resistor R20 is also grounded via the capacitor C6.

[0012] Beneficial effects of the present invention: The present invention uses an integrated circuit chip to measure the capacitance value of the capacitor to be measured, and the devices on the same integrated circuit can have good repeatability. Using an integrated circuit chip to implement dynamic capacitance testing of integrated semiconductor devices can effectively improve system linearity and reduce system volume.

[0013] The present invention uses an integrated circuit chip to add a reference DC voltage signal and a sinusoidal input, and excites the electrode plate on one side of the capacitor to be measured, and obtains a modulated signal containing capacitance information through capacitive coupling, and then obtains a DC signal representing the capacitance through square wave demodulation and low-pass filtering, and finally converts it into digital information that can be processed by a computer through an ADC and returns it to a controller, which can be transmitted back to the computer through a USB for data acquisition, processing and storage; the present invention realizes the measurement of dynamic capacitance of semiconductor devices at different temperatures through temperature control.

[0014] The system of the present invention couples the capacitance to the amplitude of the AC analog signal through a capacitive reactance amplifier circuit, then leaves the DC component through square wave demodulation and filtering, and finally converts the DC component into a digital signal, thus converting the capacitance value into a digital signal simply, accurately and with high precision; a closed-loop automatic control method is used in the controller to automatically measure the dynamic capacitance of semiconductor devices at different temperatures and achieve stable single temperature point maintenance. The system of the present invention adopts a capacitance amplification detection and sinusoidal demodulation method of impedance ratio detection, which can make the entire system have higher linearity and resolution within the range of 1pF-1000pF. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a test principle block diagram of the semiconductor dynamic capacitance test system of the present invention; Figure 2 This is the principle block diagram of the temperature control module; Figure 3 It is the principle block diagram of the integrated detection front-stage interface circuit; Figure 4 It is the principle block diagram of the loading signal generating module; Figure 5 It is the circuit diagram of the capacitance detection part in the capacitance detection and amplification circuit; Figure 6 It is the circuit diagram of the amplification part in the capacitance detection and amplification circuit. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0018] The present invention will be further described below in conjunction with the accompanying drawings, but is not intended to be a limitation of the present invention.

[0019] Combination Figure 1 As shown, the present invention provides a semiconductor dynamic capacitance testing system, comprising: The controller 100 is used to generate a temperature control signal target value and a detection control enable voltage signal according to a detection instruction; and is also used to receive a capacitance measurement value and a temperature measurement value; The temperature control module 200 is used to heat the detection platform according to the target value of the temperature control signal, and make the detection platform reach the target value of the temperature control signal through an internal closed-loop control method; at the same time, the actual temperature of the detection platform is detected to obtain a temperature measurement value; The integrated detection front-end interface circuit 300 is used to generate a reference DC voltage signal and a target sinusoidal voltage signal according to the detection control enable voltage signal using an integrated circuit chip and load them to the capacitor to be tested. The capacitor to be measured The integrated detection front-end interface circuit 300 is also used to collect the capacitance to be tested. The voltage waveform at both ends is processed to obtain the capacitance measurement value.

[0020] The controller can be implemented by a single chip microcomputer.

[0021] Further, combined with Figure 2 As shown, the temperature control module 200 includes a temperature sensor, a temperature ADC module, a temperature PID control module, a power drive module, a fan and a resistance wire. The temperature sensor is used to obtain the temperature measurement value of the detection platform in analog form, and the analog temperature measurement value is converted into a digital temperature measurement value through the temperature ADC module; the temperature PID control module obtains a temperature control signal according to the difference between the temperature control signal target value and the digital temperature measurement value, and the power drive module drives the fan or resistance wire according to the temperature control signal to cool down or heat up the detection platform to reach the temperature control signal target value.

[0022] Combination Figure 3 As shown, the integrated detection front-stage interface circuit 300 includes a load signal generating module 310, a capacitance detection and amplification circuit 320 and a capacitance ADC module 330. The bracket load signal generating module 310 generates a target sinusoidal voltage signal through a resonant crystal based on the detection control enabling voltage signal and PID control, and generates a reference DC voltage signal at the same time; then generates a square wave signal with the same phase and frequency as the target sinusoidal voltage signal based on the target sinusoidal voltage signal, and multiplies the frequency to obtain a high-frequency clock signal as the clock of the capacitor ADC module 330; The capacitance detection and amplification circuit 320 is used to add the target sinusoidal voltage signal and the reference DC voltage signal and load them to the capacitor to be tested. Two ends; detect the capacitance to be tested The voltage waveform at both ends is demodulated by using the square wave signal obtained by the loading signal generating module 310 to obtain a DC analog voltage representing the capacitance value; The capacitance ADC module 330 , driven by the high-frequency clock signal generated by the load signal generating module 310 , converts the DC analog voltage into a digital form to obtain a capacitance measurement value.

[0023] Capacitor to be tested The signals at both ends are detected by the capacitance detection and amplification circuit 320 and amplified, demodulated and filtered to output a DC analog voltage representing the capacitance value; the DC analog voltage is converted into a digital value representing the capacitance value by the ADC and then input into the controller.

[0024] After receiving the controller's command to start detection, the integrated detection front-stage interface circuit 300 enters the working state. The loading signal generating module 310 generates a low-noise, frequency-stable sinusoidal voltage signal through a closed-loop self-oscillation of a resonant crystal, obtains a square wave with the same frequency and phase as the sinusoidal signal through a phase-locked loop, and obtains the clock required by the ADC part by frequency multiplication; then the signal is input to the capacitance detection and amplification circuit 320 and the capacitance ADC module 330; the loading signal generating module 310 simultaneously generates a reference DC voltage signal to the capacitance detection and amplification circuit 320.

[0025] The capacitor detection and amplification circuit 320 adds the target sinusoidal voltage signal and the reference DC voltage signal and loads them to the loading voltage input terminal of the capacitor to be measured, detects the voltage output waveform of the capacitor to be measured and demodulates it using the square wave generated by the loading signal generation module 310, and then performs low-pass filtering to obtain a DC analog voltage representing the capacitance value; then the DC analog voltage is input to the capacitor ADC module 330.

[0026] Driven by the high-frequency clock signal generated by the loading signal generating module, the capacitance ADC module 330 converts the DC analog voltage generated by the capacitance detection and amplification circuit 320 into a digital signal that can be processed by the controller and inputs it into the controller.

[0027] Combination Figure 4As shown, the loading signal generating module 310 includes a resonant crystal, a gain module G1, a gain module G2, a phase-locked loop PLL, an amplitude detection module, a low-pass filter LPF, a loading signal PID controller, a gain module G3 and a gain module G4. The gain module G1 detects the movement of the resonant crystal as a sinusoidal voltage signal, and obtains the original DC voltage signal representing the sinusoidal voltage signal after passing through the amplitude detection module and the low-pass filter LPF; The detection control enable voltage signal is passed through the gain module G3 to obtain a target DC voltage signal, the original DC voltage signal is subtracted from the target DC voltage signal to obtain an amplitude increment, and the amplitude increment is input into the resonant crystal after passing through the loading signal PID controller and the gain module G2 to realize positive feedback, so that the sinusoidal voltage signal output by the resonant crystal is finally stabilized to the target sinusoidal voltage signal; The target sinusoidal voltage signal output by the resonant crystal is passed through the gain module G1 and the phase-locked loop PLL to obtain a square wave signal with the same phase and frequency as the target sinusoidal voltage signal. times the high frequency clock signal; The detection control enable voltage signal is outputted as a reference DC voltage signal Vdc via the gain module G4.

[0028] The target sinusoidal voltage signal is a stable sinusoidal oscillation with a natural frequency and an amplitude equal to the expected value. The sinusoidal voltage output by the gain module G1 has the same frequency and phase as the target sinusoidal voltage signal. The phase-locked loop PLL detects the sinusoidal voltage signal output by the gain module G1 and generates a square wave signal with the same phase and frequency as the sinusoidal voltage signal, and at the same time multiplies the frequency of the square wave signal. A high-frequency clock signal times the ADC clock.

[0029] Combination Figure 5 As shown, the capacitance detection part of the capacitance detection and amplification circuit 320 includes a variable resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a variable resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, an operational amplifier AMP1, an operational amplifier AMP2, an operational amplifier AMP3, an operational amplifier AMP4, a capacitor C1 and a capacitor C2, One end of the variable resistor R1 is connected to the target sinusoidal voltage signal, one end of the resistor R2 is connected to the reference DC voltage signal Vdc, the other end of the resistor R1 is connected to the other end of the resistor R2, and is also connected to the inverting input of the operational amplifier AMP1, and the non-inverting input of the operational amplifier AMP1 is grounded via the resistor R3; the inverting input of the operational amplifier AMP1 is connected to the output of the operational amplifier AMP1 via the resistor R4, and the output of the operational amplifier AMP1 is connected to the capacitor to be measured through the probe one end; The inverting input terminal of the operational amplifier AMP2 is connected to the capacitor to be tested through a probe At the other end, the inverting input of the op amp AMP2 is connected to the output of the op amp AMP2 through the capacitor C2, and the resistor R6 is connected in parallel with the capacitor C2; the non-inverting input of the op amp AMP2 is grounded through the capacitor C1, and the resistor R5 is connected in parallel with the capacitor C1; the output of the op amp AMP2 is connected to the inverting input of the op amp AMP3 through the variable resistor R7, the inverting input of the op amp AMP3 is connected to the output of the op amp AMP3 through the resistor R9, and the non-inverting input of the op amp AMP3 is grounded through the resistor R8; the output of the op amp AMP3 is used as the capacitor to be measured The positive output terminal a of the voltage waveform at both ends; The output of the op amp AMP3 is connected to the inverting input of the op amp AMP4 via resistor R10, the inverting input of the op amp AMP4 is connected to the output of the op amp AMP4 via resistor R11, and the inverting input of the op amp AMP4 is grounded via resistor R12; the output of the op amp AMP4 is used as the capacitor to be measured. The negative pole of the voltage waveform at both ends is output terminal b.

[0030] Combination Figure 6 As shown, the amplification part of the capacitance detection and amplification circuit 320 includes a switch S1, a switch S2, an inverter N1, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an operational amplifier AMP5 and an operational amplifier AMP6, One end of the switch S1 is connected to the positive output end a of the voltage waveform, one end of the switch S2 is connected to the negative output end b of the voltage waveform, the other end of the switch S1 is connected to the other end of the switch S2, the control end of the switch S1 is connected to the square wave signal, and the square wave signal is connected to the control end of the switch S2 after being inverted by the inverter N1; The other end of the switch S1 is connected to one end of the resistor R14 via the resistor R13, and one end of the resistor R14 is grounded via the capacitor C3; the other end of the resistor R14 is connected to the inverting input end of the operational amplifier AMP5 via the resistor R15, and the other end of the resistor R14 is connected to the output end of the operational amplifier AMP5 via the resistor R16, and the inverting input end of the operational amplifier AMP5 is connected to the output end of the operational amplifier AMP5 via the capacitor C5; the non-inverting input end of the operational amplifier AMP5 is grounded via the resistor R21; the output end of the operational amplifier AMP5 is connected to the non-inverting input end of the operational amplifier AMP6 via the resistor R17, and the inverting input end of the operational amplifier AMP6 is grounded via the resistor R18, and the inverting input end of the operational amplifier AMP6 is connected to the output end of the operational amplifier AMP6 via the resistor R19, and the output end of the operational amplifier AMP6 is connected to one end of the resistor R20, and the other end of the resistor R20 outputs a DC analog voltage representing the capacitance value; the other end of the resistor R20 is also grounded via the capacitor C6.

[0031] Combination Figure 5 As shown, the voltage relationship in the integrated detection front-stage interface circuit 300 includes: , , , , , In the formula is the voltage signal output from the output terminal of the operational amplifier AMP1. is the target sinusoidal voltage signal, is the frequency of the target sinusoidal voltage signal, For time; is the voltage signal output from the output terminal of the operational amplifier AMP2. is the equivalent impedance of the resistor R6 and capacitor C2 in parallel, The capacitor to be tested The equivalent impedance of The voltage signal output from the output terminal of op amp AMP3, It is the voltage signal outputted from the output terminal of the operational amplifier AMP4; make , and Inverting, The capacitor to be tested The voltage waveform signal at both ends.

[0032] The amplitude of the capacitor to be measured is coupled size.

[0033] Combination Figure 6 As shown, the DC analog voltage representing the capacitance value obtained in the capacitance detection and amplification circuit 320 is expressed as : , In the formula The total gain of the filter composed of the operational amplifier AMP5 and the resistor R13, the capacitor C3, the resistor R14, the capacitor C4, the resistor R15, the resistor R16, the capacitor C5, and the resistor R21 and the gain module composed of the operational amplifier AMP6 and the resistor R17, the resistor R18, the resistor R19, the resistor R20, and the capacitor C6; Represents the supremum.

[0034] DC analog voltage The calculation formula ignores the frequency signals within the limited bandwidth of the filter.

[0035] Going a step further, combined Figure 1As shown, a human-computer interaction module or a host computer is also included; the human-computer interaction module or the host computer is used to send a detection instruction to the controller 100 and receive the capacitance measurement value and the temperature measurement value transmitted by the controller 100.

[0036] The human-computer interaction module or the host computer can be used to display the capacitance measurement value and the temperature measurement value. The host computer can also be used to store data.

[0037] Combination Figure 1 As shown, this embodiment also includes a power supply module for providing working power to the controller 100, the temperature control module 200 and the integrated detection front-stage interface circuit 300; The power module provides +5V power for the controller 100, provides +5V power for the temperature sensor, temperature ADC module and temperature PID control module in the temperature control module 200, provides +12V power for the fan and resistance wire, and provides ±5V and ±15V power for the integrated detection front-stage interface circuit 300.

[0038] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that the features described in conjunction with a single embodiment may be used in other described embodiments.

Claims

1. A semiconductor dynamic capacitance test system, characterized in that: include: A controller (100) is used to generate a temperature control signal target value and a detection control enable voltage signal according to a detection instruction; and is also used to receive a capacitance measurement value and a temperature measurement value; A temperature control module (200) is used to heat the detection platform according to a target value of a temperature control signal, and to make the detection platform reach the target value of the temperature control signal through an internal closed-loop control method; and to perform actual temperature detection on the detection platform to obtain a temperature measurement value; An integrated detection front-stage interface circuit (300) is used to generate a reference DC voltage signal and a target sinusoidal voltage signal according to a detection control enabling voltage signal using an integrated circuit chip and load the signals to a capacitor to be tested. The capacitor to be measured The integrated detection front-end interface circuit (300) is arranged on the detection platform and is also used to collect the capacitance to be tested. The voltage waveform at both ends is processed to obtain the capacitance measurement value.

2. The semiconductor dynamic capacitance testing system according to claim 1, characterized in that: The temperature control module (200) comprises a temperature sensor, a temperature ADC module, a temperature PID control module, a power drive module, a fan and a resistance wire. The temperature sensor is used to obtain the temperature measurement value of the detection platform in analog form, and the analog temperature measurement value is converted into a digital temperature measurement value through the temperature ADC module; the temperature PID control module obtains a temperature control signal according to the difference between the temperature control signal target value and the digital temperature measurement value, and the power drive module drives the fan or resistance wire according to the temperature control signal to cool down or heat up the detection platform to reach the temperature control signal target value.

3. The semiconductor dynamic capacitance testing system according to claim 2, characterized in that: The integrated detection front-stage interface circuit (300) comprises a loading signal generating module (310), a capacitance detection and amplification circuit (320) and a capacitance ADC module (330). The bracket load signal generating module (310) generates a target sinusoidal voltage signal through a resonant crystal based on the detection control enabling voltage signal and PID control, and simultaneously generates a reference DC voltage signal; then generates a square wave signal with the same phase and frequency as the target sinusoidal voltage signal based on the target sinusoidal voltage signal, and multiplies the frequency to obtain a high-frequency clock signal as the clock of the capacitor ADC module (330); The capacitance detection and amplification circuit (320) is used to add the target sinusoidal voltage signal and the reference DC voltage signal and load them to the capacitor to be tested. Two ends; detect the capacitance to be tested voltage waveforms at both ends, and demodulating the voltage waveforms using a square wave signal obtained by a loading signal generating module (310) to obtain a DC analog voltage representing a capacitance value; The capacitance ADC module (330), driven by the high-frequency clock signal generated by the loading signal generating module (310), converts the DC analog voltage into a digital form to obtain a capacitance measurement value.

4. The semiconductor dynamic capacitance test system according to claim 3, characterized in that: The loading signal generating module (310) comprises a resonant crystal, a gain module G1, a gain module G2, a phase-locked loop PLL, an amplitude detection module, a low-pass filter LPF, a loading signal PID controller, a gain module G3 and a gain module G4. The gain module G1 detects the movement of the resonant crystal as a sinusoidal voltage signal, and obtains the original DC voltage signal representing the sinusoidal voltage signal after passing through the amplitude detection module and the low-pass filter LPF; The detection control enable voltage signal is passed through the gain module G3 to obtain a target DC voltage signal, the original DC voltage signal is subtracted from the target DC voltage signal to obtain an amplitude increment, and the amplitude increment is input into the resonant crystal after passing through the loading signal PID controller and the gain module G2 to realize positive feedback, so that the sinusoidal voltage signal output by the resonant crystal is finally stabilized to the target sinusoidal voltage signal; The target sinusoidal voltage signal output by the resonant crystal is passed through the gain module G1 and the phase-locked loop PLL to obtain a square wave signal with the same phase and frequency as the target sinusoidal voltage signal. times the high frequency clock signal; The detection control enable voltage signal is outputted as a reference DC voltage signal Vdc via the gain module G4.

5. The semiconductor dynamic capacitance testing system according to claim 4, characterized in that: The capacitance detection part of the capacitance detection and amplification circuit (320) comprises a variable resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a variable resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, an operational amplifier AMP1, an operational amplifier AMP2, an operational amplifier AMP3, an operational amplifier AMP4, a capacitor C1 and a capacitor C2, One end of the variable resistor R1 is connected to the target sinusoidal voltage signal, one end of the resistor R2 is connected to the reference DC voltage signal Vdc, the other end of the resistor R1 is connected to the other end of the resistor R2, and is also connected to the inverting input of the operational amplifier AMP1, and the non-inverting input of the operational amplifier AMP1 is grounded via the resistor R3; the inverting input of the operational amplifier AMP1 is connected to the output of the operational amplifier AMP1 via the resistor R4, and the output of the operational amplifier AMP1 is connected to the capacitor to be measured through the probe one end; The inverting input terminal of the operational amplifier AMP2 is connected to the capacitor to be tested through a probe At the other end, the inverting input terminal of the operational amplifier AMP2 is connected to the output terminal of the operational amplifier AMP2 through the capacitor C2, and the resistor R6 is connected in parallel with the capacitor C2; The non-inverting input terminal of the operational amplifier AMP2 is grounded via the capacitor C1, and the resistor R5 is connected in parallel with the capacitor C1; The output of the op amp AMP2 is connected to the inverting input of the op amp AMP3 via the variable resistor R7, the inverting input of the op amp AMP3 is connected to the output of the op amp AMP3 via the resistor R9, and the inverting input of the op amp AMP3 is grounded via the resistor R8; the output of the op amp AMP3 is used as the capacitor to be measured. The positive output terminal a of the voltage waveform at both ends; The output of the op amp AMP3 is connected to the inverting input of the op amp AMP4 via resistor R10, the inverting input of the op amp AMP4 is connected to the output of the op amp AMP4 via resistor R11, and the inverting input of the op amp AMP4 is grounded via resistor R12; the output of the op amp AMP4 is used as the capacitor to be measured. The negative pole of the voltage waveform at both ends is output terminal b.

6. The semiconductor dynamic capacitance testing system according to claim 5, characterized in that: The amplification part of the capacitance detection and amplification circuit (320) comprises a switch S1, a switch S2, an inverter N1, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an operational amplifier AMP5 and an operational amplifier AMP6, One end of the switch S1 is connected to the positive output end a of the voltage waveform, one end of the switch S2 is connected to the negative output end b of the voltage waveform, the other end of the switch S1 is connected to the other end of the switch S2, the control end of the switch S1 is connected to the square wave signal, and the square wave signal is connected to the control end of the switch S2 after being inverted by the inverter N1; The other end of the switch S1 is connected to one end of the resistor R14 via the resistor R13, and one end of the resistor R14 is grounded via the capacitor C3; the other end of the resistor R14 is connected to the inverting input end of the operational amplifier AMP5 via the resistor R15, and the other end of the resistor R14 is connected to the output end of the operational amplifier AMP5 via the resistor R16, and the inverting input end of the operational amplifier AMP5 is connected to the output end of the operational amplifier AMP5 via the capacitor C5; the non-inverting input end of the operational amplifier AMP5 is grounded via the resistor R21; the output end of the operational amplifier AMP5 is connected to the non-inverting input end of the operational amplifier AMP6 via the resistor R17, and the inverting input end of the operational amplifier AMP6 is grounded via the resistor R18, and the inverting input end of the operational amplifier AMP6 is connected to the output end of the operational amplifier AMP6 via the resistor R19, and the output end of the operational amplifier AMP6 is connected to one end of the resistor R20, and the other end of the resistor R20 outputs a DC analog voltage representing the capacitance value; the other end of the resistor R20 is also grounded via the capacitor C6.

7. The semiconductor dynamic capacitance testing system according to claim 6, characterized in that: The voltage relationship in the integrated detection front-stage interface circuit (300) includes: ， ， ， ， ， In the formula is the voltage signal output from the output terminal of the operational amplifier AMP1. is the target sinusoidal voltage signal, is the frequency of the target sinusoidal voltage signal, For time; is the voltage signal output from the output terminal of the operational amplifier AMP2. is the equivalent impedance of the resistor R6 and capacitor C2 in parallel, The capacitor to be tested The equivalent impedance of The voltage signal output from the output terminal of op amp AMP3, It is the voltage signal outputted from the output terminal of the operational amplifier AMP4; make , and Inverting, The capacitor to be tested The voltage waveform signal at both ends.

8. The semiconductor dynamic capacitance testing system according to claim 7, characterized in that: The DC analog voltage representing the capacitance value obtained in the capacitance detection and amplification circuit (320) is expressed as: : ， In the formula The total gain of the filter composed of the operational amplifier AMP5 and the resistor R13, the capacitor C3, the resistor R14, the capacitor C4, the resistor R15, the resistor R16, the capacitor C5, and the resistor R21 and the gain module composed of the operational amplifier AMP6 and the resistor R17, the resistor R18, the resistor R19, the resistor R20, and the capacitor C6; Represents the supremum.

9. The semiconductor dynamic capacitance testing system according to claim 1, characterized in that: It also includes a human-machine interaction module or a host computer; the human-machine interaction module or the host computer is used to send a detection instruction to the controller (100) and receive the capacitance measurement value and the temperature measurement value transmitted by the controller (100).

10. The semiconductor dynamic capacitance testing system according to claim 1, characterized in that: It also includes a power supply module, which is used to provide working power to the controller (100), the temperature control module (200) and the integrated detection front-stage interface circuit (300); The power module provides a +5V power supply for the controller (100), provides a +5V power supply for the temperature sensor, the temperature ADC module and the temperature PID control module in the temperature control module (200), provides a +12V power supply for the fan and the resistance wire, and provides ±5V and ±15V power supplies for the integrated detection front-stage interface circuit (300).

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