Manufacturing method of semiconductor structure

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a manufacturing method of a semiconductor structure, and the method comprises the steps: providing a substrate which comprises a plurality of grooves distributed at intervals in a first direction; performing first deposition treatment, and introducing a first silicon source gas into the groove to form a first semiconductor layer on the inner wall of the groove until the width of the remaining groove in the first direction is a preset width; and second deposition treatment is carried out, second silicon source gas is circularly introduced into the groove to form a second semiconductor layer, the second semiconductor layer covers the surface of the first semiconductor layer, the groove is filled with the second semiconductor layer, and the activity of the second silicon source gas is larger than that of the first silicon source gas. The reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used in general computer systems can be divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, consisting of many repeated storage units.

[0003] At present, as the integration of memory becomes higher and higher, structures with high aspect ratios are becoming more and more common. Therefore, when performing deposition processing in structures with high aspect ratios, part of the deposition gas cannot enter the bottom, resulting in the formation of holes in the high aspect ratio, affecting the reliability of the semiconductor structure. Summary of the invention

[0004] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which can at least improve the reliability of forming the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a plurality of grooves arranged at intervals along a first direction; performing a first deposition process, introducing a first silicon source gas into the grooves to form a first semiconductor layer on the inner walls of the grooves until the remaining width of the grooves in the first direction is a preset width; performing a second deposition process, circulating a second silicon source gas into the grooves to form a second semiconductor layer, wherein the second semiconductor layer covers the surface of the first semiconductor layer and fills the grooves, and the activity of the second silicon source gas is greater than that of the first silicon source gas.

[0006] In some embodiments, the first silicon source gas includes monosilane, and the second silicon source gas includes disilane.

[0007] In some embodiments, each time after the second silicon source gas is introduced, the process further includes: introducing a cleaning gas, wherein the cleaning gas is used to clean the second semiconductor layer on the top of the groove before forming the second semiconductor layer that fills the groove.

[0008] In some embodiments, the second silicon source gas and the cleaning gas are cyclically introduced for 20 to 40 seconds each time, and the cleaning gas is introduced for 50 to 70 seconds each time.

[0009] In some embodiments, the preset width is 3-7 nm.

[0010] In some embodiments, a gas flow rate of the second silicon source gas introduced is less than a gas flow rate of the first silicon source gas introduced.

[0011] In some embodiments, the gas flow rate of the first silicon source gas is 750-900 sccm.

[0012] In some embodiments, the gas flow rate of the second silicon source gas is 350-450 sccm.

[0013] In some embodiments, the first deposition process further includes: introducing a doping gas while introducing the first silicon source gas.

[0014] In some embodiments, the introduced doping gas is phosphine.

[0015] In some embodiments, the gas flow rate of the introduced doping gas is 100-180 sccm.

[0016] In some embodiments, the ambient temperature of the first deposition process and / or the ambient temperature of the second deposition process is 400-550°C.

[0017] In some embodiments, after forming the second semiconductor layer, the method further includes: performing a third deposition process, introducing a first silicon source gas into the surface of the second semiconductor layer to form a third semiconductor layer on the top surface of the second semiconductor layer, wherein the bottom surface of the third semiconductor layer is higher than the top surface of the groove.

[0018] In some embodiments, the gas flow rate of the first silicon source gas introduced in the third deposition process is 1500-2500 sccm.

[0019] In some embodiments, the ambient temperature of the third deposition process is 500-580°C.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: a first semiconductor layer is first formed on the inner wall of the groove in the substrate through a first deposition process until the width of the remaining groove in the first direction is a preset width. At this time, a second deposition process is performed again, and a second silicon source gas with greater activity is introduced. The second silicon source gas can diffuse to the bottom of the groove more easily, thereby facilitating the formation of a second semiconductor layer filling the bottom of the groove, thereby improving the problem of easy formation of holes when filling the groove, thereby improving the reliability of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figures 1 to 4 A schematic diagram of the structures corresponding to each step of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] As can be seen from the background art, during the current deposition process, as the aspect ratio gradually increases, some holes may be present in the semiconductor structure formed by the deposition process, thus affecting the reliability of the semiconductor structure.

[0024] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, wherein a first semiconductor layer is first formed on the inner wall of a groove in a substrate through a first deposition process until the width of the remaining groove in the first direction reaches a preset width. At this time, a second deposition process is performed again, and a second silicon source gas with greater activity is introduced. The second silicon source gas is more easily diffused to the bottom of the groove, thereby facilitating the formation of a second semiconductor layer filling the bottom of the groove, thereby improving the problem of easily forming holes when filling the groove, thereby improving the reliability of the formed semiconductor structure.

[0025] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0026] refer to Figures 1 to 4 , Figures 1 to 4 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure.

[0027] In some embodiments, the method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure includes: providing a substrate 100 , wherein the substrate 100 includes a plurality of grooves 110 arranged at intervals along a first direction X.

[0028] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure further includes: performing a first deposition process, introducing a first silicon source gas into the groove 110 to form a first semiconductor layer 120 on the inner wall of the groove 110 until the width of the remaining groove 110 in the first direction X reaches a preset width.

[0029] The method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure also includes: performing a second deposition process, circulating a second silicon source gas into the groove 110 to form a second semiconductor layer 130, the second semiconductor layer 130 covers the surface of the first semiconductor layer 120, and the second semiconductor layer 130 completely fills the groove 110, and the activity of the second silicon source gas is greater than that of the first silicon source gas.

[0030] In the embodiment of the present disclosure, a first semiconductor layer 120 is first formed on the inner wall of the groove 110 in the substrate 100 through a first deposition process, until the width of the remaining groove 110 in the first direction X reaches a preset width. At this time, a second deposition process is performed again, and a second silicon source gas with greater activity is introduced. The second silicon source gas is more easily diffused to the bottom of the groove 110, thereby facilitating the formation of a second semiconductor layer 130 filling the bottom of the groove 110, thereby improving the problem of easily forming holes when filling the groove 110, thereby improving the reliability of the formed semiconductor structure.

[0031] In some embodiments, in some embodiments, the material of the substrate 100 may include a semiconductor material, for example, including but not limited to silicon. In some embodiments, the substrate 100 may include: a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the basic semiconductor includes germanium; the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or III-V semiconductor materials, etc.; the alloy semiconductor includes silicon germanium, silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide, etc. In some embodiments, the substrate 100 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0032] In addition, the substrate 100 may be doped according to design requirements (eg, a P-type substrate or an N-type substrate). In some embodiments, the substrate 100 may be doped with P-type doping ions (eg, boron ions, aluminum ions) or N-type doping ions (eg, phosphorus ions, arsenic ions).

[0033] The substrate 100 is etched to form a plurality of grooves 110 arranged along the first direction X on the substrate 100 . The grooves 110 may be used to form a bit line contact structure later.

[0034] In some embodiments, the groove 110 can also be a groove 110 formed between adjacent capacitors after forming spaced capacitors. The groove 110 is used to subsequently form a conductive layer connecting the upper electrode layers of different capacitors, so that the capacitors share the upper electrode layer and improve the performance of the capacitors.

[0035] In some embodiments, the aspect ratio of the groove 110 may be greater than 5. It should be noted that the depth here refers to the dimension of the groove 110 in a direction perpendicular to the surface of the substrate 100, the width is the dimension of the groove 110 along the first direction X, and the aspect ratio is the ratio of the depth dimension to the width dimension, wherein the larger the aspect ratio, the more difficult it is to form a film layer with a better morphology in the groove 110, that is, the formed film layer is more likely to have holes.

[0036] It can be understood that the second silicon source gas is highly active, and therefore the second semiconductor layer 130 formed by the second silicon source gas is difficult to control. Therefore, the width of the groove 110 in the first direction X is first reduced to a preset width through a first deposition process to avoid the formed second semiconductor layer not conforming to the expected morphology. The first semiconductor layer 120 is first formed in the groove 110 using the first silicon source gas with relatively poor activity, so that a semiconductor layer with a partial desired morphology can be formed in the groove 110, and then the second semiconductor layer 130 is formed using the second silicon source gas with relatively strong activity, so that the second silicon source gas can diffuse to the bottom of the groove 110, so as to form a second semiconductor layer 130 with a better morphology at the bottom of the groove 110.

[0037] It can be understood that the preset width here can be 3 to 7 nm, for example, 4 nm, 5 nm, 5.5 nm, 6 nm or 6.5 nm, etc. When the remaining width of the groove 110 is less than the preset width, the first silicon source gas is introduced into the groove 110. Since the activity of the first silicon source gas is relatively poor, it is difficult for the first silicon source gas to diffuse to the bottom of the groove 110, which will cause holes to be formed in the first semiconductor layer 120, resulting in poor morphology of the formed first semiconductor layer 120, which will affect the reliability of the semiconductor structure. Therefore, when the remaining width of the groove 110 is less than the preset width, the second silicon source gas is circulated into the groove. Since the activity of the second silicon source gas is relatively strong, it is convenient for the second silicon source gas to diffuse to the bottom of the groove 110, so that the formed second semiconductor layer 130 can also have a better morphology at the bottom of the groove 110, thereby reducing the holes in the semiconductor structure and improving the reliability of the semiconductor structure.

[0038] It should be noted that the bottom of the groove 110 mentioned above refers to the portion of the groove 110 close to the substrate 100 .

[0039] It should be noted that the activity of the gas mentioned above may refer to: the diffusion capacity of the gas and / or the gas that is easy to decompose and / or react, that is, the diffusion capacity of the first silicon source gas is smaller than the diffusion capacity of the second silicon source gas and / or the second silicon source gas is more reactive and / or more decomposable than the first silicon source gas.

[0040] In some embodiments, the first silicon source gas includes monosilane, and the second silicon source gas includes disilane. It is understood that disilane has a higher film-forming density, which can improve the smoothness and continuity of the formed second semiconductor layer 130, and disilane has a higher activity than monosilane, so it can be used as the second silicon source gas to form the second semiconductor layer.

[0041] In some embodiments, the first silicon source gas and the second silicon source gas may also be other semiconductor gases, as long as the activity of the second silicon source gas is greater than that of the first silicon source gas, and the second silicon source gas may decompose to produce semiconductor materials or react to produce semiconductor materials.

[0042] In some embodiments, each time after the second silicon source gas is introduced, it also includes: introducing a cleaning gas, and the cleaning gas is used to clean the second semiconductor layer 130 at the top of the groove 110 before forming the second semiconductor layer 130 that fills the groove 110. In other words, cyclically introducing the second silicon source gas may include: introducing the second silicon source gas for a period of time, then stopping the introduction of the second silicon source gas, introducing the cleaning gas while stopping the introduction of the second silicon source gas, and then stopping the introduction of the cleaning gas, and cyclically. By introducing the cleaning gas after each introduction of the second silicon source gas, it is possible to avoid sealing the top of the groove 110 before the second semiconductor layer 130 that fills the groove 110 is formed, and to avoid the subsequent introduction of the second silicon source gas from being unable to enter the bottom of the groove 110.

[0043] It should be noted that the top of the groove 110 here may refer to: the top of the groove 110 away from the substrate 100 .

[0044] In some embodiments, the cleaning gas here may include: nitrogen, argon or carbon dioxide and other chemically stable gases. Taking nitrogen as an example, by introducing nitrogen, it is possible to avoid nitrogen from reacting with disilane, or reacting with by-products produced after the second semiconductor layer 130 is formed. Nitrogen can also be used to clean the top of the groove 110, thereby avoiding the top of the groove 110 from being sealed before the second semiconductor layer 130 that fills the groove 110 is formed, thereby ensuring that disilane can smoothly enter the bottom of the groove 110, thereby improving the morphology of the second semiconductor layer 130, and further improving the reliability of the formed semiconductor structure.

[0045] In some embodiments, the time for each introduction of the second silicon source gas and the cleaning gas in the cycle is 20 to 40 seconds, and the time for each introduction of the cleaning gas is 50 to 70 seconds. The time for each introduction of the second silicon source gas can be 22 seconds, 25 seconds, 30 seconds or 35 seconds, etc., and the time for each introduction of the cleaning gas can be 55 seconds, 58 seconds, 60 seconds or 65 seconds, etc. By setting the time for each introduction of the second silicon source gas to 20 to 40 seconds and the time for each introduction of the cleaning gas to 50 to 70 seconds, it can be ensured that a second semiconductor layer 130 of a certain thickness is formed and the top of the groove 110 is not sealed, thereby further improving the reliability of the semiconductor structure.

[0046] It is understandable that if the time for each introduction of the second silicon source gas is less than 20 seconds before the cleaning gas is introduced, the second silicon source gas may be swept away by the cleaning gas before the second semiconductor layer 130 of a certain thickness is formed, affecting the formation efficiency of the second semiconductor layer 130. If the time for each introduction of the second silicon source gas is greater than 40 seconds, it may result in that the top of the groove 110 is sealed before the cleaning gas is introduced, resulting in that even if the cleaning gas is introduced later, the sealing of the groove 110 cannot be changed, resulting in the second silicon source gas introduced later being unable to enter the bottom of the groove 110, affecting the formation. If the time for each introduction of the cleaning gas is less than 50 seconds, the top of the groove 110 may not be cleaned well, resulting in the top of the groove 110 being sealed during the circulation of the second silicon source gas, resulting in the subsequent introduction of the second silicon source gas being unable to enter the bottom of the groove 110, affecting the reliability of the formed second semiconductor layer 130; if the time for each introduction of the cleaning gas is greater than 70 seconds, the process time of the semiconductor structure manufacturing method will be increased, that is, the cleaning gas is still introduced after the purpose of introducing the cleaning gas has been achieved, resulting in a waste of process time.

[0047] Therefore, by setting the time for introducing the second silicon source gas to 20 to 40 seconds each time, a second semiconductor layer 130 of a certain thickness can be formed each time while preventing the top of the groove 110 from being sealed. The time for introducing the cleaning gas each time is 50 to 70 seconds, which can prevent the second semiconductor layer 130 from being formed at the top of the groove 110 each time and avoid wasting process time.

[0048] In some embodiments, the gas flow rate of the second silicon source gas introduced is less than the gas flow rate of the first silicon source gas introduced. It can be understood that the activity of the first silicon source gas is poorer than that of the second silicon source gas, that is, the first silicon source gas is easy to control, and the formation rate of the first semiconductor layer 120 can be increased by increasing the gas flow rate of the first silicon source gas, thereby reducing the process time of the entire semiconductor structure manufacturing method. Similarly, the activity of the second silicon source gas is strong, and the second silicon source gas is difficult to control. By reducing the gas flow rate of the second silicon source gas, the formation rate of the second semiconductor layer 130 can be reduced, thereby avoiding sealing the top of the groove 110 before the second semiconductor layer 130 that fills the groove 110 is formed, thereby improving the reliability of the formed semiconductor structure.

[0049] In some embodiments, during the process of cyclically introducing the second silicon source gas, the gas flow rate of the second silicon source gas introduced each time can also be reduced in sequence. In other words, the gas flow rate of the second silicon source gas introduced each time is smaller than the gas flow rate of the silicon source gas introduced last time. It can be understood that each time the second silicon source gas is passed through, the width of the groove 110 will be reduced, that is, the second silicon source gas introduced next time will be more likely to seal the top of the groove 110. By reducing the gas flow rate of the second silicon source gas introduced next time, the formation rate of the second semiconductor layer 130 can be reduced, thereby further reducing the possibility of sealing the top of the groove 110 before the second semiconductor layer 130 that fills the groove 110 is formed, thereby further improving the reliability of the formed semiconductor structure.

[0050] In some embodiments, the gas flow rate of the first silicon source gas introduced is 750-900 sccm, for example, 780 sccm, 800 sccm, 850 sccm or 880 sccm, etc. By setting the gas flow rate of the first silicon source gas introduced to 750-900 sccm, the first semiconductor layer 120 can be controlled to have a certain formation rate, while avoiding a large deviation between the width of the remaining groove 110 and the preset width after the first semiconductor layer 120 is formed, thereby improving the reliability of the formed semiconductor structure.

[0051] It is understandable that if the gas flow rate of the first silicon source gas is less than 750 sccm, the formation rate of the first semiconductor layer 120 is too low, which will increase the process time of the entire semiconductor structure manufacturing method. If the gas flow rate of the first silicon source gas is greater than 900 sccm, the formation rate of the first semiconductor layer 120 is too fast, which will make the width of the remaining groove 110 difficult to control and easily cause holes in the formed first semiconductor layer 120, affecting the reliability of the formed first semiconductor layer 120.

[0052] In some embodiments, the gas flow rate of the second silicon source gas introduced is 350-450 sccm, for example, 380 sccm, 400 sccm, 420 sccm or 440 sccm, etc. By setting the gas flow rate of the second silicon source gas introduced to 350-450 sccm, the second semiconductor layer 130 can be formed at a certain rate while preventing the second semiconductor layer 130 from sealing the top of the groove 110 before the second semiconductor layer 130 that fills the groove 110 is formed, thereby improving the reliability of the formed semiconductor structure.

[0053] It is understandable that if the gas flow rate of the second silicon source gas is less than 350 sccm, the formation rate of the second semiconductor layer 130 is too low, which will increase the process time of the entire semiconductor structure manufacturing method. If the gas flow rate of the second silicon source gas is greater than 450 sccm, the formation rate of the second semiconductor layer 130 is too fast, which will cause the top of the groove 110 to be sealed before the second semiconductor layer 130 that fills the groove 110 is formed, resulting in the second semiconductor layer 130 failing to fill the groove 110, affecting the reliability of the formed semiconductor structure.

[0054] In some embodiments, the first deposition process also includes: introducing a doping gas while introducing the first silicon source gas. The first semiconductor layer 120 formed can be doped by introducing the doping gas. The type of doping gas can be selected according to needs to perform N-type doping or P-type doping on the first semiconductor layer 120.

[0055] In some embodiments, the introduced doping gas may be phosphine (PH3) or borane (B2H6), borane may be used as a P-type dopant, and phosphine may be used as an N-type dopant. In the process of introducing phosphine, phosphine is chemically adsorbed by the first semiconductor layer 120 and decomposed into silicon-hydrogen bonds, and at the same time, phosphine is decomposed into a phosphorus layer by hydrogenolysis. After adsorption, the phosphine gas is stable under the gas flow of the first silicon source gas, and the surface of the first semiconductor layer 120 is effectively passivated; in the process of introducing borane, the adhesion coefficient of borane is very small, and it is easy to decompose into boron on the surface of the first semiconductor layer 120, which is conducive to the heterogeneous reaction of the first silicon source gas on the surface of the first semiconductor layer 120, thereby increasing the growth rate of the first semiconductor layer.

[0056] In some embodiments, the introduced doping gas may also be other gases.

[0057] In some embodiments, the gas flow rate of the introduced doping gas may be 100-180 sccm, for example, 120 sccm, 140 sccm, 160 sccm or 170 sccm, etc. By setting the gas flow rate of the introduced doping gas to be 100-180 sccm, it is possible to ensure that the formed first semiconductor layer 120 has a certain doping degree while preventing the introduced doping gas from affecting the formation of the first semiconductor layer.

[0058] Taking phosphine as an example, if the gas flow rate of the introduced doping gas is less than 100 sccm, the doping effect on the first semiconductor layer 120 is not good. Phosphine will inhibit the subsequent deposition of the first silicon source gas on the surface of the first semiconductor layer 120 while passivating the surface of the first semiconductor layer 120. If the gas flow rate of the introduced doping gas is greater than 180 sccm, the formation rate of the first semiconductor layer 120 will be reduced, resulting in a slower formation rate of the first semiconductor layer 120, which will increase the process time of the entire semiconductor structure manufacturing method. Taking borane as an example, If the gas flow rate of the introduced doping gas is less than 100 sccm, the doping effect on the first semiconductor layer 120 is not good. It can be understood that the doping amount entering the first semiconductor layer 120 is also related to the growth rate of the first semiconductor layer 120. If the gas flow rate of the introduced doping gas is greater than 180 sccm, borane will accelerate the growth rate of the first semiconductor layer 120, resulting in a corresponding decrease in the doping ions in the subsequently formed first semiconductor layer 120, resulting in uneven doping in the formed first semiconductor layer 120, affecting the reliability of the formed first semiconductor layer 120.

[0059] During the second deposition process, doping gas, such as borane or phosphine, may also be introduced. The same or corresponding description may refer to the doping gas introduced during the first deposition process.

[0060] It should be noted that, taking phosphine as an example, the gas flow rate of the phosphine gas introduced in the second deposition process can be adjusted according to actual conditions. For example, if the resistance value of the second semiconductor layer 130 to be formed is small, the gas flow rate of the phosphine gas introduced can be increased.

[0061] It should be noted that sccm is a unit of volume flow, representing standard milliliters per minute.

[0062] In some embodiments, the ambient temperature of the first deposition process and / or the ambient temperature of the second deposition process is 400-550° C., for example, 420° C., 450° C., 470° C., 500° C., or 530° C. By controlling the ambient temperature of the first deposition process and / or the ambient temperature of the second deposition process to be 400-550° C., a better generation environment can be provided for forming the first semiconductor layer 120 and the second semiconductor layer 130.

[0063] In some embodiments, setting the ambient temperature of the first deposition treatment and / or the ambient temperature of the second deposition treatment to 400-550° C. is also beneficial for doping the formed first semiconductor layer 120 and / or the second semiconductor layer 130. For example, when the first deposition treatment also includes the introduction of phosphine, at a temperature above 400° C., the phosphine is decomposed to form a phosphorus layer, thereby doping the first semiconductor layer 120 and / or the second semiconductor layer 130.

[0064] In some embodiments, the first deposition process also includes: controlling the gas pressure of the first deposition process to be between 1 and 1.3 torr, such as 1.1 torr, 1.125 torr, 1.15 torr, 1.2 torr or 1.25 torr, etc. By controlling the gas pressure of the first deposition process to be between 1 and 1.3 torr, the formation rate of the first semiconductor layer 120 can be guaranteed during the first deposition process.

[0065] In some embodiments, the second deposition process further includes: controlling the gas pressure of the second deposition process to be 0.5 to 0.75 torr, such as 0.6 torr, 0.65 torr, 0.675 torr or 0.7 torr, etc. By controlling the gas pressure of the second deposition process to be 0.5 to 0.75 torr, the formation rate of the second semiconductor layer 130 can be guaranteed during the second deposition process.

[0066] In some embodiments, the gas pressure of the second deposition process is controlled to be lower than that of the first deposition process. It can be understood that the greater the gas pressure, the faster the formation rate of the corresponding film layer will be. By controlling the gas pressure of the first deposition process to be high, the process time of the entire semiconductor structure manufacturing method can be reduced. By controlling the gas pressure of the second deposition process to be low, it is possible to avoid sealing the top of the groove 110 before the second semiconductor layer 130 that fills the groove 110 is formed.

[0067] It is understandable that the method for controlling the gas pressure of the first deposition process or the second deposition process may be to introduce the first silicon source gas or the second silicon source gas while extracting the byproduct gas generated after the reaction, thereby controlling the gas pressure of the entire environment.

[0068] It should be noted that torr is a unit of pressure, and 1 torr is generally considered to be 1 / 760 times the atmospheric pressure.

[0069] In some embodiments, after forming the second semiconductor layer 130, the process also includes: performing a third deposition process, introducing a first silicon source gas into the surface of the second semiconductor layer 130 to form a third semiconductor layer 140 on the top surface of the second semiconductor layer 130, wherein the bottom surface of the third semiconductor layer 140 is higher than the top surface of the groove 110, and the formation of the third semiconductor layer 140 prepares for subsequent processes.

[0070] It can be understood that after the second deposition process, the groove 110 is filled, and even the formed first semiconductor layer 120 also covers the top surface of the substrate 100, and the formed second semiconductor layer 130 also covers the top surface of the first semiconductor layer 120. Therefore, the top surface of the second semiconductor layer 130 can be higher than the top surface of the substrate 100. Therefore, in the process of forming the third semiconductor layer 140, there is no groove with a high aspect ratio. Therefore, the morphology of the formed third semiconductor layer 140 can be improved by directly introducing the first silicon source gas that is easy to control.

[0071] In some embodiments, the gas flow rate of the first silicon source gas introduced in the third deposition process is 1500-2500 sccm, for example, 1600 sccm, 1800 sccm, 2000 sccm, 2200 sccm or 2400 sccm. It is understandable that after the second deposition process, the groove 110 is filled, so there is no groove with a high aspect ratio in the process of forming the third semiconductor layer 140. By controlling the gas flow rate of the first silicon source gas introduced in the third deposition process to 1500-2500 sccm, the formation rate of the third semiconductor layer 140 can be increased, thereby further reducing the process time of the entire semiconductor structure manufacturing method.

[0072] In some embodiments, the ambient temperature of the third deposition process is 500-580° C., for example, 530° C., 550° C., 560° C., or 570° C. It is understandable that after the second deposition process, the groove 110 is filled, so there is no groove with a high aspect ratio in the process of forming the third semiconductor layer 140. By controlling the ambient temperature of the third deposition process to 500-580° C., the formation rate of the third semiconductor layer 140 can be increased, thereby further reducing the process time of the entire semiconductor structure manufacturing method.

[0073] In some embodiments, the third deposition process further includes: controlling the gas pressure of the third deposition process to be between 0.5 and 0.75 torr, such as 0.6 torr, 0.65 torr, 0.675 torr or 0.7 torr.

[0074] In some embodiments, phosphine may be introduced during the third deposition process to dope the formed third semiconductor layer 140 .

[0075] In some embodiments, the gas flow rate of phosphine introduced during the third deposition process may also be 50-70 sccm, such as 55 sccm, 60 sccm, 63 sccm or 67 sccm.

[0076] In some embodiments, if the first semiconductor layer 120 and the second semiconductor layer 130 serve as part of the upper electrode layer connecting the capacitor, the formation of the third semiconductor layer 140 can also ensure that the upper electrode layers of different capacitors are connected to each other; if the first semiconductor layer 120, the second semiconductor layer 130 and the third semiconductor layer 140 serve as the basis for the subsequent formation of a bit line contact structure, then after the third semiconductor layer 140 is formed, the first semiconductor layer 120, the second semiconductor layer 130 and the third semiconductor layer 140 can also be etched to form a bit line contact structure spaced apart from each other.

[0077] In the embodiment of the present disclosure, a first semiconductor layer 120 is first formed on the inner wall of the groove 110 in the substrate 100 through a first deposition process, until the width of the remaining groove 110 in the first direction X reaches a preset width. At this time, a second deposition process is performed again, and a second silicon source gas with greater activity is introduced. The second silicon source gas is more easily diffused to the bottom of the groove 110, thereby facilitating the formation of a second semiconductor layer 130 filling the bottom of the groove 110, thereby improving the problem of easily forming holes when filling the groove 110, thereby improving the reliability of the formed semiconductor structure.

[0078] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate includes a plurality of grooves arranged at intervals along a first direction; Performing a first deposition process, introducing a first silicon source gas into the groove to form a first semiconductor layer on an inner wall of the groove until the remaining width of the groove in the first direction is a preset width; A second deposition process is performed to circulate a second silicon source gas into the groove to form a second semiconductor layer, wherein the second semiconductor layer covers the surface of the first semiconductor layer and fills the groove, and the activity of the second silicon source gas is greater than that of the first silicon source gas.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first silicon source gas includes monosilane, and the second silicon source gas includes disilane.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Each time after the second silicon source gas is introduced, the method further includes: introducing a cleaning gas, wherein the cleaning gas is used to clean the second semiconductor layer on the top of the groove before forming the second semiconductor layer that fills the groove.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The second silicon source gas and the cleaning gas are cyclically introduced for 20 to 40 seconds each time, and the cleaning gas is introduced for 50 to 70 seconds each time.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The preset width is 3-7 nm.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The gas flow rate of the second silicon source gas introduced is smaller than the gas flow rate of the first silicon source gas introduced.

7. The method for manufacturing a semiconductor structure according to claim 1 or 6, characterized in that: The gas flow rate of the first silicon source gas introduced is 750-900 sccm.

8. The method for manufacturing a semiconductor structure according to claim 1 or 6, characterized in that: The gas flow rate of the second silicon source gas introduced is 350-450 sccm.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first deposition process further includes: introducing a doping gas while introducing the first silicon source gas.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The introduced doping gas is phosphine or borane.

11. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The gas flow rate of the introduced doping gas is 100-180 sccm.

12. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The ambient temperature of the first deposition process and / or the ambient temperature of the second deposition process is 400-550°C.

13. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After forming the second semiconductor layer, the method further includes: performing a third deposition process, introducing a first silicon source gas into the surface of the second semiconductor layer to form a third semiconductor layer on the top surface of the second semiconductor layer, wherein the bottom surface of the third semiconductor layer is higher than the top surface of the groove.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: The gas flow rate of the first silicon source gas introduced in the third deposition process is 1500-2500 sccm.

15. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: The ambient temperature of the third deposition process is 500-580°C.

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