Low-power-consumption nonvolatile memory device, memory array and preparation method thereof

Abstract

Compared with a common structure of a magnetic tunnel junction, the low-power-consumption nonvolatile memory device, the memory array and the preparation method thereof are characterized in that a non-uniform magnetic moment induction layer is additionally sputtered on an upper interface or a lower interface of a free layer or is consistent with the common structure of the magnetic tunnel junction; the difference is that the thickness of the upper ferromagnetic layer or the lower ferromagnetic layer in the free layer is not uniform, the upper ferromagnetic layer or the lower ferromagnetic layer grows in a wedge shape from thin to thick, and the perpendicular magnetic anisotropy is reduced along with increase of the thickness. The invention provides two low-power-consumption nonvolatile memory device structure design schemes and storage array arrangement design, is suitable for a CMOS standard logic circuit, and can effectively improve the writing speed, reduce the MTJ overturning current density and the writing energy consumption, and improve the MRAM storage density.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a low-power non-volatile memory device, a memory array and a preparation method thereof. Background Art

[0002] Magnetic Random Access Memory (MRAM) is an emerging information storage technology based on spin properties. With its non-volatility, ultra-low static power consumption, fast read and write, high storage density, strong durability, natural radiation resistance and compatibility with advanced CMOS / superconducting processes, MRAM is a rising star in the storage field. It accelerates the development of new memory and is expected to break through the development bottleneck of traditional semiconductor memory (SRAM, DRAM, flash memory) that stores information based on electronic charge properties to meet the storage needs of contemporary huge information. Its storage unit usually consists of a core storage device - magnetic tunnel junction (MTJ) and a semiconductor device that acts as a switch - metal oxide semiconductor field effect transistor (MOSFET). MTJ is generally composed of a buffer layer, a pinned layer, a reference layer, a barrier layer, a free layer, a cap layer, and a hard mask layer. The most important components are: (1) the reference layer, which is made of ferromagnetic material. Its magnetic moment direction is firmly pinned by the pinned layer, that is, it is fixed and generally exhibits in-plane or perpendicular magnetic anisotropy; (2) the barrier layer, which plays a key role in producing a significant tunneling magnetoresistance effect; (3) the free layer, which is made of ferromagnetic material. Its magnetic moment direction is variable and generally exhibits in-plane or perpendicular magnetic anisotropy. The principle of information storage is as follows: when the magnetic moment direction of the free layer is consistent with that of the reference layer, the resistance of the magnetic storage device is in a low resistance state, and when the magnetic moment direction of the free layer is opposite to that of the reference layer, the resistance of the magnetic storage device is in a high resistance state. The above two completely different resistance states are used to represent binary data "0" or "1" respectively.

[0003] The first generation of MRAM mainly uses an external magnetic field to induce the magnetic moment of the free layer to flip and complete the switching between high and low resistance states. MTJ often has in-plane magnetic anisotropy, but the storage density is severely limited due to the need to set up additional write bit lines to generate magnetic fields. The second generation of MRAM mainly uses spin transfer torque (STT) to drive the free magnetic moment to flip. The core storage device can choose in-plane or vertical MTJ. Compared with in-plane MTJ, the latter is expected to further reduce the energy consumption of MRAM while greatly improving storage density and reliability. The second generation of MRAM circuit design is simpler, and the preparation process is becoming more mature, gradually becoming the mainstream MRAM technology. At present, Samsung Foundry, Intel, GlobalFoundries, TSMC and other companies have developed a number of STT-MRAM and put them into mass production. In addition, they are also actively planning a new generation of MRAM products, using new writing methods to cause the magnetic moment of the free layer to flip, such as SOT-MRAM, VCMA-MRAM, etc. However, it is worth noting that the write power consumption of STT-MRAM is often much higher than the CMOS flip energy (1fJ), and even 2-3 orders of magnitude higher. It requires a larger MOS tube to provide drive current, which seriously hinders STT-MRAM from moving towards high integration and ultra-low power consumption. The key breakthrough to solve the above problem is how to reduce the write energy consumption of MTJ. Summary of the invention

[0004] In view of the above-mentioned write energy consumption problem, the present invention proposes two low-power non-volatile memory device structure design schemes and storage array arrangement designs, which are suitable for CMOS standard logic circuits, can effectively improve the write speed, reduce MTJ flip current density and write energy consumption, and improve MRAM storage density.

[0005] The present invention provides a low-power nonvolatile memory device, which sequentially arranges a buffer layer, a pinning layer, a reference layer, a barrier layer, a free layer, a covering layer and a hard mask layer on a substrate from bottom to top, and arranges a non-uniform magnetic moment inducing layer on the upper interface or the lower interface of the free layer.

[0006] Preferably, the non-uniform magnetic moment inducing layer is obtained by doping ferromagnetic particles on a non-magnetic film, or doping non-magnetic particles on a ferromagnetic film; the doping concentration is non-uniform and gradually increases or decreases along a certain direction on the film surface.

[0007] More preferably, the ratio of non-magnetic particles to ferromagnetic particles on one side can be 400% to 1000%; the ratio of non-magnetic particles to ferromagnetic particles on the other side can be 10% to 80%. The material of non-magnetic film or particles can be selected from one or more elements of Al, Cr, Mn, Cu, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Ir, Pt, Au, and the material of ferromagnetic film or ferromagnetic particles can be selected from one or more elements of Fe, Co, Ni, Ge, Tb, Pd, Te, Gd, Pt, B, Si.

[0008] Preferably, the film thickness of the non-uniform magnetic moment inducing layer is uniform and flat, and the range of the thickness can be selected between 0.2nm and 1.5nm. The smaller the roughness, the better, and at least less than 0.3nm.

[0009] Preferably, the free layer is composed of an upper ferromagnetic layer, a coupling insertion layer and a lower ferromagnetic layer; the magnetic moments of the upper ferromagnetic layer and the lower ferromagnetic layer have ferromagnetic coupling or antiferromagnetic coupling, and the easy axis directions of the two are near the perpendicular direction of the film surface; under the action of the perpendicular magnetic anisotropy field and the demagnetization field, the upper ferromagnetic layer or the lower ferromagnetic layer is domained.

[0010] The present invention also provides another low-power non-volatile memory device, in which a buffer layer, a pinning layer, a reference layer, a barrier layer, a free layer, a covering layer, and a hard mask layer are sequentially arranged on a substrate from bottom to top, and the free layer is composed of an upper ferromagnetic layer, a coupling insertion layer, and a lower ferromagnetic layer; the thickness of the upper ferromagnetic layer or the lower ferromagnetic layer is uneven, and grows in a wedge shape from thin to thick, and as the thickness increases, the perpendicular magnetic anisotropy decreases.

[0011] Preferably, the magnetic moments of the upper ferromagnetic layer and the lower ferromagnetic layer have ferromagnetic coupling or antiferromagnetic coupling, and the easy axis directions of the two are near the perpendicular direction of the film surface; under the action of the perpendicular magnetic anisotropy field and the demagnetization field, the upper ferromagnetic layer or the lower ferromagnetic layer is domained.

[0012] Preferably, the ferromagnetic layer material includes at least one or more elements selected from Co, Fe, Ni, Mn, Rh, Pd, Pt, Gd, Tb, Dy, Ho, Ga, Ge, B, Al, and Si. The coupling insertion layer material includes one or more elements selected from V, Cr, Cu, Nb, Mo, Ru, Rh, Hf, Ta, W, Re, and Ir.

[0013] Preferably, the device has a shape of a cylinder, an elliptical cylinder, a truncated cone, a quasi-truncated cone, a cube, a cuboid, a prism, a truncated pyramid, and a quasi-truncated pyramid.

[0014] Preferably, the barrier layer material can be selected from MgO, Al 2 O3 MgAlO x 、SiNO y 、TiO 2 , HfO 2 One of the oxide materials; artificially construct the antiferromagnetic structure of the reference layer and the pinning layer, the reference layer and the pinning layer can be composed of a single-layer ferromagnetic film or a multi-layer film, and the material can be selected from one or more elements of Co, Fe, Ni, Mn, Rh, Pt, Pd, B, Al, Si, V, Cr, Cu, Nb, Mo, Ru, Rh, Hf, Ta, W, Re, and Ir; the cover layer material can be selected from one or more elements of Ru, Pd, Hf, Ta, W, Ir, Pt, Au, and N; the hard mask layer material can be selected from Ta, W, N, Si, Ti and other materials.

[0015] The present invention also provides a storage array of MRAM composed of low-power non-volatile storage devices, which is arranged in a traditional or dense manner. The dense arrangement means that the storage units composed of the storage devices are arranged in a regular hexagon, and the rule is to place a certain storage unit at the center of the regular hexagon, and six storage units are placed at the six corners of the regular hexagon respectively, so as to improve the density of the storage array.

[0016] The present invention also provides a method for preparing a low-power non-volatile memory device, comprising the following steps:

[0017] A buffer layer, a pinning layer, a reference layer, a barrier layer, a free layer, a covering layer and a hard mask layer are prepared on a substrate according to conventional processes; a non-uniform magnetic moment inducing layer is prepared by adjusting a co-sputtering angle or a co-sputtering power.

[0018] The present invention also provides another method for preparing a low-power non-volatile memory device, comprising the following steps:

[0019] A buffer layer, a pinning layer, a reference layer, a barrier layer, a covering layer, and a hard mask layer are prepared on the substrate according to conventional processes; the free layer is obtained by adjusting the substrate movement speed and movement distance to obtain an upper ferromagnetic layer or a lower ferromagnetic layer with a film thickness gradient growth; and the covering layer is also planarized after preparation.

[0020] Beneficial Effects

[0021] The present invention proposes two low-power non-volatile memory device structure design schemes and storage array arrangement designs, which are suitable for CMOS standard logic circuits, can effectively improve the writing speed, reduce the MTJ flip current density and writing energy consumption, and improve the MRAM storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1It is a schematic diagram of the interlayer structure of the first low-power non-volatile memory device of the present invention.

[0023] Figure 2 A top view of the non-uniform magnetic moment induction layer of the first low-power non-volatile memory device of the present invention (taking a cylindrical device as an example).

[0024] Figure 3 The diagram is a schematic diagram of the easy axis of the magnetic moment of the free layer of the first low-power non-volatile memory device of the present invention.

[0025] Figure 4 This is a schematic diagram of the binary logic state of the first low-power non-volatile memory device of the present invention (taking the ferromagnetic coupling relationship between the magnetic moments of the upper ferromagnetic layer and the lower ferromagnetic layer as an example).

[0026] Figure 5 It is a schematic diagram of the interlayer structure of the second low-power non-volatile memory device of the present invention.

[0027] Figure 6 The diagram is a schematic diagram of the easy axis of the magnetic moment of the free layer of the second low-power non-volatile memory device of the present invention.

[0028] Figure 7 This is a schematic diagram of the binary logic state of the second low-power non-volatile memory device of the present invention (taking the ferromagnetic coupling relationship between the magnetic moments of the upper ferromagnetic layer and the lower ferromagnetic layer as an example).

[0029] Figure 8 ab are schematic diagrams of the storage array arrangement of the present invention.

[0030] Fig. 9 Schematic diagram of a storage unit of the present invention.

[0031] Fig.10 Schematic diagram of the storage array writing process of the present invention (taking the traditional arrangement as an example).

[0032] Fig.11 The figure is a schematic diagram of the preparation process of the first low-power non-volatile memory device of the present invention (taking the interface design of the non-uniform magnetic moment inducing layer on the free layer as an example).

[0033] Fig.12 The present invention is a schematic diagram of the preparation process of the second low-power non-volatile memory device. DETAILED DESCRIPTION

[0034] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0035] Example 1

[0036] This embodiment provides a low-power non-volatile memory device. Compared with the commonly used structure of a magnetic tunnel junction, an additional non-uniform magnetic moment inducing layer is sputtered on the upper interface or the lower interface of the free layer, and a buffer layer, a pinned layer, a reference layer, a barrier layer, a free layer, a non-uniform magnetic moment inducing layer, a cover layer, and a hard mask layer are sequentially arranged on the substrate from bottom to top, or a buffer layer, a pinned layer, a reference layer, a barrier layer, a non-uniform magnetic moment inducing layer, a free layer, a cover layer, and a hard mask layer are sequentially arranged on the substrate from bottom to top, such as Figure 1 The device has various shapes, including cylinder, elliptical cylinder, truncated cone, quasi-truncated cone, cube, cuboid, prism, truncated cone, quasi-truncated cone, etc. In this embodiment, a cylinder is taken as an example.

[0037] The non-uniform magnetic moment inducing layer is prepared by co-sputtering, and ferromagnetic particles can be doped on the non-magnetic film, or non-magnetic particles can be doped on the ferromagnetic film. The doping concentration is uneven and gradually increases or decreases along a certain direction on the film surface. Figure 2 As shown. The ratio of non-magnetic particles to ferromagnetic particles on one side can be selected from 400% to 1000%; the ratio of non-magnetic particles to ferromagnetic particles on the other side can be selected from 10% to 80%. The material of non-magnetic film or particles can be selected from one or more elements of Al, Cr, Mn, Cu, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Ir, Pt, Au, and the material of ferromagnetic film or ferromagnetic particles can be selected from one or more elements of Fe, Co, Ni, Ge, Tb, Pd, Te, Gd, Pt, B, Si. The film thickness of the non-uniform magnetic moment induction layer is uniform and flat, and its range can be selected from 0.2nm to 1.5nm. The smaller the roughness, the better, at least less than 0.3nm.

[0038] The free layer is composed of an upper ferromagnetic layer, a coupling insertion layer and a lower ferromagnetic layer. The magnetic moments of the upper ferromagnetic layer and the lower ferromagnetic layer are ferromagnetically coupled or antiferromagnetically coupled, and the easy axis directions of the two are near the vertical direction of the film surface. Under the action of the perpendicular magnetic anisotropy field and the demagnetization field, the upper ferromagnetic layer or the lower ferromagnetic layer in the free layer is domained. Among them, the easy axis direction of the magnetic moment of the ferromagnetic layer close to the non-uniform magnetic moment inducing layer is obviously affected by the non-uniform magnetic moment inducing layer, and gradually deviates from the vertical direction of the film surface. The angle gradually deflects from 0° to the maximum deflection angle (range: 20°~45°), which effectively reduces the difficulty of reversing the magnetic moment of the free layer, thereby reducing the reversal current density and increasing the reversal speed; while the easy axis direction of the magnetic moment of the ferromagnetic layer far away from the non-uniform magnetic moment inducing layer is almost not affected by the non-uniform magnetic moment inducing layer, and its easy axis is approximately parallel to the vertical direction of the film surface, and the angle between the two does not exceed 5°, such as Figure 3As shown. The material of the ferromagnetic layer in the free layer includes at least one or more elements of Co, Fe, Ni, Mn, Rh, Pd, Pt, Gd, Tb, Dy, Ho, Ga, Ge, B, Al, and Si. The material of the coupling insertion layer includes one or more elements of V, Cr, Cu, Nb, Mo, Ru, Rh, Hf, Ta, W, Re, and Ir. The film thicknesses of the upper ferromagnetic layer, the coupling insertion layer, and the lower ferromagnetic layer are uniform and flat. The film thickness of the upper ferromagnetic layer (0.4nm to 0.8nm) is slightly smaller than the film thickness of the lower ferromagnetic layer (0.9nm to 1.4nm). The film thickness range of the coupling insertion layer is: 0.2nm to 0.5nm. The smaller the roughness, the better, at least less than 0.4nm.

[0039] The information storage principle of the low-power non-volatile memory device provided in this embodiment is: according to the difference between the directions of the magnetic moments of the free layer and the reference layer, binary information is stored. When the magnetic moment of the free layer is approximately parallel to the magnetic moment of the reference layer, the resistance state is a low resistance state, and the binary data "0" can be stored; when the magnetic moment of the free layer is approximately antiparallel to the magnetic moment of the reference layer, the resistance state is a high resistance state, and the binary data "1" can be stored. Figure 4 As shown (only the non-uniform magnetic moment inducing layer, free layer, barrier layer and reference layer are shown).

[0040] Example 2

[0041] This embodiment provides a low-power non-volatile memory device, which is consistent with the common structure of a magnetic tunnel junction. A buffer layer, a pinned layer, a reference layer, a barrier layer, a free layer, a cap layer, and a hard mask layer are sequentially arranged on a substrate from bottom to top. The difference is that the thickness of the upper ferromagnetic layer or the lower ferromagnetic layer in the free layer is uneven, and grows in a wedge shape from thin to thick. As the thickness increases, the perpendicular magnetic anisotropy decreases, such as Figure 5 shown.

[0042] The free layer design is consistent with that of Example 1 - the free layer is also composed of an upper ferromagnetic layer, a coupling insertion layer and a lower ferromagnetic layer. The magnetic moments of the upper ferromagnetic layer and the lower ferromagnetic layer have ferromagnetic coupling or antiferromagnetic coupling, and the easy axis directions of the two are near the vertical direction of the film surface; and under the action of the perpendicular magnetic anisotropy field and the demagnetization field, the upper ferromagnetic layer or the lower ferromagnetic layer in the free layer is domained. Among them, as the thickness increases, the easy axis direction of the magnetic moment of the wedge-shaped upper ferromagnetic layer or the lower ferromagnetic layer gradually deviates from the vertical direction of the film surface, and the maximum deflection angle can be selected in the range of 20° to 60°, while the easy axis direction of the magnetic moment of the ferromagnetic layer with uniform thickness is near the vertical direction of the film surface, and the angle between the two does not exceed 5°, such as Figure 6As shown. The material selection of the ferromagnetic layer in the free layer is consistent with that of Scheme 1, and will not be repeated here. The thickness change rate of the wedge-shaped ferromagnetic layer film can be selected in the range of 50% to 300%, the starting film thickness of the upper ferromagnetic layer is about 0.3nm, and the starting film thickness of the lower ferromagnetic layer is about 0.6nm. In order to ensure the vertical magnetic anisotropy of the free layer as a whole, the thickness of the upper ferromagnetic layer generally does not exceed the thickness of the lower ferromagnetic layer (at the same horizontal position).

[0043] The information storage principle of the low-power non-volatile memory device provided in this embodiment is similar to that of Embodiment 1. Figure 7 shown.

[0044]

[0045] This embodiment provides a storage array of MRAM composed of low-power non-volatile storage devices of embodiment 1 or embodiment 2, and the arrangement is conventional or dense, such as Figure 8 As shown. Among them, the storage unit is as follows Fig. 9 As shown in Figure 1. According to the process preparation and design requirements, it is assumed that the minimum spacing allowed between each storage unit is d. For the traditional type, the spacing between a storage unit and the four storage units in front, behind, left, and right is d, and the spacing between the four storage units in the upper left corner, upper right corner, lower left corner, and lower right corner is d. For dense type, the distance between a storage unit and the six surrounding storage units is d, which is similar to placing a storage unit in the center of a regular hexagon with a side length of d, and placing the six storage units at the six corners of the regular hexagon. Therefore, the row spacing of the storage array is Compared with the traditional arrangement, it is shortened by 13.4%, improving the storage density of non-volatile memory and at the same time putting forward higher requirements for layout and wiring.

[0046] The process of writing information to the storage array: The address decoding circuit selects the word line corresponding to the address and powers on, so that the semiconductor device (MOSFET) set under the selected low-power non-volatile memory device is in the on state. When a moderate positive voltage is applied to the bit line (slightly larger than the absolute value of the flip voltage, ensuring that the error write rate does not exceed 10 -6 That is, excessive voltage will affect the life of the device, and even the device will be broken down). The polarization current can flow from top to bottom through the entire selected low-power non-volatile memory device, causing the resistance state of the device to change from a high-resistance state to a low-resistance state, completing the writing of the binary data "0"; while other semiconductor devices are in the off state, which is equivalent to an open circuit. Therefore, it can be regarded as no current flowing through other low-power non-volatile memory devices, such as Fig.10Similarly, the word line corresponding to the address is selected and powered on through the address decoding circuit, so that the semiconductor device (MOSFET) arranged below the selected low-power non-volatile memory device is in the on state. When a moderate positive voltage is applied to the source line or a moderate negative voltage is applied to the bit line, the polarization current can flow from bottom to top through the entire selected low-power non-volatile memory device, so that the device changes from a low-resistance state to a high-resistance state, completing the writing of the binary data "1".

[0047] Example 4

[0048] The preparation method of the storage array of Example 1: adopt CMOS standard logic process and integrate with MRAM back-end special process. Taking the interface design of the non-uniform magnetic moment inducing layer on the free layer as an example, the biggest difference from the conventional preparation process is the preparation of the non-uniform magnetic moment inducing layer. This layer is prepared by co-sputtering. One method is to adjust the co-sputtering angle so that the non-magnetic target material and the magnetic target material are sputtered to the substrate at different angles, and adjust the sputtering power of one of the targets during the sputtering process; another method is to set a slowly movable baffle above the non-magnetic target material or the magnetic target material, slowly block one of the targets during the sputtering process, and adjust the sputtering power of the unblocked target material during the sputtering process, and both methods can obtain a magnetic moment inducing layer with uneven composition.

[0049] like Fig.11 As shown, the method for preparing the storage array specifically includes:

[0050] S1. Magnetron sputtering deposition of conventional stacked films corresponding to storage devices (buffer layer, pinning layer, reference layer, barrier layer, free layer);

[0051] S2, depositing the unconventional stacked thin film (non-uniform magnetic moment inducing layer) corresponding to the memory device by co-sputtering;

[0052] S3, magnetron sputtering deposition of conventional stacked thin films (capping layer, hard mask layer) corresponding to the memory device;

[0053] S4, annealing;

[0054] S5, photolithography + etching to form storage devices + degumming and cleaning;

[0055] S6, insulation medium filling;

[0056] S7, flattening;

[0057] S8, opening a contact through hole;

[0058] S9, depositing thin films required for the bit lines;

[0059] S10, photolithography + etching to form bit lines + debonding and cleaning;

[0060] S11, passivation layer filling;

[0061] S12, photolithography + etching to form bit lines + de-resisting and cleaning.

[0062] Example 5

[0063] The preparation method of the storage array of Example 2: the CMOS standard logic process is used for process integration with the MRAM back-end special process. The biggest difference from the conventional preparation process is that the preparation of the wedge-shaped film in the free layer - during the sputtering process, the upper ferromagnetic layer or the lower ferromagnetic layer with a film thickness gradient growth is obtained by adjusting the substrate movement speed and movement distance, and an additional planarization step is required after the cover layer growth is completed.

[0064] like Fig.11 As shown, the method for preparing the storage array specifically includes:

[0065] S1. Magnetron sputtering deposition of conventional stacked films corresponding to storage devices (buffer layer, pinning layer, reference layer, barrier layer);

[0066] S2, unconventional stacked films corresponding to magnetron sputtering deposition memory devices (wedge-shaped films in the free layer: obtained by regulating the substrate movement speed and movement distance during the sputtering process);

[0067] S3, magnetron sputtering deposition of conventional stacked films corresponding to the memory device + planarization (covering layer);

[0068] S4, magnetron sputtering deposition of conventional stacked thin films (hard mask layer) corresponding to the memory device + annealing;

[0069] S5, photolithography + etching to form storage devices + degumming and cleaning;

[0070] S6, insulation medium filling;

[0071] S7, flattening;

[0072] S8, opening a contact through hole;

[0073] S9, depositing thin films required for the bit lines;

[0074] S10, photolithography + etching to form bit lines + debonding and cleaning;

[0075] S11, passivation layer filling;

[0076] S12, photolithography + etching to form bit lines + de-resisting and cleaning.

Claims

1. A low-power non-volatile memory device, comprising a buffer layer, a pinning layer, a reference layer, a barrier layer, a free layer, a cap layer, and a hard mask layer arranged on a substrate in order from bottom to top, characterized in that: A non-uniform magnetic moment inducing layer is arranged on the upper interface or the lower interface of the free layer.

2. The low-power non-volatile memory device according to claim 1, characterized in that: The non-uniform magnetic moment inducing layer is obtained by doping ferromagnetic particles on a non-magnetic film, or doping non-magnetic particles on a ferromagnetic film; the doping concentration is non-uniform and gradually increases or decreases along a certain direction on the film surface.

3. The low-power non-volatile memory device according to claim 1, characterized in that: The free layer is composed of an upper ferromagnetic layer, a coupling insertion layer and a lower ferromagnetic layer; the magnetic moments of the upper ferromagnetic layer and the lower ferromagnetic layer have ferromagnetic coupling or antiferromagnetic coupling, and the easy axis directions of the two are near the vertical direction of the film surface; under the action of the perpendicular magnetic anisotropy field and the demagnetization field, the upper ferromagnetic layer or the lower ferromagnetic layer is domained.

4. A low-power non-volatile memory device, wherein a buffer layer, a pinning layer, a reference layer, a barrier layer, a free layer, a cap layer, and a hard mask layer are sequentially arranged on a substrate from bottom to top, characterized in that: The free layer is composed of an upper ferromagnetic layer, a coupling insertion layer and a lower ferromagnetic layer; the thickness of the upper ferromagnetic layer or the lower ferromagnetic layer is uneven, growing from thin to thick in a wedge shape, and as the thickness increases, the perpendicular magnetic anisotropy decreases.

5. The low power non-volatile memory device according to claim 4, characterized in that: The magnetic moments of the upper ferromagnetic layer and the lower ferromagnetic layer have ferromagnetic coupling or antiferromagnetic coupling, and the easy axis directions of the two are near the vertical direction of the film surface; under the action of the perpendicular magnetic anisotropy field and the demagnetization field, the upper ferromagnetic layer or the lower ferromagnetic layer is domained.

6. The low-power non-volatile memory device according to claim 1 or 4, characterized in that: The device has a shape of a cylinder, an elliptical cylinder, a truncated cone, a quasi-truncated cone, a cube, a cuboid, a prism, a truncated pyramid, and a quasi-truncated pyramid.

7. A storage array of MRAM composed of the low-power non-volatile memory device according to claim 1 or 4, characterized in that: The arrangement is traditional or dense.

8. The storage array according to claim 7, characterized in that: The dense type means that the storage units formed by the storage device are arranged in a regular hexagon.

9. A method for preparing the low power non-volatile memory device according to claim 1, comprising the following steps: A buffer layer, a pinning layer, a reference layer, a barrier layer, a free layer, a covering layer and a hard mask layer are prepared on a substrate according to conventional processes; a non-uniform magnetic moment inducing layer is prepared by adjusting a co-sputtering angle or a co-sputtering power.

10. A method for preparing a low power non-volatile memory device as claimed in claim 4, comprising the following steps: A buffer layer, a pinning layer, a reference layer, a barrier layer, a covering layer, and a hard mask layer are prepared on the substrate according to conventional processes; the free layer is obtained by adjusting the substrate movement speed and movement distance to obtain an upper ferromagnetic layer or a lower ferromagnetic layer with a film thickness gradient growth; and the covering layer is also planarized after preparation.

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