Preparation method of positive and negative electrode coplanar photoelectric conversion semiconductor device and device thereof

Abstract

The invention discloses a preparation method of a positive and negative electrode coplanar photoelectric conversion semiconductor device and the device. The method comprises the following steps: depositing a tunneling oxide layer and an undoped intrinsic polycrystalline silicon layer on the back surface of a substrate in sequence; spraying a p + doping source and an n + doping source on the undoped intrinsic polycrystalline silicon layer by adopting a graphical screen printing process; the p + doping sources and the n + doping sources are sequentially arranged in a crossed manner; sE laser doping and diffusion processing are carried out, p + heavily doped polycrystalline silicon layers and n + heavily doped polycrystalline silicon layers which are arranged in a crossed mode are formed, and meanwhile a crystalline silicon glass layer containing a doping source is formed on the surface layer of the silicon wafer; carrying out slotting processing on adjacent positions of the p + heavily doped polycrystalline silicon layer and the n + heavily doped polycrystalline silicon layer so as to realize p-n isolation; removing the crystalline silicon glass layer, and performing double-sided texturing treatment; sequentially forming a passivation layer and an antireflection layer on the front and back surfaces of the silicon wafer; and carrying out silk-screen printing and sintering to form an electrode. The method can effectively shorten the production cycle, reduce the production cost and improve the production efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a preparation method of a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion and the device. Background Art

[0002] Solar cells are thin sheets of photovoltaic semiconductors that use sunlight to generate electricity directly. They are also called "solar chips" or "photovoltaic cells". They can directly convert light energy into electrical energy through the photoelectric effect or photochemical effect. At present, the implementation of solar cells is mainly based on crystalline silicon solar cells that work based on the photoelectric effect.

[0003] With the development of semiconductor photoelectric conversion technology, more and more new photoelectric conversion semiconductor technologies are being used in the field of solar cells. Among them, the positive and negative electrode photoelectric conversion semiconductor device places the p+ emitter, n+ back field region and silver grid line on the back of the device through the back patterning process, which can greatly improve the absorption rate of light on the front side.

[0004] However, the existing photoelectric conversion devices with positive and negative electrodes on the same surface mostly need to go through multiple masking, laser etching and cleaning processes during the production process, which greatly increases the production cost and production cycle, and is therefore not suitable for mass production. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion and the device thereof. The technical problem to be solved by the present invention is achieved by the following technical solution:

[0006] In a first aspect, the present invention provides a method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion, comprising:

[0007] S1: depositing a tunneling oxide layer and an undoped intrinsic polysilicon layer in sequence on the back side of the substrate;

[0008] S2: spraying a p+ doping source and an n+ doping source on the undoped intrinsic polysilicon layer by a patterned screen printing process; wherein the p+ doping source and the n+ doping source are arranged crosswise in sequence;

[0009] S3: Performing SE laser doping and diffusion treatment on the silicon wafer obtained in S2, so that the p+ doping source and the n+ doping source diffuse into the undoped intrinsic polysilicon layer to form a cross-arranged p+ heavily doped polysilicon layer and an n+ heavily doped polysilicon layer, and at the same time forming a crystalline silicon glass layer containing the doping source on the surface of the silicon wafer;

[0010] S4: Grooving the adjacent positions of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer to form an isolation groove to achieve pn isolation; wherein the isolation groove penetrates the tunnel oxide layer from the surface of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer inward until the back side of the substrate is exposed;

[0011] S5: removing the crystalline silicon glass layer containing the doping source from the silicon wafer obtained in S4, and performing double-sided texturing treatment;

[0012] S6: forming a passivation layer and an anti-reflection layer on the front and back sides of the silicon wafer obtained in S5 in sequence;

[0013] S7: Screen printing and sintering are performed on the back side of the silicon wafer obtained in S6 to form an electrode.

[0014] In one embodiment of the present invention, in step S1, the material of the substrate is n-type phosphorus-doped single crystal silicon; the material of the tunneling oxide layer is SiO2 with a thickness of 1 to 5 nm; and the thickness of the undoped intrinsic polysilicon layer is 300 to 500 nm.

[0015] In one embodiment of the present invention, in step S2, the p+ doping source is one or more elements of the III main group elements B, Al, Ga, In, Tl; the n+ doping source is one or more elements of the V main group elements N, P, As, Sb, Bi.

[0016] In one embodiment of the present invention, step S3 includes:

[0017] S31, using SE laser to perform laser doping on the silicon wafer obtained in S2, so that the atoms in the p+ doping source and the n+ doping source are pushed to the surface layer of the silicon wafer; wherein the laser doping uses a green nanosecond pulse laser with a wavelength of 532nm, and the laser power is between 20 and 80W;

[0018] S32, performing diffusion treatment on the laser-doped silicon wafer, so that atoms in the surface layer of the silicon wafer diffuse into the undoped intrinsic polysilicon layer, forming a cross-arranged p+ heavily doped polysilicon layer and an n+ heavily doped polysilicon layer, and at the same time forming a crystalline silicon glass layer containing a doping source on the surface layer of the silicon wafer;

[0019] The doping concentrations of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer are both between 1E15 / cm3 and 5E21 / cm3; the thickness of the crystalline silicon glass layer containing the doping source is 50 to 150 nm.

[0020] In one embodiment of the present invention, step S32 includes:

[0021] In a nitrogen and oxygen environment, the temperature is raised to 1000-1300°C and maintained for 3-5 hours to cause atoms in the p+ doping source and n+ doping source to diffuse into the undoped intrinsic polysilicon layer with a diffusion depth of 300-500nm, forming a cross-arranged p+ heavily doped polysilicon layer and n+ heavily doped polysilicon layer, and forming a crystalline silicon glass layer containing the doping source on the surface of the silicon wafer.

[0022] In one embodiment of the present invention, step S4 includes:

[0023] A green nanosecond pulse laser with a spot size of 150-300nm and a power of 30-100% is used to perform grooving on the adjacent positions of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer to form an isolation groove with a width of 40-50μm and a depth of 3-3.5μm.

[0024] In one embodiment of the present invention, step S5 includes:

[0025] S51, removing the crystalline silicon glass layer containing the doping source by using an acid pickling process;

[0026] S52, performing pyramid micro-suede treatment on the front side of the substrate and the back side of the substrate exposed at the bottom of the isolation groove by using a suede making process to form a regular suede structure.

[0027] In one embodiment of the present invention, in step S6, the material of the passivation layer is AlOx, with a thickness of 5-10 nm; the material of the anti-reflection layer is SiNx, with a thickness of 70-100 nm.

[0028] In one embodiment of the present invention, in step S7, the printing paste used in screen printing is one or more combinations of Ag, Cu, and Al.

[0029] In a second aspect, the present invention provides a semiconductor device for photoelectric conversion with positive and negative electrodes on the same surface, the device being manufactured by the preparation method provided by the first aspect of the present invention, comprising:

[0030] a substrate having a front side and a back side;

[0031] A tunnel oxide layer is disposed on the back side of the substrate;

[0032] The p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer are alternately arranged on the tunnel oxide layer, and the two layers have the same thickness;

[0033] An isolation groove is provided at the junction of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer to achieve pn isolation; wherein the isolation groove penetrates the tunnel oxide layer from the surface of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer inwardly until the back side of the substrate is exposed;

[0034] The stacked passivation layer and anti-reflection layer are arranged on the front side of the substrate, the surface of the p+ heavily doped polysilicon layer and the surface of the n+ heavily doped polysilicon layer;

[0035] The electrodes are arranged on the anti-reflection layer on the surface of the p+ heavily doped polysilicon layer and on the anti-reflection layer on the surface of the n+ heavily doped polysilicon layer.

[0036] Beneficial effects of the present invention:

[0037] The present invention provides a method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion. First, a tunneling oxide layer and an undoped intrinsic polysilicon layer are sequentially deposited on the back of a substrate; then a one-step graphic screen printing process is used to print a p+ doping source and an n+ doping source at corresponding doping positions, and after SE laser doping and high-temperature diffusion treatment, a p+ heavily doped polysilicon layer and an n+ heavily doped polysilicon layer are simultaneously formed. The method can effectively shorten the production cycle, reduce production costs, and improve production efficiency; it avoids the problems of long production cycle and high production costs caused by the need for multiple steps of covering masks, laser etching and cleaning in the prior art, and is helpful to realize the mass production of semiconductor devices with positive and negative electrodes on the same surface for photoelectric conversion.

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic structural diagram of a semiconductor device for photoelectric conversion with positive and negative electrodes on the same surface provided by an embodiment of the present invention;

[0040] Figure 2 It is a schematic flow chart of a method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion provided by an embodiment of the present invention;

[0041] Figure 3a-3g It is a schematic diagram of a process for preparing a semiconductor device for photoelectric conversion with positive and negative electrodes on the same surface provided by an embodiment of the present invention;

[0042] Description of reference numerals:

[0043] 101-substrate; 201-tunneling oxide layer; 202-undoped intrinsic polysilicon layer; 301-p+ doping source; 302-n+ doping source; 401-p+ heavily doped polysilicon layer; 402-n+ heavily doped polysilicon layer; 403-crystalline silicon glass layer containing doping source; 501-isolation groove; 601-passivation layer; 602-anti-reflection layer; 701-electrode. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In order to solve the problems of long production cycle and high production cost caused by the need for multiple steps of mask covering, laser etching and cleaning in the prior art, the present invention provides a method for preparing a positive and negative electrode co-planar photoelectric conversion semiconductor device and its device structure. The preparation method uses a one-step screen printing method to print p+ doping source and n+ doping source at corresponding doping positions, and then forms p+ heavily doped regions and n+ heavily doped regions through SE laser doping and high-temperature diffusion, which effectively improves production efficiency. The following will describe in detail a method for preparing a positive and negative electrode co-planar photoelectric conversion semiconductor device and its device structure provided by the present invention in conjunction with the accompanying drawings.

[0046] See also Figure 1 , Figure 1 1 is a schematic structural diagram of a positive and negative electrode co-surface photoelectric conversion semiconductor device provided by an embodiment of the present invention, the device mainly includes:

[0047] A substrate 101 having a front side and a back side;

[0048] A tunnel oxide layer 201 is disposed on the back side of the substrate 101;

[0049] The p+ heavily doped polysilicon layer 401 and the n+ heavily doped polysilicon layer 402 are alternately arranged on the tunnel oxide layer 201 and have the same thickness;

[0050] An isolation groove 501 is provided at the junction of the p+ heavily doped polysilicon layer 401 and the n+ heavily doped polysilicon layer 402 to achieve pn isolation; wherein the isolation groove 501 penetrates the tunnel oxide layer 201 from the surface of the p+ heavily doped polysilicon layer 401 and the n+ heavily doped polysilicon layer 402 inwardly until the back side of the substrate 101 is exposed;

[0051] The stacked passivation layer 601 and the anti-reflection layer 602 are arranged on the front surface of the substrate 101, the surface of the p+ heavily doped polysilicon layer 401 and the surface of the n+ heavily doped polysilicon layer 402;

[0052] The electrode 701 is disposed on the anti-reflection layer 602 on the surface of the p+ heavily doped polysilicon layer 401 and on the anti-reflection layer 602 on the surface of the n+ heavily doped polysilicon layer 402 .

[0053] It should be noted that the front side of the substrate 101 and the back side of the substrate 101 exposed at the bottom of the isolation groove 501 are also subjected to texturing treatment. The texturing treatment can improve the microstructure of the silicon wafer surface, increase the surface area, reduce surface defects and impurities, and thus improve the photoelectric conversion efficiency of the battery.

[0054] The following is a detailed description of the method for preparing the positive and negative electrodes on the same surface photoelectric conversion semiconductor device.

[0055] See also Figure 2 and Figure 3a-3g , Figure 2 1 is a schematic flow chart of a method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion provided by an embodiment of the present invention. Figure 3a-3g The present invention provides a schematic diagram of a process for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion. The preparation method mainly includes the following steps:

[0056] S1: a tunneling oxide layer 201 and an undoped intrinsic polysilicon layer 202 are sequentially deposited on the back side of the substrate 101 .

[0057] First, n-type phosphorus-doped single crystal silicon is selected as a substrate, and polishing and cleaning processes are performed. Any side of the processed substrate 101 is defined as the back side, and the other side is defined as the front side of the substrate.

[0058] Then, any one of the process technologies such as electron beam evaporation, magnetron sputtering, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) can be selected to sequentially deposit an ultra-thin tunnel oxide layer 201 and an undoped intrinsic polysilicon layer 202 on the back of the substrate 101. The material of the tunnel oxide layer 201 is SiO2, with a thickness of 1 to 5 nm; the thickness of the undoped intrinsic polysilicon layer 202 is 300 to 500 nm.

[0059] After S1 treatment, the silicon wafer obtained is as follows Figure 3a shown.

[0060] S2: spraying p+ doping source 301 and n+ doping source 302 on the undoped intrinsic polysilicon layer 202 by patterned screen printing process; wherein the p+ doping source 301 and the n+ doping source 302 are arranged crosswise in sequence.

[0061] Optionally, in this embodiment, the p+ doping source 301 may be one or more elements of the III-group elements B, Al, Ga, In, and Tl; the n+ doping source 302 may be one or more elements of the V-group elements N, P, As, Sb, and Bi.

[0062] The specific implementation process of the graphic screen printing process can refer to the existing related technologies.

[0063] After S2 treatment, the silicon wafer obtained is as follows Figure 3b shown.

[0064] S3: The silicon wafer obtained in S2 is subjected to SE laser doping and high-temperature diffusion treatment so that the p+ doping source 301 and the n+ doping source 302 diffuse into the undoped intrinsic polysilicon layer 202 to form a cross-arranged p+ heavily doped polysilicon layer 401 and n+ heavily doped polysilicon layer 402, and at the same time, a crystalline silicon glass layer 403 containing the doping source is formed on the surface of the silicon wafer.

[0065] S31. Use SE laser to laser dope the silicon wafer obtained in S2, so as to push the atoms in the p+ doping source 301 and the n+ doping source 302 to the surface of the silicon wafer; wherein the laser doping uses a green nanosecond pulse laser with a wavelength of 532nm, and the laser power is between 20 and 80W.

[0066] S32. The laser-doped silicon wafer is further diffused at high temperature to diffuse the atoms in the surface layer of the silicon wafer into the undoped intrinsic polysilicon layer 202, forming a cross-arranged p+ heavily doped polysilicon layer 401 and an n+ heavily doped polysilicon layer 402, and at the same time forming a crystalline silicon glass layer 403 containing a doping source on the surface of the silicon wafer.

[0067] Specifically, the temperature is raised to 1000-1300°C in a nitrogen and oxygen environment and maintained for 3-5 hours, causing atoms in the p+ doping source 301 and the n+ doping source 302 to diffuse into the undoped intrinsic polysilicon layer 202 with a diffusion depth of 300-500nm, forming a cross-arranged p+ heavily doped polysilicon layer 401 and n+ heavily doped polysilicon layer 402, and forming a crystalline silicon glass layer 403 containing the doping source on the surface of the silicon wafer.

[0068] In this embodiment, the doping concentrations of the formed p+ heavily doped polysilicon layer 401 and the n+ heavily doped polysilicon layer 402 are both between 1E15 / cm3 and 5E21 / cm3; the thickness of the crystalline silicon glass layer 403 containing the doping source is 50 to 150 nm.

[0069] After S3 treatment, the silicon wafer obtained is as follows Figure 3c shown.

[0070] In this embodiment, the p+ doping source and the n+ doping source can be printed at the corresponding doping positions at the same time through the graphic screen printing process. After SE laser doping and high-temperature diffusion treatment, the p+ heavily doped area and the n+ heavily doped area are formed at the same time, avoiding the multiple use of covering masks, laser etching and cleaning process steps, reducing production costs and improving production efficiency.

[0071] S4: Grooving is performed on the adjacent positions of the p+ heavily doped polysilicon layer 401 and the n+ heavily doped polysilicon layer 402 to form an isolation groove 501 to achieve pn isolation; wherein the isolation groove 501 penetrates the tunnel oxide layer 201 inward from the surface of the p+ heavily doped polysilicon layer 401 and the n+ heavily doped polysilicon layer 402 until the back side of the substrate 101 is exposed.

[0072] Optionally, as an implementation method, this embodiment can use a green nanosecond pulse laser with a spot size of 150 to 300 nm and a power of 30 to 100% to perform groove processing on the adjacent positions of the p+ heavily doped polysilicon layer 401 and the n+ heavily doped polysilicon layer 402 to form an isolation groove 501 with a width of 40 to 50 μm and a depth of 3 to 3.5 μm.

[0073] After S4 treatment, the silicon wafer obtained is as follows Figure 3d shown.

[0074] In this embodiment, by making grooves at the positions where the p+ heavily doped polysilicon layer 401 and the n+ heavily doped polysilicon layer 402 are adjacent to each other, short circuits between adjacent positive and negative electrodes can be prevented, thereby achieving pn isolation.

[0075] S5: removing the crystalline silicon glass layer 403 containing the doping source from the silicon wafer obtained in S4, and performing double-sided texturing treatment.

[0076] S51, removing the crystalline silicon glass layer 403 containing the doping source by an acid pickling process;

[0077] S52 , using a texturing process, respectively perform pyramid micro-texture processing on the front side of the substrate 101 and the back side of the substrate 101 exposed at the bottom of the isolation groove 501 to form a regular suede structure.

[0078] Among them, the detailed implementation process and parameter setting of the pickling process and the texturing process can be achieved by referring to the existing relevant technologies.

[0079] After S4 treatment, the silicon wafer obtained is as follows Figure 3e shown.

[0080] The main purpose of texturing the silicon wafer in this embodiment is to increase the silicon wafer's absorption of light and reduce surface reflection, thereby improving the conversion efficiency of solar cells. By forming an undulating velvet surface on the silicon wafer surface, the absorption of sunlight is increased, and at the same time, the mechanical damage layer and impurities on the silicon wafer surface are removed, thereby improving the performance of the battery.

[0081] S6: forming a passivation layer 601 and an anti-reflection layer 602 in sequence on the front and back sides of the silicon wafer obtained in S5.

[0082] Optionally, in this embodiment, the material of the passivation layer 601 may be AlOx, with a thickness of 5 to 10 nm; the material of the anti-reflection layer 602 may be SiNx, with a thickness of 70 to 100 nm.

[0083] The manufacturing process of the passivation layer 601 and the anti-reflection layer 602 may adopt an existing conventional process, such as an ALD method or a PEALD method.

[0084] After S6 treatment, the silicon wafer obtained is as follows Figure 3f shown.

[0085] S7: Screen printing and sintering are performed on the back side of the silicon wafer obtained in S6 to form an electrode 701.

[0086] As an implementation manner, the printing paste used in the screen printing in this embodiment can be one or a combination of Ag, Cu, and Al.

[0087] At this point, the preparation of the positive and negative electrodes on the same side of the photoelectric conversion semiconductor device has been completed. The obtained device is as follows Figure 3g shown.

[0088] It can be understood that the corresponding electrode on the p+ heavily doped polysilicon layer 401 can be used as a positive electrode, and the corresponding electrode on the n+ heavily doped polysilicon layer 402 can be used as a negative electrode.

[0089] The present invention provides a method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion. First, a tunneling oxide layer and an undoped intrinsic polysilicon layer are sequentially deposited on the back of a substrate; then a one-step graphic screen printing process is used to print a p+ doping source and an n+ doping source at corresponding doping positions, and after SE laser doping and high-temperature diffusion treatment, a p+ heavily doped polysilicon layer and an n+ heavily doped polysilicon layer are simultaneously formed. The method can effectively shorten the production cycle, reduce production costs, and improve production efficiency; it avoids the problems of long production cycle and high production costs caused by the need for multiple steps of covering masks, laser etching and cleaning in the prior art, and is helpful to realize the mass production of semiconductor devices with positive and negative electrodes on the same surface for photoelectric conversion.

[0090] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0091] In addition, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes the first feature being directly below and obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0092] In the description of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0093] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion, characterized in that: include: S1: depositing a tunneling oxide layer and an undoped intrinsic polysilicon layer in sequence on the back side of the substrate; S2: spraying a p+ doping source and an n+ doping source on the undoped intrinsic polysilicon layer using a patterned screen printing process; wherein the p+ doping source and the n+ doping source are arranged crosswise in sequence; S3: performing SE laser doping and diffusion treatment on the silicon wafer obtained in S2, so that the p+ doping source and the n+ doping source diffuse into the undoped intrinsic polysilicon layer to form a cross-arranged p+ heavily doped polysilicon layer and an n+ heavily doped polysilicon layer, and at the same time forming a crystalline silicon glass layer containing the doping source on the surface of the silicon wafer; S4: Grooving the adjacent positions of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer to form an isolation groove to achieve pn isolation; wherein the isolation groove penetrates the tunneling oxide layer inward from the surface of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer until the back side of the substrate is exposed; S5: removing the crystalline silicon glass layer containing the doping source from the silicon wafer obtained in S4, and performing double-sided texturing treatment; S6: forming a passivation layer and an anti-reflection layer on the front and back sides of the silicon wafer obtained in S5 in sequence; S7: Screen printing and sintering are performed on the back side of the silicon wafer obtained in S6 to form an electrode.

2. The method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion according to claim 1, characterized in that: In step S1, The material of the substrate is n-type phosphorus-doped single crystal silicon; The material of the tunnel oxide layer is SiO2, and the thickness is 1 to 5 nm; The thickness of the undoped intrinsic polysilicon layer is 300-500 nm.

3. The method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion according to claim 1, characterized in that: In step S2, the p+ doping source is one or more elements of the group III elements B, Al, Ga, In, and Tl; the n+ doping source is one or more elements of the group V elements N, P, As, Sb, and Bi.

4. The method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion according to claim 1, characterized in that: Step S3 includes: S31, using SE laser to perform laser doping on the silicon wafer obtained in S2, so that the atoms in the p+ doping source and the n+ doping source are pushed to the surface layer of the silicon wafer; wherein the laser doping uses a green nanosecond pulse laser with a wavelength of 532nm, and the laser power is between 20 and 80W; S32, performing diffusion treatment on the laser-doped silicon wafer, so that atoms in the surface layer of the silicon wafer diffuse into the undoped intrinsic polysilicon layer, forming a cross-arranged p+ heavily doped polysilicon layer and an n+ heavily doped polysilicon layer, and at the same time forming a crystalline silicon glass layer containing a doping source on the surface layer of the silicon wafer; The doping concentrations of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer are both between 1E15 / cm3 and 5E21 / cm3; and the thickness of the crystalline silicon glass layer containing the doping source is 50 to 150 nm.

5. The method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion according to claim 4, characterized in that: Step S32 includes: In a nitrogen and oxygen environment, the temperature is raised to 1000-1300°C and maintained for 3-5 hours to cause the atoms in the p+ doping source and the n+ doping source to diffuse into the undoped intrinsic polysilicon layer with a diffusion depth of 300-500nm, forming a cross-arranged p+ heavily doped polysilicon layer and an n+ heavily doped polysilicon layer, and forming a crystalline silicon glass layer containing the doping source on the surface of the silicon wafer.

6. The method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion according to claim 1, characterized in that: Step S4 includes: A green nanosecond pulse laser with a spot size of 150-300nm and a power of 30-100% is used to perform grooving on the adjacent positions of the p+ heavily doped polysilicon layer and the n+ heavily doped polysilicon layer to form an isolation groove with a width of 40-50μm and a depth of 3-3.5μm.

7. The method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion according to claim 1, characterized in that: Step S5 includes: S51, removing the crystalline silicon glass layer containing the doping source by an acid pickling process; S52, performing pyramid micro-texture treatment on the front side of the substrate and the back side of the substrate exposed at the bottom of the isolation groove respectively by using a texturing process to form a regular suede structure.

8. The method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion according to claim 1, characterized in that: In step S6, the material of the passivation layer is AlOx, and the thickness is 5-10 nm; the material of the anti-reflection layer is SiNx, and the thickness is 70-100 nm.

9. The method for preparing a semiconductor device with positive and negative electrodes on the same surface for photoelectric conversion according to claim 1, characterized in that: In step S7, the printing paste used in screen printing is one or more combinations of Ag, Cu, and Al.

10. A photoelectric conversion semiconductor device with positive and negative electrodes on the same surface manufactured by the manufacturing method according to any one of claims 1 to 9, characterized in that: The positive and negative electrodes on the same side of the photoelectric conversion semiconductor device comprises: A substrate (101) having a front side and a back side; A tunneling oxide layer (201) is arranged on the back side of the substrate (101); A p+ heavily doped polysilicon layer (401) and an n+ heavily doped polysilicon layer (402) are alternately arranged on the tunneling oxide layer (201), and both have the same thickness; An isolation groove (501) is arranged at the junction of the p+ heavily doped polysilicon layer (401) and the n+ heavily doped polysilicon layer (402) to achieve pn isolation; wherein the isolation groove penetrates the tunneling oxide layer inward from the surface of the p+ heavily doped polysilicon layer (401) and the n+ heavily doped polysilicon layer (402) until the back side of the substrate is exposed; A stacked passivation layer (601) and an anti-reflection layer (602) are arranged on the front surface of the substrate (101), the surface of the p+ heavily doped polysilicon layer (401), and the surface of the n+ heavily doped polysilicon layer (402); The electrode (701) is arranged on the anti-reflection layer (602) on the surface of the p+ heavily doped polysilicon layer (401) and on the anti-reflection layer (602) on the surface of the n+ heavily doped polysilicon layer (402).

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