In-memory multiplication circuit and module of SRAM (Static Random Access Memory), SRAM and electronic equipment

Abstract

The invention relates to an in-memory multiplication circuit and module of an SRAM (Static Random Access Memory), the SRAM and electronic equipment, the in-memory multiplication circuit comprises a storage part and a weighting part, the storage part comprises eight storage units, each storage unit is provided with an analog quantity input end and an analog quantity output end and is used for storing a single bit weight, and the weighting part is used for weighting the analog quantity input end and the analog quantity output end. The analog input end and the analog output end of each storage unit are conducted when the single bit weight stored in the storage unit is 1, and the analog input end and the analog output end of each storage unit are disconnected when the single bit weight stored in the storage unit is 0; the weighting part comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor. The number and the total capacitance value of the adopted capacitors are smaller, the area overhead of the circuit is reduced, and the problem that the area overhead of an existing in-memory multiplication circuit of the SRAM based on the charge domain is large is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an in-memory multiplication operation circuit and module of an SRAM, an SRAM, and an electronic device. Background Art

[0002] In-memory computing technology breaks through the "storage wall" problem of the traditional von Neumann architecture. Its core advantage is that it can perform computing operations directly inside the memory. This innovation reduces the transmission bottleneck between storage and computing units, improves computing efficiency, and brings new development opportunities to fields such as artificial intelligence and visual recognition. With the advancement of technology, in-memory computing has developed rapidly in related applications, and the scientific research community has also increasingly higher requirements for its performance.

[0003] For high-precision analog weighted in-memory multiplication calculations, the current in-memory multiplication circuit based on charge domain SRAM (static random access memory) still needs to rely on a large number of capacitor combinations to implement, which greatly increases the circuit area overhead. Summary of the invention

[0004] The present invention provides an SRAM in-memory multiplication operation circuit and module, SRAM and electronic equipment to solve the problem of large area overhead of the current SRAM in-memory multiplication operation circuit based on charge domain.

[0005] In a first aspect, the present invention provides an in-memory multiplication circuit of an SRAM, comprising: A storage part, comprising eight storage units, each of which has an analog input terminal and an analog output terminal and is used to store a single-bit weight, each of which turns on the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 1, and turns off the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 0, and the analog input terminals of the eight storage units are connected to the same analog input line; a weighted portion, comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor; Among them, the analog output ends of the eight storage units are respectively connected to the first plates of the first capacitor to the eighth capacitor, the second plates of the first capacitor and the second capacitor are connected to the first plate of the ninth capacitor, the second plates of the third capacitor and the fourth capacitor are connected to the second plate of the ninth capacitor, the second plates of the fifth capacitor and the sixth capacitor are connected to the first plate of the tenth capacitor, the second plates of the seventh capacitor and the eighth capacitor are connected to the second plate of the tenth capacitor, the second plate of the ninth capacitor is also connected to the first plate of the eleventh capacitor, and the second plate of the tenth capacitor is also connected to the second plate of the eleventh capacitor and constitutes the output node of the in-memory multiplication circuit of the SRAM.

[0006] In a second aspect, the present invention provides an in-memory computing circuit, comprising: A multiplication circuit, which is the in-memory multiplication circuit of the SRAM described in the first aspect; The accumulation circuit is used to accumulate the weighted multiplication calculation results of the multiplication circuit on multiple analog quantities respectively.

[0007] In a third aspect, the present invention provides an SRAM in-memory multiplication operation module, which encapsulates the SRAM in-memory multiplication operation circuit described in the first aspect and has: A first pin connected to the analog quantity input line, used for receiving the analog quantity to be calculated by weighted multiplication; The second pin connected to the output node of the in-memory multiplication circuit of the SRAM is used to output the weighted multiplication calculation result of the analog quantity.

[0008] In a fourth aspect, the present invention provides a static random access memory (SRAM), which implements weighted in-memory multiplication calculation of analog quantities through the in-memory multiplication operation circuit of the SRAM described in the first aspect.

[0009] In a fifth aspect, the present invention provides an electronic device, comprising a memory and a processor, wherein the memory is the static random access memory described in the fourth aspect.

[0010] Compared with the related art, the SRAM in-memory multiplication circuit provided by the present invention can realize the multiplication calculation of analog quantity and eight-bit weight. More importantly, the structure of the weighted part in the circuit is relatively simple, and only 11 capacitors are used to implement it. Compared with the existing in-memory multiplication circuit, the number and total capacitance of the capacitors used are both less, which reduces the circuit area overhead and solves the problem of large area overhead of the current charge domain-based SRAM in-memory multiplication circuit.

[0011] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Schematic diagram of an in-memory multiplication circuit of an SRAM provided in an embodiment of the present invention; Figure 2 is a schematic diagram of a storage unit provided in one embodiment of the present invention; Figure 3 Schematic diagram of an in-memory multiplication operation module of an SRAM provided in an embodiment of the present invention; Figure 4 This is a simulation diagram of input and output signals of the in-memory multiplication circuit of the SRAM in the first example performing multiplication calculation of an analog signal and an eight-bit digital signal; Figure 5 This is a simulation diagram of input and output signals for the in-memory multiplication circuit of the SRAM in the second example performing multiplication calculations of analog signals and eight-bit digital signals. DETAILED DESCRIPTION

[0013] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0014] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0015] In an embodiment of the present invention, a multiplication circuit in a SRAM is provided. Figure 1 Schematic diagram of an in-memory multiplication circuit of an SRAM provided in an embodiment of the present invention.

[0016] like Figure 1 As shown, the in-memory multiplication circuit includes a storage part and a weighting part.

[0017] The storage part includes eight storage units, each of which has an analog input terminal and an analog output terminal and is used to store a single-bit weight. Each storage unit turns on the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 1, and turns off the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 0. The analog input terminals of the eight storage units are connected to the same analog input line VIN.

[0018] It should be noted that the storage unit may adopt a currently relatively mature storage unit. Figure 2 is a schematic diagram of a storage unit provided in one embodiment of the present invention. Figure 2Each storage unit may include a storage subunit and a transmission unit. The storage subunit has a first storage node Q and a second storage node QB. The transmission unit includes a first NMOS tube N1, a second NMOS tube N2 and a first PMOS tube P1. The drain of the first NMOS tube N1 and the source of the first PMOS tube P1 are connected to form an analog input terminal. The source of the first NMOS tube N1, the drain of the first PMOS tube P1 and the drain of the second NMOS tube N2 are connected to form an analog output terminal. The gate of the first NMOS tube N1 is connected to the first storage node Q, the gate of the first PMOS tube P1 is connected to the second storage node QB, the gate of the second NMOS tube N2 is connected to the second storage node QB, and the source of the second NMOS tube N2 is grounded to VSS. In the storage subunit, the first storage node Q is high and the second storage node QB is low, indicating that the stored single-bit weight is 1, and the first storage node Q is low and the second storage node QB is high, indicating that the stored single-bit weight is 0.

[0019] In the above transmission unit, the first NMOS tube N1 and the first PMOS tube P1 constitute a transmission gate, and the second NMOS tube N2 is used as a switching device. When the single-bit weight stored in the storage subunit is 1, the first storage node Q is high and the second storage node QB is low, then the transmission gate is turned on and the second NMOS tube N2 is turned off, then the potential of the analog output terminal and the analog input terminal is the same, that is, the analog signal VIN received by the analog input terminal is transmitted to the analog output terminal. At this time, the corresponding upper plate of the capacitor is charged to the analog potential VIN, realizing the multiplication operation of 1*VIN=VIN of the single bit. When the single-bit weight stored in the storage subunit is 0, the first storage node Q is low and the second storage node QB is high, then the transmission gate is turned off and the second NMOS tube N2 is turned on, then the analog output terminal is grounded, and the corresponding potential is 0, that is, the analog signal VIN received by the analog input terminal is not transmitted to the analog output terminal. At this time, the corresponding upper plate of the capacitor cannot be charged and the potential is 0, thereby completing the single-bit multiplication operation of 0*VIN=0.

[0020] Among them, the storage subunit includes a third NMOS tube N3, a fourth NMOS tube N4, a first inverter I1 and a second inverter I2. The first inverter I1 and the second inverter I2 are cross-coupled to form a first storage node Q and a second storage node QB. The source and drain of the third NMOS tube N3 are respectively connected to the first storage node Q and the first bit line BL, the source and drain of the fourth NMOS tube N4 are respectively connected to the second storage node QB and the second bit line BLB, and the gates of the third NMOS tube N3 and the fourth NMOS tube N4 are both connected to the word line WL.

[0021] Since each inverter is composed of two devices, the storage unit used in this embodiment is a 9T-SRAM unit (9T-cell). Accordingly, in other embodiments, the storage unit can adopt other structures, and it is only necessary for the storage unit to turn on the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 1, and to turn off the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 0.

[0022] The weighted part includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10 and an eleventh capacitor C11. The analog output terminals of the eight storage units are respectively connected to the first plates of the first capacitor C1 to the eighth capacitor C8, the second plates of the first capacitor C1 and the second capacitor C2 are connected to the first plate of the ninth capacitor C9, the second plates of the third capacitor C3 and the fourth capacitor C4 are connected to the second plate of the ninth capacitor C9, the second plates of the fifth capacitor C5 and the sixth capacitor C6 are connected to the first plate of the tenth capacitor C10, the second plates of the seventh capacitor C7 and the eighth capacitor C8 are connected to the second plate of the tenth capacitor C10, the second plate of the ninth capacitor C9 is also connected to the first plate of the eleventh capacitor C11, and the second plate of the tenth capacitor C10 is also connected to the second plate of the eleventh capacitor C11 and constitutes an output node VOUT of the in-memory multiplication circuit of the SRAM.

[0023] The single-bit weights stored in the eight storage units constitute eight-bit weights in reverse order. For example, the eight storage units can be defined as the first storage unit to the eighth storage unit, the first storage unit is connected to the first capacitor C1, the second storage unit is connected to the second capacitor C2, and so on, the eighth storage unit is connected to the eighth capacitor C8. Then the first storage unit to the eighth storage unit store the low-order weights to the high-order weights of the eight-bit weights in sequence.

[0024] The capacitance of the first capacitor C1, the third capacitor C3, the fifth capacitor C5, the seventh capacitor C7, the ninth capacitor C9 and the tenth capacitor C10 are the same, the capacitance of the second capacitor C2, the fourth capacitor C4, the sixth capacitor C6 and the eighth capacitor C8 is twice that of the first capacitor C1, and the capacitance of the eleventh capacitor C11 is one quarter of that of the first capacitor C1. Assuming that the capacitance of the first capacitor C1, the third capacitor C3, the fifth capacitor C5, the seventh capacitor C7, the ninth capacitor C9 and the tenth capacitor C10 is C, the capacitance of the second capacitor C2, the fourth capacitor C4, the sixth capacitor C6 and the eighth capacitor C8 is 2C, and the capacitance of the eleventh capacitor C11 is 1 / 4C.

[0025] For the above-mentioned in-memory multiplication circuit, each storage unit in the same row shares the same word line WL. When the potential of the analog input line VIN is always 0 and the potential of the word line is 1, the in-memory multiplication circuit is in a read-write mode, and data reading and writing are realized through the first bit line BL and the second bit line BLB. When the potential of the analog input line VIN is not always 0 and the potential of the word line WL is 0, the in-memory multiplication circuit is in a calculation mode.

[0026] For the first capacitor C1 to the eighth capacitor C8 in the calculation mode, the relationship between the upper plate potential of each capacitor and the output node potential of the in-memory multiplication circuit is described as follows.

[0027] When the upper plate potential of the eighth capacitor C8 is the analog value VIN and the upper plate potentials of other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the eighth capacitor C8 is 1, and the single-bit weight stored in other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0028] The derivation process is: when the upper plate potential of the eighth capacitor C8 is the analog value VIN, the value of VOUT is equal to the voltage divider value of the capacitance value of C8 relative to the total capacitance at the VOUT output point. Therefore, in the numerator, 2C represents the capacitance value of C8; in the denominator, 15C / 64 represents the equivalent capacitance value of C1, C2, C3, C4, C9, and C11 at the VOUT output point, 3C / 4 represents the equivalent capacitance value of C5, C6, and C10 at the VOUT output point, C represents the capacitance value of C7, and 2C represents the capacitance value of C8.

[0029] When the upper plate potential of the seventh capacitor C7 is the analog value VIN and the upper plate potentials of other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the seventh capacitor C7 is 1, and the single-bit weight stored in other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0030] The derivation process is: when the upper plate potential of the seventh capacitor C7 is the analog value VIN, the value of VOUT is equal to the voltage divider value of the capacitance value of C7 relative to the total capacitance at the VOUT output point. Therefore, in the numerator of the above formula, C represents the capacitance value of C7; in the denominator, 15C / 64 represents the equivalent capacitance value of C1, C2, C3, C4, C9, and C11 at the VOUT output point, 3C / 4 represents the equivalent capacitance value of C5, C6, and C10 at the VOUT output point, C represents the capacitance value of C7, and 2C represents the capacitance value of C8.

[0031] When the upper plate potential of the sixth capacitor C6 is the analog value VIN and the upper plate potentials of other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the sixth capacitor C6 is 1, and the single-bit weight stored in other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0032] The derivation process is: when the upper plate potential of the sixth capacitor C6 is the analog value VIN, first find the voltage value output by the lower plate of C6. For the first part:

[0033] In the numerator, 2C represents the capacitance value of C6; in the denominator, represents the equivalent capacitance value of C1, C2, C3, C4, C7, C8, C9, C10, and C11 at the lower plate point of C6, C represents the capacitance value of C5, and 2C represents the capacitance value of C6. Therefore, the first part represents the voltage value output by the lower plate of C6 when the upper plate potential of the sixth capacitor C6 is the analog value VIN, that is, the input to the left plate of C10.

[0034] Then, this is equivalent to inputting to the left plate of C10:

[0035] The value of VOUT is equal to the voltage divided by the capacitance of C10 relative to the total capacitance at the VOUT output point. So, for the second part In the numerator, C represents the capacitance value of C10; in the denominator, 15C / 64 represents the equivalent capacitance value of C1, C2, C3, C4, C9, and C11 at the VOUT output point, 2C represents the capacitance value of C8, and the two Cs represent the capacitance values ​​of C7 and C10 respectively.

[0036] When the upper plate potential of the fifth capacitor C5 is the analog value VIN and the upper plate potentials of other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the fifth capacitor C5 is 1, and the single-bit weight stored in other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0037] The derivation process is: when the upper plate potential of the fifth capacitor C5 is the analog value VIN, first find the voltage value output by the lower plate of C5. For the first part:

[0038] In the numerator, C represents the capacitance value of C5; in the denominator, represents the equivalent capacitance value of C1, C2, C3, C4, C7, C8, C9, C10, and C11 at the lower plate point of C5, C represents the capacitance value of C5, and 2C represents the capacitance value of C6. Therefore, the first part represents the voltage value output by the lower plate of C5 when the upper plate potential of the fifth capacitor C5 is the analog value VIN, that is, the input to the left plate of C10.

[0039] Then, this is equivalent to inputting to the left plate of C10:

[0040] The value of VOUT is equal to the voltage divided by the capacitance of C10 relative to the total capacitance at the VOUT output point. So, for the second part In the numerator, C represents the capacitance value of C10; in the denominator, 15C / 64 represents the equivalent capacitance value of C1, C2, C3, C4, C9, and C11 at the VOUT output point, 2C represents the capacitance value of C8, and the two Cs represent the capacitance values ​​of C7 and C10 respectively.

[0041] When the upper plate potential of the fourth capacitor C4 is the analog value VIN and the upper plate potentials of other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the fourth capacitor C4 is 1, and the single-bit weight stored in other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0042] The derivation process is as follows: when the upper plate potential of the fourth capacitor C4 is the analog value VIN, first find the voltage value output by the lower plate of C4. In the numerator, 2C represents the capacitance value of C4; in the denominator, 15C / 64 represents the equivalent capacitance value of C5, C6, C7, C8, C10, and C11 at the lower plate point of C4, 3C / 4 represents the equivalent capacitance value of C1, C2, and C9 at the lower plate point of C4, C represents the capacitance value of C3, and 2C represents the capacitance value of C4. So, It represents the voltage value output by the lower plate of C4 when the upper plate potential of the fourth capacitor C4 is the analog value VIN, that is, the voltage input to the left plate of C11 .

[0043] Then, this is equivalent to inputting the left plate of C11 , the value of VOUT is equal to the voltage divided by the capacitance of C11 relative to the total capacitance at the VOUT output point. So, for the second part In the numerator, C / 4 represents the capacitance value of C11; in the denominator, 15C / 4 represents the equivalent capacitance value of C5, C6, C7, C8, and C10 at the VOUT output point, and C / 4 represents the capacitance value of C11.

[0044] When the upper plate potential of the third capacitor C3 is the analog value VIN and the upper plate potentials of other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the third capacitor C3 is 1, and the single-bit weight stored in other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0045] The derivation process is as follows: when the upper plate potential of the third capacitor C3 is the analog value VIN, first find the voltage value output by the lower plate of C3. In the numerator, C represents the capacitance value of C3; in the denominator, 15C / 64 represents the equivalent capacitance value of C5, C6, C7, C8, C10, and C11 at the lower plate point of C3, 3C / 4 represents the equivalent capacitance value of C1, C2, and C9 at the lower plate point of C3, C represents the capacitance value of C3, and 2C represents the capacitance value of C4. So, It represents the voltage value output by the lower plate of C3 when the upper plate potential of the third capacitor C3 is the analog value VIN, that is, the voltage input to the left plate of C11 .

[0046] Then, this is equivalent to inputting the left plate of C11 , the value of VOUT is equal to the voltage divided by the capacitance of C11 relative to the total capacitance at the VOUT output point. So, for the second part In the numerator, C / 4 represents the capacitance value of C11; in the denominator, 15C / 4 represents the equivalent capacitance value of C5, C6, C7, C8, and C10 at the VOUT output point, and C / 4 represents the capacitance value of C11.

[0047] When the upper plate potential of the second capacitor C2 is the analog value VIN and the upper plate potentials of other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the second capacitor C2 is 1, and the single-bit weight stored in other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0048] The derivation process is: when the upper plate potential of the second capacitor C2 is the analog value VIN, first find the voltage value output by the lower plate of C2. For the first part:

[0049] In the numerator, 2C represents the capacitance value of C2; in the denominator, represents the equivalent capacitance value of C3, C4, C5, C6, C7, C8, C9, C10, and C11 at the lower plate point of C2, C represents the capacitance value of C1, and 2C represents the capacitance value of C2. Therefore, the first part represents the voltage value output by the lower plate of C2 when the upper plate potential of the second capacitor C2 is the analog value VIN, that is, the input to the left plate of C9.

[0050] Then, this is equivalent to inputting to the left plate of C9:

[0051] The output voltage value of the right plate of C9 is equal to the voltage divided by the capacitance value of C9 relative to the total capacitance value at the right plate point of C9. So, for the second part In the numerator, C represents the capacitance value of C9; in the denominator, 15C / 64 represents the equivalent capacitance value of C5, C6, C7, C8, C10, and C11 at the right plate point of C9, 2C represents the capacitance value of C4, and the two Cs represent the capacitance values ​​of C3 and C9 respectively. Therefore, the multiplication of the first part and the second part represents the voltage value output by the right plate of C9, that is, the input to the left plate of C11.

[0052] Finally, this is equivalent to inputting to the left plate of C11:

[0053] The value of VOUT is equal to the voltage divided by the capacitance of C11 relative to the total capacitance at the VOUT output point. So, for the third part In the numerator, C / 4 represents the capacitance value of C11; in the denominator, 15C / 4 represents the equivalent capacitance value of C5, C6, C7, C8, and C10 at the VOUT output point, and C / 4 represents the capacitance value of C11.

[0054] When the upper plate potential of the first capacitor C1 is the analog value VIN and the upper plate potentials of other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the first capacitor C1 is 1, and the single-bit weight stored in other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0055] The derivation process is: when the potential of the upper plate of the first capacitor C1 is the analog value VIN, first find the voltage value output by the lower plate of C1. For the first part:

[0056] In the numerator, C represents the capacitance value of C1; in the denominator, represents the equivalent capacitance value of C3, C4, C5, C6, C7, C8, C9, C10, and C11 at the lower plate point of C1, C represents the capacitance value of C1, and 2C represents the capacitance value of C2. Therefore, the first part represents the voltage value output by the lower plate of C1 when the upper plate potential of the first capacitor C1 is the analog value VIN, that is, the input to the left plate of C9.

[0057] Then, this is equivalent to inputting to the left plate of C9:

[0058] The output voltage value of the right plate of C9 is equal to the voltage divided by the capacitance value of C9 relative to the total capacitance value at the right plate point of C9. So, for the second part In the numerator, C represents the capacitance value of C9; in the denominator, 15C / 64 represents the equivalent capacitance value of C5, C6, C7, C8, C10, and C11 at the right plate point of C9, 2C represents the capacitance value of C4, and the two Cs represent the capacitance values ​​of C3 and C9 respectively. Therefore, the multiplication of the first part and the second part represents the voltage value output by the right plate of C9, that is, the input to the left plate of C11.

[0059] Finally, this is equivalent to inputting to the left plate of C11:

[0060] The value of VOUT is equal to the voltage divided by the capacitance of C11 relative to the total capacitance at the VOUT output point. So, for the third part In the numerator, C / 4 represents the capacitance value of C11; in the denominator, 15C / 4 represents the equivalent capacitance value of C5, C6, C7, C8, and C10 at the VOUT output point, and C / 4 represents the capacitance value of C11.

[0061] The above illustrates the output potential corresponding to each single-bit weight being 1. It can be seen that the weight ratio of each bit of data in the eight-bit weight is 128:64:32:16:8:4:2:1, that is, the single-bit weight stored in the storage unit connected to the eighth capacitor C8 constitutes the highest bit of the eight-bit weight, and so on. The single-bit weight stored in the storage unit connected to the first capacitor C1 constitutes the lowest bit of the eight-bit weight. Therefore, the multiplication operation of the analog quantity VIN and the eight-bit weight can be realized. The multiplication result is the sum of the output potentials corresponding to the single-bit weights of 1 in the eight-bit weight. For example, when the eight-bit weight is 11000000, the weights stored in the storage units corresponding to the eighth capacitor C8 and the seventh capacitor C7 are 1, and the weights stored in the other storage units are 0, then at this time:

[0062] The output VOUT of the in-memory multiplication circuit of the SRAM is the weighted multiplication calculation result of the analog quantity.

[0063] The calculation accuracy of the in-memory multiplication circuit of the SRAM in the above embodiment is verified by some experimental data as follows.

[0064] Reference Figure 4 , which is a simulation diagram of the input and output signals of the in-memory multiplication circuit of the SRAM in the first example for multiplication calculation of analog signals and eight-bit digital signals. The input analog signal is 900mv, and the eight-bit weight changes with a period of 2ns. Before the analog signal is input or when the stored weight data is changed, the circuit has been over-discharged to reduce errors.

[0065] When it is 0~2ns, the 8-bit digital weight is 111111111, the in-memory calculation result is 878.8mv, the ideal result is 900mv, and the difference is 21.2mv.

[0066] When it is 2~4ns, the 8-bit digital weight is 10101010, the in-memory calculation result is 582.3mv, the ideal result is 597.6mv, and the difference is 15.3mv.

[0067] When it is 4~6ns, the 8-bit digital weight is 10000000, the in-memory calculation result is 438.1mv, the ideal result is 450mv, and the difference is 11.9mv.

[0068] Reference Figure 5 , which is a simulation diagram of the input and output signals of the in-memory multiplication circuit of the SRAM in the second example for multiplication calculation of analog signals and eight-bit digital signals. The input analog signal is 500mv, and the eight-bit weight changes with a period of 2ns. Before the analog signal is input or when the stored weight data is changed, the circuit has been over-discharged to reduce errors.

[0069] When it is 0~2ns, the 8-bit digital weight is 111111111, the in-memory calculation result is 482.7mv, the ideal result is 500mv, and the difference is 17.3mv.

[0070] When it is 2~4ns, the 8-bit digital weight is 10101010, the in-memory calculation result is 318.5mv, the ideal result is 332.1mv, and the difference is 13.6mv.

[0071] When it is 4~6ns, the 8-bit digital weight is 10000000, the in-memory calculation result is 239.4mv, the ideal result is 250mv, and the difference is 10.6mv.

[0072] From the above experimental results, it can be seen that the error between the in-memory calculation result and the ideal result is within the allowable range.

[0073] Therefore, the in-memory multiplication circuit of the SRAM provided by the present invention can realize the multiplication calculation of the analog quantity and the eight-bit weight. More importantly, the structure of the weighted part in the circuit is relatively simple, and only 11 capacitors are used to implement it. Compared with the existing in-memory multiplication circuit, the number of capacitors used is less. In addition, the total capacitance value is 14.25 unit capacitors. When the unit capacitance values ​​are the same, the total capacitance value used is less. Fewer capacitors and less total capacitance values ​​both reduce the circuit area overhead, solving the problem of large area overhead of the in-memory multiplication circuit of the current charge domain-based SRAM.

[0074] In an embodiment of the present invention, there is also provided an in-memory calculation circuit, which includes a multiplication circuit and an accumulation circuit. The multiplication circuit is an in-memory multiplication circuit of the SRAM provided by the present invention; the accumulation circuit is used to accumulate the weighted multiplication calculation results of multiple analog quantities respectively by the multiplication circuit, thereby comprehensively realizing the weighted accumulation calculation.

[0075] Reference Figure 3 In an embodiment of the present invention, there is also provided an in-memory multiplication operation module of an SRAM, which encapsulates the in-memory multiplication operation circuit of the SRAM provided by the present invention and has: The first pin VIN connected to the analog quantity input line is used to receive the analog quantity to be weighted multiplied; the second pin VOUT connected to the output node of the in-memory multiplication circuit of the SRAM is used to output the weighted multiplication result of the analog quantity; the third pin WL connected to the word line is used to receive the word line signal; the fourth pin VSS connected to the source of the second NMOS tube is used to connect to the external ground terminal; the eight fifth pins BL connected to the eight first bit lines respectively are used to transmit the first bit line signal; the eight sixth pins BLB connected to the eight second bit lines respectively are used to transmit the second bit line signal; the eight seventh pins Q connected to the eight first storage nodes respectively are used to observe the first storage signal; the eight eighth pins QB connected to the eight second storage nodes respectively are used to observe the second storage signal.

[0076] Preferably, the in-memory multiplication operation module may also encapsulate a discharge tube for discharging the in-memory multiplication operation circuit, and the in-memory multiplication operation module may also have a ninth pin discharge connected to the discharge tube. By discharging, the calculation of the in-memory multiplication operation circuit can be made more accurate. Correspondingly, a tenth pin VDD connected to an external power supply may also be configured.

[0077] In an embodiment of the present invention, a static random access memory (SRAM) is also provided, which has the SRAM in-memory multiplication operation circuit provided by the present invention built in, and the weighted in-memory multiplication calculation of analog quantity is realized by the SRAM in-memory multiplication operation circuit provided by the present invention.

[0078] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory is the static random access memory provided by the present invention.

[0079] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0080] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

Claims

1. An in-memory multiplication circuit of an SRAM, characterized in that: include: A storage part, comprising eight storage units, each storage unit having an analog input terminal and an analog output terminal and being used to store a single-bit weight, each storage unit turning on the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 1 and turning off the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 0, and the analog input terminals of the eight storage units are connected to the same analog input line; a weighted portion, comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor; Among them, the analog output ends of the eight storage units are respectively connected to the first plates of the first capacitor to the eighth capacitor, the second plates of the first capacitor and the second capacitor are connected to the first plate of the ninth capacitor, the second plates of the third capacitor and the fourth capacitor are connected to the second plate of the ninth capacitor, the second plates of the fifth capacitor and the sixth capacitor are connected to the first plate of the tenth capacitor, the second plates of the seventh capacitor and the eighth capacitor are connected to the second plate of the tenth capacitor, the second plate of the ninth capacitor is also connected to the first plate of the eleventh capacitor, and the second plate of the tenth capacitor is also connected to the second plate of the eleventh capacitor and constitutes the output node of the in-memory multiplication circuit of the SRAM.

2. The in-memory multiplication circuit of the SRAM according to claim 1, characterized in that: The single-bit weights stored in the eight storage units constitute eight-bit weights in reverse order; The capacitance of the first capacitor, the third capacitor, the fifth capacitor, the seventh capacitor, the ninth capacitor and the tenth capacitor are the same, the capacitance of the second capacitor, the fourth capacitor, the sixth capacitor and the eighth capacitor are twice that of the first capacitor, and the capacitance of the eleventh capacitor is one quarter of that of the first capacitor.

3. The in-memory multiplication circuit of the SRAM according to claim 1, characterized in that: Each storage unit includes a storage subunit and a transmission unit, the storage subunit has a first storage node and a second storage node, the transmission unit includes a first NMOS tube, a second NMOS tube and a first PMOS tube, the drain of the first NMOS tube and the source of the first PMOS tube are connected to form an analog input terminal, the source of the first NMOS tube, the drain of the first PMOS tube and the drain of the second NMOS tube are connected to form an analog output terminal, the gate of the first NMOS tube is connected to the first storage node, the gate of the first PMOS tube is connected to the second storage node, the gate of the second NMOS tube is connected to the second storage node, and the source of the second NMOS tube is grounded.

4. The in-memory multiplication circuit of the SRAM according to claim 3, characterized in that: In the storage subunit, the first storage node is at a high level and the second storage node is at a low level, indicating that the stored single-bit weight is 1; the second storage node is at a low level and the second storage node is at a high level, indicating that the stored single-bit weight is 0.

5. The in-memory multiplication circuit of the SRAM according to claim 3, characterized in that: The storage subunit includes a third NMOS tube, a fourth NMOS tube, a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled to form a first storage node and a second storage node. The source and the drain of the third NMOS tube are respectively connected to the first storage node and the first bit line. The source and the drain of the fourth NMOS tube are respectively connected to the second storage node and the second bit line. The gates of the third NMOS tube and the fourth NMOS tube are both connected to the word line.

6. An in-memory computing circuit, characterized in that: include; A multiplication circuit, which is an in-memory multiplication circuit of the SRAM according to any one of claims 1 to 5; The accumulation circuit is used to accumulate the weighted multiplication calculation results of multiple analog quantities respectively performed by the multiplication circuit.

7. An in-memory multiplication operation module of SRAM, characterized in that: An in-memory multiplication circuit encapsulated with the SRAM according to any one of claims 1 to 5 and having: A first pin connected to the analog quantity input line, used for receiving the analog quantity to be calculated by weighted multiplication; The second pin connected to the output node of the in-memory multiplication circuit of the SRAM is used to output the weighted multiplication calculation result of the analog quantity.

8. The in-memory multiplication operation module of the SRAM according to claim 7, characterized in that: When the packaged device is the SRAM in-memory multiplication circuit of claim 5, it also has: A third pin connected to the word line, used to receive a word line signal; A fourth pin connected to the source of the second NMOS tube and used to connect to an external ground terminal; Eight fifth pins connected to the eight first bit lines respectively, for transmitting first bit line signals; Eight sixth pins respectively connected to the eight second bit lines, and used for transmitting second bit line signals; Eight seventh pins connected to the eight first storage nodes respectively, and used for observing the first storage signal; Eight eighth pins respectively connected to the eight second storage nodes are used to observe the second storage signal.

9. A SRAM, characterized in that: The weighted in-memory multiplication calculation of analog quantities is realized by the in-memory multiplication operation circuit of the SRAM described in any one of claims 1-5.

10. An electronic device comprising a memory and a processor, characterized in that: The memory is the SRAM according to claim 9.

Images