Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate which is internally provided with a plurality of first grooves which are arranged at intervals; forming a conductive layer, wherein the first groove is filled with the conductive layer and the conductive layer covers the surface of the substrate; forming mask layers arranged at intervals on the surface of the conductive layer, wherein the mask layers and the first grooves are partially overlapped; the conductive layer is preprocessed, the preprocessing comprises the steps that the mask layer serves as a mask, the conductive layer is patterned, a second groove is formed, and the side wall of the conductive layer is exposed through the second groove; forming a barrier film on the side wall surface; an etching process is carried out on the conductive layer to form a third groove from the upper end of the conductive layer, and in the etching process, the etching rate of the conductive layer covered with the barrier film is smaller than the etching rate of the conductive layer not covered with the barrier film; and forming a conductive column, wherein the third groove is filled with the conductive column. The semiconductor structure and the preparation method thereof provided by the embodiment of the invention are at least beneficial to reducing the contact resistance between the conductive plug and the conductive layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the continuous development of integrated circuit process technology, in order to improve the integration of integrated circuits, while increasing the operating speed of memory and reducing its power consumption, for example, the characteristic size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices continues to shrink, and MOSFET devices face a series of challenges.

[0003] The reduction of feature size brings about an increase in integration, but at the same time, it will cause problems in the contact performance between the lower electrode of the transistor and the contact window, and between the contact plug and the conductive layer. For example, due to the requirement of the storage area of ​​the transistor, in the vertical direction, the ratio of the height and width of the lower electrode is relatively large. In the process of forming the capacitor hole for accommodating the lower electrode, due to the etching effect of the aspect ratio, it may be impossible to etch through, that is, the bottom of the capacitor hole does not expose the contact window or the area of ​​the bottom of the capacitor hole is relatively small, and thus the needs of the device cannot be met. How to improve the contact performance between the lower electrode and the contact window, and between the conductive plug and the conductive layer, has become an important problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial for reducing the contact resistance between a conductive plug and a conductive layer in the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate, wherein the substrate has a plurality of first grooves arranged at intervals; forming a conductive layer, wherein the conductive layer fills the first grooves and covers the surface of the substrate; forming a mask layer arranged at intervals on the surface of the conductive layer, wherein the mask layer partially overlaps with the first grooves; pre-treating the conductive layer, wherein the pre-treating comprises: using the mask layer as a mask, patterning the conductive layer and forming a second groove, wherein the side wall of the conductive layer is exposed through the second groove; forming a barrier film on the side wall surface; performing an etching process on the conductive layer to form a third groove from the upper end of the conductive layer, wherein in the etching process, the etching rate of the conductive layer covered with the barrier film is lower than the etching rate of the conductive layer not covered with the barrier film; forming a conductive column, wherein the conductive column fills the third groove.

[0006] In some embodiments, the pretreatment process steps include: providing a first source gas and a second source gas, the first source gas is used to etch the conductive layer, and the second source gas is used to form a barrier film; removing a portion of the thickness of the conductive layer not covered by the mask layer to form a second groove, and forming a continuous barrier film on the surface of the conductive layer exposed by the inner wall surface of the second groove and the bottom of the second groove.

[0007] In some embodiments, the second source gas is also used to remove the mask layer, and an etching selection ratio of the second source gas to the mask layer is less than or equal to a thickness of the mask layer.

[0008] In some embodiments, the second source gas includes monofluoromethane and oxygen, and a flow rate of the monofluoromethane is greater than a flow rate of the oxygen.

[0009] In some embodiments, the substrate includes an array region and a peripheral region, and the conductive layer is located in the array region and / or the peripheral region.

[0010] In some embodiments, before forming the conductive pillar, the method further includes: removing the barrier film.

[0011] In some embodiments, the barrier film is removed by using a cleaning gas, wherein the cleaning gas includes any one of NF3, O2, Ar or CF4 or a combination of multiple thereof.

[0012] According to some embodiments of the present disclosure, on the other hand, a semiconductor structure is provided, comprising: a substrate having a contact window therein, the contact window protruding from the surface of the substrate; and conductive columns, part of the conductive columns being located in the contact window and part of the conductive columns being located on the surface of the contact window.

[0013] In some embodiments, the conductive column includes a continuous first conductive column and a second conductive column, the first conductive column is located in the contact window, and the second conductive column is located on the surface of the contact window; along the direction from the second conductive column to the first conductive column, the line width of the first conductive column decreases.

[0014] In some embodiments, a cross-sectional shape of the first conductive pillar along a direction perpendicular to the surface of the substrate includes: a U-shape or a V-shape.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] In the technical solution provided by the embodiment of the present disclosure, the conductive layer is pre-treated to form a barrier film on the inner wall surface of the second groove, and in the subsequent etching process, the etching rate of the conductive layer covered with the barrier film is less than the etching rate of the conductive layer not covered with the barrier film. In this way, only one step of etching the conductive layer to form a third groove can be added to change the contact area between the conductive column and the conductive layer. Compared with the conventional process of forming a mask and patterning the third groove, the process steps and preparation costs can be reduced, thereby saving process cycles and improving the process rate. In addition, the barrier film covers the side of the conductive layer, and the barrier film can protect the outer side of the conductive layer so that the morphology of the conductive layer is only complete. The formed third groove can increase the contact area between the conductive column and the contact window, thereby reducing the contact resistance between the conductive column and the conductive layer, thereby improving the electrical performance of the semiconductor structure, reducing electrical losses, and improving the response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0019] Figure 2 to Figure 8 A schematic flow chart of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0020] Figures 9 to 16 A schematic flow chart of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0021] Fig.17 A structural block diagram of a terminal provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] As known from the background art, the contact resistance between the conductive plug and the conductive layer of the current semiconductor structure is relatively large.

[0023] The disclosed embodiment provides a method for preparing a semiconductor structure, wherein a barrier film is formed on the inner wall surface of the second groove by pre-treating the conductive layer, and in the subsequent etching process, the etching rate of the conductive layer covered with the barrier film is less than the etching rate of the conductive layer not covered with the barrier film, so that only one step of etching the conductive layer to form a third groove can be added to change the contact area between the conductive column and the conductive layer. Compared with the conventional process of forming a mask and patterning the third groove, the process steps and preparation costs can be reduced, thereby saving process cycles and improving the process rate. In addition, the barrier film covers the side of the conductive layer, so the barrier film can protect the outer side of the conductive layer so that the morphology of the conductive layer is only complete, and the formed third groove can increase the contact area between the conductive column and the contact window, thereby reducing the contact resistance between the conductive column and the conductive layer, thereby improving the electrical performance of the semiconductor structure, reducing electrical losses, and improving the response speed.

[0024] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0025] Figure 1 A process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0026] refer to Figure 1 According to some embodiments of the present disclosure, the present disclosure provides a method for preparing a semiconductor structure, including:

[0027] S10, providing a substrate, wherein the substrate has a plurality of first grooves arranged at intervals.

[0028] In some embodiments, the semiconductor structure can be a memory. The substrate includes an array area and a peripheral area. The array area is the core area of ​​the memory, which is used to store data; the peripheral area is the control area of ​​the memory, which is used to control the writing and reading of data in the array area. The array area includes a storage capacitor and a switch tube, wherein the storage capacitor is used to store data; the switch tube in the array area is used to control the input and output of data in the storage capacitor. The peripheral area also includes a switch tube, which is used to form a control circuit to realize the control of writing and reading data in the array area.

[0029] S20, forming a conductive layer, wherein the conductive layer fills the first groove and covers the surface of the substrate.

[0030] In some embodiments, the conductive layer is located in the array region (eg Figure 2 to Figure 8The semiconductor structure shown in FIG. 1 is a semiconductor structure in which the conductive layer serves as a capacitor window, and the conductive column formed subsequently serves as a lower electrode of the capacitor structure.

[0031] In some embodiments, the conductive layer is located in the peripheral region (eg Figures 9 to 16 The semiconductor structure shown in FIG. 1 ) is a semiconductor structure in which the conductive layer and the conductive pillar serve as contact plugs. The contact plugs may be any one of a source contact plug, a drain contact plug or a gate contact plug.

[0032] S30, forming mask layers arranged at intervals on the surface of the conductive layer, wherein the mask layers partially overlap with the first grooves.

[0033] S40, pre-processing the conductive layer, the pre-processing comprising: using the mask layer as a mask, patterning the conductive layer and forming a second groove, wherein the side wall of the conductive layer is exposed through the second groove; and forming a barrier film on the side wall surface.

[0034] S50, performing an etching process on the conductive layer to form a third groove from the upper end of the conductive layer, wherein in the etching process, the etching rate of the conductive layer covered with the barrier film is lower than the etching rate of the conductive layer not covered with the barrier film.

[0035] S50 , forming a conductive column, wherein the conductive column fills the third groove.

[0036] The following will be combined Figure 2 to Figure 8 The preparation method of the conductive layer array region provided in the above embodiment is described in detail with respect to each step corresponding to the array region.

[0037] Figure 2 to Figure 8 A schematic flow chart of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure.

[0038] refer to Figure 2 , providing a substrate 10, wherein the substrate 10 has a plurality of first grooves 106 arranged at intervals.

[0039] In some embodiments, the base 10 may include a stacked substrate 100 and an isolation layer 102 , and the first groove 106 is located in the isolation layer 102 .

[0040] In some embodiments, the substrate 100 may be a semiconductor material, and the semiconductor material includes silicon, silicon germanium, or germanium. The substrate has a P-type doping element or an N-type doping element. The N-type doping element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type doping element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0041] In some embodiments, the material of the isolation layer 102 may be silicon oxide, silicon nitride, silicon carbonitride or other materials with high dielectric constants. Exemplarily, the material of the isolation layer 102 is silicon nitride, which not only has high dielectric properties, but also has high hardness, thereby ensuring that the bit line 108 and the capacitor plug 104 located in the isolation layer 102 are less likely to deform their profiles, which is beneficial to improving the yield of the semiconductor structure. In some embodiments, the isolation layer 102 may be a multi-layer stacked film layer, and the material of the film layer may be any two or more of silicon oxide, silicon nitride, silicon carbonitride or other materials with high dielectric constants.

[0042] In some embodiments, the substrate 10 further includes: an active layer 101, the active layer 101 being located between the substrate 100 and the isolation layer 102. The active layer 101 may include a channel region and a first source and drain region and a second source and drain region located at both ends of the channel region. The bit line 108 and the capacitor plug 104 are electrically connected to the first source and drain region or the second source and drain region of the active layer 101, respectively. For example, the bit line 108 is electrically connected to the first source and drain region, and the capacitor plug 104 is electrically connected to the second source and drain region of the active layer 101.

[0043] In some embodiments, the active layer 101 and the substrate 100 can be prepared from the same original substrate. Part of the thickness of the original substrate is patterned to form an active layer 101 arranged at intervals, and the remaining original substrate serves as the substrate 100. There is no interface state between the active layer 101 and the substrate 100. Instead, the active layer 101 and the substrate 100 are two different film layers divided due to different definitions of different functional limited areas. The two are actually the same film layer.

[0044] In some embodiments, an isolation structure 105 is included between adjacent active layers 101, and the isolation structure 105 is used to divide and isolate the spaced active layers 101, so as to define transistors one by one in the subsequent process, and select the specified transistor through the bit line and word line to write data and read data. The isolation structure 105 can be a shallow trench isolation structure (STI).

[0045] In some embodiments, the isolation structure 105 is an isolation structure formed of an isolation material, and the isolation structure 105 can be a single-layer film layer or a multi-layer film layer.

[0046] In some embodiments, the semiconductor structure includes a bit line 108 and a word line. The material of the bit line 108 includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride, which is beneficial to reduce the resistance of the bit line 108 itself. The word line is located in the isolation structure 105 on one side of the channel region. The material of the word line includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0047] In some embodiments, one end of the bit line 108 away from the substrate 100 has a barrier layer 109 , and the barrier layer 109 is used to isolate the bit line 108 from the capacitor structure. The material of the barrier layer 109 may be silicon nitride or silicon nitride oxide.

[0048] In some embodiments, the substrate 10 further includes: a capacitor plug 104, the capacitor plug 104 is located in the isolation layer 102, and the capacitor plug 104 is electrically connected to the active layer 101. The capacitor plug 104 can be a metal silicide layer or a polysilicon layer. The metal silicide layer can reduce the contact resistance between the capacitor contact plug and the active layer 101.

[0049] In some embodiments, the bottom of the first groove 106 exposes the capacitor plug 104 , and the first groove 106 is used to form a capacitor contact plug.

[0050] refer to Figure 3 , forming a conductive layer 110, the conductive layer 110 fills the first groove 106 (refer to Figure 2 ) and covers the surface of the isolation layer 102.

[0051] In some embodiments, the material of the conductive layer 110 may include at least one of tungsten, tantalum, tungsten nitride, or tantalum nitride.

[0052] Continue to refer Figure 3 , a mask layer 103 arranged at intervals is formed on the surface of the conductive layer 110, and the mask layer 103 and the first groove 106 (reference Figure 2 ) partially overlap.

[0053] In some embodiments, the mask layer 103 may be a photoresist, or any material whose etching rate is different from that of the conductive layer 110 and the barrier layer under the same etching process. For example, the material of the mask layer 103 is carbon.

[0054] In some embodiments, the mask layer 103 has an opening 107, and a portion of the opening 107 is aligned with the first groove 106 (see Figure 2 ) overlaps, and also overlaps with part of the blocking layer 109, so that the original square arrangement of the standard cone can be transformed into a hexagonal closest arrangement, thereby increasing the storage area and reducing the difficulty of the preparation process within a limited space, thereby accurately controlling the distance between each capacitor hole and ensuring that the yield of the capacitor hole is high based on the capacitor hole with a high aspect ratio.

[0055] refer to Figure 4 , the conductive layer 110 is pre-treated, the pre-treatment comprising: using the mask layer 103 as a mask, patterning the conductive layer 110 and forming a second groove 116, wherein the side wall of the conductive layer 110 is exposed through the second groove 116; and forming a barrier film 115 on the side wall surface.

[0056] In some embodiments, the pretreatment process steps include: providing a first source gas and a second source gas, the first source gas is used to etch the conductive layer 110, and the second source gas is used to form a blocking film 115; removing a portion of the thickness of the conductive layer 110 not covered by the mask layer 103 to form a second groove 116, and forming a continuous blocking film 115 on the surface of the conductive layer 110 exposed by the inner wall surface of the second groove 116 and the bottom of the second groove 116.

[0057] It is understandable that the second groove 116 does not completely penetrate the conductive layer 110 , thereby increasing the contact area between the conductive layer 110 and the capacitor plug 104 , thereby reducing the contact resistance between the conductive layer 110 and the capacitor plug 104 .

[0058] In some embodiments, during the pre-treatment process, not only the conductive layer 110 is etched, but also a portion of the barrier layer 109 is etched.

[0059] In some embodiments, the first source gas includes chlorine gas. The conductive layer 110 is removed by chlorine gas, and the etching rate is relatively high, so that the second groove 116 can be formed quickly.

[0060] In some embodiments, the second source gas is also used to remove the mask layer 103, and the etching selectivity ratio of the second source gas to the mask layer 103 is less than or equal to the thickness of the mask layer 103. In this way, during the process of forming the second groove 116, the mask layer 103 always exists, and after the second groove 116 is formed, the mask layer 103 still exists or is just completely etched, so that the blocking film 115 will not be formed on the surface of the conductive layer 110 covered by the mask layer 103, and the third groove can be formed later by the different etching rates of the uncovered conductive layer 110 and the covered conductive layer 110, thereby increasing the contact area between the capacitor contact window and the lower electrode.

[0061] In addition, during the process of forming the second groove 116 , the mask layer 103 is always present, which can reduce the surface defects and etching damage of the conductive layer 110 , thereby improving the performance and stability of the conductive layer 110 itself.

[0062] When the etching selection ratio of the second source gas to the mask layer 103 is equal to the thickness of the mask layer 103, the mask layer is removed simultaneously during the process of forming the blocking film 115, thereby omitting a part of the step of removing the mask layer.

[0063] In some embodiments, the second source gas includes monofluoromethane and oxygen, and the flow rate of monofluoromethane is greater than the flow rate of oxygen. Since oxygen can remove the mask layer 103, the flow rate of monofluoromethane is greater than the flow rate of oxygen, which can ensure that the proportion of the second source gas that forms the barrier film 115 is greater than the proportion that removes the mask layer 103, thereby forming the barrier film 115 before removing the mask layer 103.

[0064] In some embodiments, the pretreatment is a dry etching process, and the conductive layer 110 and the barrier layer 109 in a partial area are etched by plasma etching and with the aid of a mask.

[0065] In some embodiments, the process and principle of the pretreatment include: first, the semiconductor structure with the mask layer 103 formed is loaded into the equipment, and then the pressure and source power of the original process equipment are increased. Increasing the pressure can increase the ability of the second source gas to deposit on the side wall of the conductive layer 110, and then increase the flow rate of the second source gas, and add a proper amount of oxidizing gas (oxygen) at the same time. The second source gas and the oxidizing gas are gases with a large specific gravity, which can be easily deposited on the side wall of the conductive layer 110. In addition, the bias power of the equipment is increased to increase the bombardment ability and directionality of the plasma, so as to assist the first source gas in etching the conductive layer 110 while assisting the second source gas in depositing on the surface of the conductive layer 110 and forming a barrier film 115.

[0066] It can be understood that the blocking film 115 is a chemical reaction between the second source gas and the plasma to produce new species. The embodiment of the present disclosure does not limit the specific structure of the blocking film 115. It is only necessary to know that the etching rate of the conductive layer 110 containing the blocking film is less than the etching rate of the conductive layer 110 not containing the blocking film.

[0067] In addition, the barrier film 115 may be a film layer composed of an amorphous gas, that is, a compound that has not formed a specific state.

[0068] The deposition principle is as follows: the power in the device is changed from pulse mode to continue mode. In the process of continuously generating plasma, ions and electrons will continue to etch the conductive layer 110 on the surface of the semiconductor structure. However, since the plasma is continuous, the etching by-products are not easy to be extracted, and the etching gas in the pretreatment is a heavy polymer gas, and the pressure set by the equipment is relatively large, which causes the gas molecules to easily vaporize onto the side wall of the conductive layer 110.

[0069] In some embodiments, when the material of the mask layer 103 is carbon, oxygen also has a certain etching ability on the mask layer 103. By adjusting the selection ratio, the mask layer 103 is etched away while the conductive layer 110 is etched to a preset depth set by the process.

[0070] In some embodiments, the pre-treatment process step includes: providing He gas, wherein the He gas serves as a diluent, thereby reducing local discharge and improving the yield of the semiconductor structure.

[0071] refer to Figure 5 , remove the mask layer to expose the top surface of the conductive layer 110.

[0072] refer to Figure 5 as well as Figure 6 , an etching process is performed on the conductive layer 110 to form a third groove 126 from the upper end of the conductive layer 110 , wherein in the etching process, the etching rate of the conductive layer 110 covered with the barrier film 115 is lower than the etching rate of the conductive layer 110 not covered with the barrier film 115 .

[0073] In some embodiments, the process steps of the etching process include: reducing the pressure and source power in the equipment, slowing down the flow rate of the etching gas and the deposition gas, and adjusting the bias power to 0 at the same time, so as to slow down the flow rate of the etching gas and the deposition gas, so that the etching morphology and etching rate of the third groove can be accurately controlled. Since a large amount of barrier film 115 and the gas formed by the barrier film 115 are deposited on the side wall of the conductive layer 110, the center of the conductive layer 110 will have a fast etching rate and the edge of the conductive layer 110 will have a slow etching rate during etching. After the etching is completed, a third groove 126 with a gradually decreasing line width is obtained, such as a V-shaped or U-shaped structure.

[0074] In some embodiments, the pretreatment and the formation of the third groove 126 can be performed in the same device. Since the second source gas has an etching effect on the mask layer 103, after the second groove 116 is formed, the pressure and bias power of the device can be adjusted to avoid forming a barrier film on the top of the conductive layer 110, but the second source gas continues to etch the mask layer 103 until the mask layer 103 is completely removed, and then the first source gas etches the top of the conductive layer 110 to form the third groove 126. In this way, only the process parameter setting for forming the second groove 116 can be changed, so that the second groove 116 and the third groove 126 can be formed, thereby increasing the contact area between the capacitor contact window and the lower electrode, saving process steps and reducing process costs.

[0075] In some embodiments, the process parameters of the pretreatment can be: pressure of 30Pa~100Pa, source power of 800W~1500W, bias power of 100W~200W, chlorine flow rate of 5sccm~15sccm, monofluoromethane flow rate of 150sccm~260sccm, oxygen flow rate of 5sccm~15sccm, and He flow rate of 50sccm~150sccm.

[0076] In some embodiments, the process parameters of the etching process are: pressure of 10 to 50 Pa, source power of 200 W to 800 W, bias power of 10 W to 100 W, chlorine flow rate of 5 sccm to 15 sccm, monofluoromethane flow rate of 150 sccm to 260 sccm, oxygen flow rate of 5 sccm to 15 sccm, and He flow rate of 50 sccm to 150 sccm.

[0077] In some embodiments, the etched conductive layer 110 serves as a contact window 117 .

[0078] refer to Figure 7 , remove the barrier film.

[0079] In some embodiments, a cleaning gas is used to remove the barrier film, and the cleaning gas includes any one or a combination of NF3, O2, Ar or CF4.

[0080] Continue to refer Figure 7 , forming a sacrificial layer 118 , wherein the sacrificial layer 118 is located on the surface of the isolation layer 102 .

[0081] refer to Figure 8 , forming a fourth groove, the fourth groove is located in the sacrificial layer 118, the fourth groove corresponds to the third groove and is connected; forming a conductive column 120, the conductive column 120 fills the third groove and the fourth groove.

[0082] In some embodiments, the conductive column 120 includes a continuous first conductive column 121 and a second conductive column 122, the first conductive column 121 is located in the contact window 117, and the second conductive column 122 is located on the surface of the contact window 117; along the direction from the second conductive column 122 to the first conductive column 121, the line width of the first conductive column 121 decreases.

[0083] In some embodiments, a cross-sectional shape of the first conductive pillar 121 along a direction perpendicular to the substrate surface includes: a U-shape or a V-shape.

[0084] In some embodiments, the material of the conductive pillar 120 includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0085] In some embodiments, the conductive pillar 120 serves as the lower electrode of the capacitor structure, and the subsequent steps include forming a capacitor dielectric layer and an upper electrode, which will not be described in detail here.

[0086] In the above-mentioned process steps of forming the contact window 117 and the conductive pillar 120 in the array area, the conductive layer 110 is pretreated to form a barrier film 115 on the inner wall surface of the second groove 116, and in the subsequent etching process, the etching rate of the conductive layer 110 covered with the barrier film 115 is lower than the etching rate of the conductive layer 110 not covered with the barrier film 115. In this way, only one step of etching the conductive layer 110 and modifying the process parameters of forming the second groove 116 to form the third groove 126 can be added to change the contact area between the conductive pillar and the conductive layer 110. Compared with forming a mask and patterning the third groove in the conventional process, the process steps and preparation costs can be reduced, thereby saving process time and improving the process rate.

[0087] In addition, the blocking film 115 covers the side of the conductive layer 110, and the blocking film 115 can protect the outer side of the conductive layer 110 so that the morphology of the conductive layer 110 is complete. The formed third groove 126 can increase the contact area between the conductive column and the contact window, thereby reducing the contact resistance between the conductive column 120 and the conductive layer 110, thereby improving the electrical performance of the semiconductor structure, reducing electrical losses, and increasing the response speed.

[0088] The following will be combined Figures 9 to 16 The steps corresponding to the peripheral region of the preparation method provided in the above embodiment are described in detail. The technical features that are the same as or corresponding to the above embodiment will not be described in detail here.

[0089] Figures 9 to 16 A schematic flow chart of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure.

[0090] refer to Fig. 9 , providing a substrate 20, wherein the substrate 20 has a plurality of first grooves 206 arranged at intervals.

[0091] In some embodiments, the base 20 may include a stacked substrate 200 and an isolation layer 202 , and the first groove 206 is located in the isolation layer 202 .

[0092] In some embodiments, the base 20 further includes an active layer 201 located between the substrate 200 and the isolation layer 202. The active layer 201 may include a channel region and first and second source and drain regions located at both ends of the channel region. The first groove 206 exposes the surface of the first or second source and drain region.

[0093] In some embodiments, the active layer 201 and the substrate 200 can be prepared from the same original substrate. Part of the thickness of the original substrate is patterned to form an active layer 201 arranged at intervals, and the remaining original substrate serves as the substrate 200. There is no interface state between the active layer 201 and the substrate 200. Instead, the active layer 201 and the substrate 200 are two different film layers divided due to different definitions of different functional limited areas. The two are actually the same film layer.

[0094] In some embodiments, an isolation structure 205 is included between adjacent active layers 201, and the isolation structure 205 is used to separate and isolate the spaced active layers 201. The isolation structure 205 may be a shallow trench isolation structure.

[0095] In some embodiments, the isolation structure 205 is an isolation structure formed of an isolation material, and the isolation structure 205 can be a single-layer film layer or a multi-layer film layer.

[0096] In some embodiments, the substrate 20 includes a gate structure, which includes a stacked gate dielectric layer 211, a first film layer 212, and a second film layer 213; and a third film layer 214, which covers the surfaces of the gate dielectric layer 211, the first film layer 212, and the second film layer 213. The material of the gate dielectric layer 211 includes silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), hafnium oxide silicate (HfSiO4), hafnium dioxide (HfO2), lanthanum oxide (La2O3), zirconium dioxide (ZrO2), strontium titanate (SrTiO3), or zirconium oxide silicate (ZrSiO4). The gate structure is a high-k metal-gate (HKMG) or a doped polysilicon gate. The first film layer 212 is a barrier layer or a work function layer. When the first film layer 212 is a barrier layer, the material of the first film layer can be titanium nitride or other metal nitrides. First, it is used to improve the gate polysilicon depletion problem, and second, it prevents the material of the top metal gate from penetrating downward into the gate dielectric layer 211 and affecting the gate dielectric layer. When the first film layer 212 is a work function layer, the first film layer can be aluminum oxide or lanthanum oxide. The material of the second film layer 213 includes metal or doped polysilicon. The material of the third film layer 214 includes silicon nitride, silicon oxide, or silicon oxynitride.

[0097] In some embodiments, the first groove exposes a surface of the second film layer.

[0098] refer to Fig.10 , forming a conductive layer 210 , which fills the first groove 206 and covers the surface of the isolation layer 202 .

[0099] In some embodiments, the material of the conductive layer 210 may include at least one of tungsten, tantalum, tungsten nitride, or tantalum nitride.

[0100] refer to Fig.11 , mask layers 203 arranged at intervals are formed on the surface of the conductive layer 210, the mask layers 203 completely overlap with the first grooves 206, and the area of ​​the mask layer 203 is larger than the area of ​​the first grooves 206, thereby ensuring that the top surface size of the subsequently formed conductive layer 210 away from the substrate 20 is larger than the bottom surface size, thereby giving full play to the role of the contact plug, improving the alignment accuracy, increasing the contact area and reducing the contact resistance.

[0101] Furthermore, the mask layer 203 has an opening 207 .

[0102] In some embodiments, the mask layer 203 may be a photoresist, or any material whose etching rate is different from that of the conductive layer 210 and the barrier layer under the same etching process. For example, the material of the mask layer 203 is carbon.

[0103] refer to Fig.12 , the conductive layer 210 is pre-treated, and the pre-treatment includes: using the mask layer 203 as a mask, patterning the conductive layer 210 and forming a second groove 216, wherein the side wall of the conductive layer 210 is exposed through the second groove 216; and forming a blocking film 215 on the side wall surface.

[0104] In some embodiments, the pretreatment process steps include: providing a first source gas and a second source gas, the first source gas is used to etch the conductive layer 210, and the second source gas is used to form a blocking film 215; removing a portion of the thickness of the conductive layer 210 not covered by the mask layer 203 to form a second groove 216, and forming a continuous blocking film 215 on the surface of the conductive layer 210 exposed by the inner wall surface of the second groove 216 and the bottom of the second groove 216.

[0105] It can be understood that the second groove 216 is engraved through the conductive layer 210 and exposes the top surface of the isolation layer 202 to achieve electrical insulation between the conductive layers 210 .

[0106] In some embodiments, the first source gas includes chlorine gas. The conductive layer 210 is removed by chlorine gas, and the etching rate is relatively high, so that the second groove can be formed quickly.

[0107] In some embodiments, the second source gas includes monofluoromethane and oxygen, and the flow rate of monofluoromethane is greater than the flow rate of oxygen.

[0108] In some embodiments, reference Fig.13, the second source gas is also used to remove the mask layer 203, and the etching selectivity ratio of the second source gas to the mask layer 203 is less than or equal to the thickness of the mask layer. In this way, during the process of forming the second groove, the mask layer 203 always exists, and after forming the second groove 216, the mask layer 203 still exists or is completely removed at the same time, so that the blocking film 215 will not be formed on the surface of the conductive layer 210 covered by the mask layer 203, and the third groove can be formed later by the different etching rates of the uncovered conductive layer 210 and the covered conductive layer 210.

[0109] In some embodiments, the pretreatment is a dry etching process, and the conductive layer 210 and the barrier layer in a partial area are etched by plasma etching and with the aid of a mask.

[0110] In some embodiments, when the material of the mask layer 203 is carbon, oxygen also has a certain etching ability on the mask layer 203. By adjusting the selection ratio, the mask layer is etched away while the conductive layer 210 is etched to a preset depth set by the process.

[0111] In some embodiments, the pre-treatment process step includes: providing He gas, wherein the He gas serves as a diluent, thereby reducing local discharge and improving the yield of the semiconductor structure.

[0112] refer to Fig.13 , remove the mask layer to expose the top surface of the conductive layer 210.

[0113] refer to Fig.13 as well as Fig.14 The conductive layer 210 is etched to form a third groove 226 from the upper end of the conductive layer 210 , wherein in the etching process, the etching rate of the conductive layer 210 covered with the barrier film 215 is lower than the etching rate of the conductive layer 210 not covered with the barrier film 215 .

[0114] In some embodiments, you can jump Fig.13 The steps included, namely pretreatment and forming the third groove 226 can be performed in the same device. Since the second source gas has an etching effect on the mask layer 203, after the second groove 216 is formed, the pressure and bias power of the equipment can be adjusted to avoid the formation of a blocking film 215 on the top of the conductive layer 210, but the second source gas continues to etch the mask layer 203 until the mask layer 203 is completely removed, and then the first source gas etches the top of the conductive layer 210 to form the third groove 226.

[0115] In some embodiments, the process parameters of the pretreatment can be: pressure of 30Pa~100Pa, source power of 800W~1500W, bias power of 100W~200W, chlorine flow rate of 5sccm~15sccm, monofluoromethane flow rate of 150sccm~260sccm, oxygen flow rate of 5sccm~15sccm, and He flow rate of 50sccm~150sccm.

[0116] In some embodiments, the process parameters of the etching process are: pressure of 10 to 50 Pa, source power of 200 W to 800 W, bias power of 10 W to 100 W, chlorine flow rate of 5 sccm to 15 sccm, monofluoromethane flow rate of 150 sccm to 260 sccm, oxygen flow rate of 5 sccm to 15 sccm, and He flow rate of 50 sccm to 150 sccm.

[0117] In some embodiments, the etched conductive layer 210 serves as a contact window 217 .

[0118] refer to Fig.15 , remove the barrier film.

[0119] In some embodiments, a cleaning gas is used to remove the barrier film, and the cleaning gas includes any one or a combination of NF3, O2, Ar or CF4.

[0120] Continue to refer Fig.15 , forming a sacrificial layer 218 , wherein the sacrificial layer 218 is located on the surface of the isolation layer 202 .

[0121] refer to Fig.16 , forming a fourth groove, the fourth groove is located in the sacrificial layer 218, the fourth groove corresponds to the third groove and is connected; forming a conductive column 220, the conductive column 220 fills the third groove and the fourth groove.

[0122] In some embodiments, the conductive column 220 includes a continuous first conductive column 221 and a second conductive column 222, wherein the first conductive column 221 is located in the contact window 217 and the second conductive column 222 is located on the surface of the contact window 217; along the direction from the second conductive column 222 to the first conductive column 221, the line width of the first conductive column 221 decreases.

[0123] In some embodiments, the cross-sectional shape of the first conductive pillar 221 along a direction perpendicular to the surface of the substrate 10 includes: U-shape or V-shape.

[0124] In some embodiments, the material of the conductive pillar 220 includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0125] In some embodiments, the conductive pillar 220 serves as a second contact structure.

[0126] In the above-mentioned process steps of forming the contact window 217 and the second contact structure in the peripheral area, the conductive layer 210 is pre-treated to form a barrier film 215 on the inner wall surface of the second groove 216, and in the subsequent etching process, the etching rate of the conductive layer 210 covered with the barrier film is lower than the etching rate of the conductive layer 210 not covered with the barrier film. In this way, only one step of etching the conductive layer 210 to form the third groove can be added or the process parameters for forming the second groove 216 can be changed to change the contact area between the conductive column 220 and the conductive layer 210. Compared with the conventional process of forming a mask and patterning the third groove, the process steps and preparation costs can be reduced, thereby saving process time and improving the process rate. In addition, the barrier film covers the side of the conductive layer 210, and the barrier film can protect the outer side of the conductive layer 210 so that the morphology of the conductive layer 210 is complete. The formed third groove can increase the contact area between the conductive column and the contact window, thereby reducing the contact resistance between the conductive column and the conductive layer 210, thereby improving the electrical performance of the semiconductor structure, reducing electrical losses, and increasing the response speed.

[0127] In addition, in the same process step, the conductive layers in the array area and the peripheral area can be pretreated and etched at the same time, thereby simultaneously forming a capacitor contact window with a third groove and a first contact structure, thereby reducing the contact resistance between the first contact structure and the second contact structure in the peripheral area and the contact resistance between the lower electrode and the capacitor contact window. When the voltage remains unchanged, it is equivalent to increasing the current, thereby making it easier to export the signal to the outside world and improving the performance of the chip.

[0128] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a semiconductor structure on the other hand, which can be prepared using the preparation method provided by the above embodiments. The technical features that are the same or corresponding to the above embodiments will not be elaborated here.

[0129] When the substrate is an array area, refer to Figure 8 The semiconductor structure includes: a substrate 10 having a contact window 117 therein, the contact window 117 protruding from the surface of the substrate 10; a conductive column 120, part of the conductive column 120 being located in the contact window 117, and part of the conductive column 120 being located on the surface of the contact window 117.

[0130] In some embodiments, the substrate 10 may include a stacked substrate 100 and an isolation layer 102, and the first groove 106 is located in the isolation layer 102. The substrate 10 also includes: an active layer 101, and the active layer 101 is located between the substrate 100 and the isolation layer 102. The active layer 101 may include a channel region and a first source and drain region and a second source and drain region located at both ends of the channel region. The bit line 108 and the capacitor plug 104 are electrically connected to the first source and drain region or the second source and drain region of the active layer 101, respectively.

[0131] In some embodiments, an isolation structure 105 is included between adjacent active layers 101 , and the isolation structure 105 is used to separate and isolate the active layers 101 that are arranged at intervals.

[0132] In some embodiments, the semiconductor structure includes a bit line 108 and a word line. The word line is located in the isolation structure 105 on one side of the channel region. The end of the bit line 108 away from the substrate 100 has a barrier layer 109, which is used to isolate the bit line 108 from the capacitor structure.

[0133] In some embodiments, the substrate 10 further includes a capacitor plug 104 , which is located in the isolation layer 102 and is electrically connected to the active layer 101 . The capacitor plug 104 may be a metal silicide layer or a polysilicon layer, and is in electrical contact with the contact window 117 .

[0134] In some embodiments, the conductive column 120 includes a continuous first conductive column 121 and a second conductive column 122, the first conductive column 121 is located in the contact window 117, and the second conductive column 122 is located on the surface of the contact window 117; along the direction from the second conductive column 122 to the first conductive column 121, the line width of the first conductive column 121 decreases.

[0135] In some embodiments, a cross-sectional shape of the first conductive pillar 121 along a direction perpendicular to the substrate surface includes: a U-shape or a V-shape.

[0136] In some embodiments, the semiconductor structure further includes a sacrificial layer 118 , the sacrificial layer 118 is located on the surface of the isolation layer 102 , and the conductive pillar is located in the sacrificial layer 118 .

[0137] When the substrate is the peripheral region, refer to Fig.16 The semiconductor structure includes: a substrate 20 having a contact window 217 therein, the contact window 217 protruding from the surface of the substrate 20; a conductive column 220, part of the conductive column 220 being located in the contact window 217, and part of the conductive column 220 being located on the surface of the contact window 217.

[0138] In some embodiments, the base 20 may include a stacked substrate 200 and an isolation layer 202 , and the first groove 206 is located in the isolation layer 202 .

[0139] In some embodiments, the base 20 further includes an active layer 201 located between the substrate 200 and the isolation layer 202. The active layer 201 may include a channel region and a first source and drain region and a second source and drain region located at both ends of the channel region. The contact window 217 is in electrical contact with the first source and drain region or the second source and drain region.

[0140] In some embodiments, the substrate 20 includes a gate structure, which includes a stacked gate dielectric layer 211, a first film layer 212, and a second film layer 213; a third film layer 214, and the third film layer 214 covers the surfaces of the gate dielectric layer 211, the first film layer 212, and the second film layer 213. The contact window penetrates the third film layer 214 and is in electrical contact with the second film layer 213.

[0141] In some embodiments, the conductive column 220 includes a continuous first conductive column 221 and a second conductive column 222, wherein the first conductive column 221 is located in the contact window 217 and the second conductive column 222 is located on the surface of the contact window 217; along the direction from the second conductive column 222 to the first conductive column 221, the line width of the first conductive column 221 decreases.

[0142] In some embodiments, the cross-sectional shape of the first conductive pillar 221 along a direction perpendicular to the surface of the substrate 10 includes: U-shape or V-shape.

[0143] In some embodiments, the semiconductor structure further includes a sacrificial layer 218 , the sacrificial layer 218 is located on the surface of the isolation layer 202 , and the conductive pillar is located in the sacrificial layer 218 .

[0144] Correspondingly, another aspect of the embodiments of the present disclosure provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the method for preparing a semiconductor structure as described in any one of the above embodiments is implemented.

[0145] In some embodiments, the computer-readable storage medium may include, but is not limited to, a floppy disk, an optical disk, a compact disk-read only memory CD-ROM, a magneto-optical disk, a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or it may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc., a magnetic card or an optical card, a flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions. In addition, the computer-readable storage medium may be a product that is not connected to a computer device, or it may be a component that is connected to a computer device for use.

[0146] Fig.17 A structural block diagram of a terminal provided in one embodiment of the present disclosure.

[0147] Accordingly, some embodiments of the present disclosure provide a terminal on the other hand, referring to Fig.17 The terminal 30 includes a processor 32 and a memory 31, the memory 31 is used to store computer programs, and the processor 32 is used to execute the computer programs stored in the memory 31, so that the terminal 30 executes the method for preparing a semiconductor structure as any one of the above embodiments.

[0148] In some embodiments, the processor 32 may be a general-purpose processor, including one or more central processing units (CPUs), network processors (NPs), etc.; it may also be a microcontroller unit (MCU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory 31 may include, but is not limited to, a high-speed random access memory, a non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. Random access memory includes dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory LPDDR SDRAM, graphic double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, thyristor random access memory TRAM, etc.; non-volatile memory includes phase change random access memory PRAM, magnetic random access memory MRAM, resistive random access memory RRAM, etc., magnetic card or optical card, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0149] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a plurality of first grooves arranged at intervals; forming a conductive layer, wherein the conductive layer completely fills the first groove and covers the surface of the substrate; Forming mask layers arranged at intervals on the surface of the conductive layer, wherein the mask layers partially overlap with the first grooves; Pre-processing the conductive layer, the pre-processing comprising: using the mask layer as a mask, patterning the conductive layer and forming a second groove, wherein the side wall of the conductive layer is exposed through the second groove; forming a barrier film on the side wall surface; Performing an etching process on the conductive layer to form a third groove from the upper end of the conductive layer, wherein in the etching process, an etching rate of the conductive layer covered with the barrier film is lower than an etching rate of the conductive layer not covered with the barrier film; A conductive column is formed, wherein the conductive column fills the third groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The process steps of the pretreatment include: Providing a first source gas and a second source gas, wherein the first source gas is used to etch the conductive layer, and the second source gas is used to form a barrier film; A portion of the conductive layer not covered by the mask layer is removed to form a second groove, and a continuous barrier film is formed on the inner wall surface of the second groove and the surface of the conductive layer exposed at the bottom of the second groove.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The second source gas is also used to remove the mask layer, and an etching selection ratio of the second source gas to the mask layer is less than or equal to a thickness of the mask layer.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: The second source gas includes monofluoromethane and oxygen, and a flow rate of the monofluoromethane is greater than a flow rate of the oxygen.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The substrate includes an array region and a peripheral region, and the conductive layer is located in the array region and / or the peripheral region.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming the conductive pillar, the method further includes: removing the barrier film.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The barrier film is removed by using a cleaning gas, wherein the cleaning gas includes any one of NF3, O2, Ar or CF4 or a combination of multiple thereof.

8. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a contact window therein, and the contact window protrudes from a surface of the substrate; Conductive pillars, part of which is located in the contact window, and part of which is located on the surface of the contact window.

9. The semiconductor structure according to claim 8, characterized in that: The conductive column includes a continuous first conductive column and a second conductive column, the first conductive column is located in the contact window, and the second conductive column is located on the surface of the contact window; along the direction from the second conductive column to the first conductive column, the line width of the first conductive column decreases.

10. The semiconductor structure according to claim 9, characterized in that: The cross-sectional shape of the first conductive pillar along a direction perpendicular to the surface of the substrate includes: U-shape or V-shape.

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