Chip packaging structure and chip packaging method

Abstract

The invention discloses a chip packaging structure and a chip packaging method, a cavity is formed by adopting a polymer bonding mode, and an annular metal cofferdam and a side wall metal plugging mode are added on a bonding surface, so that the cost is reduced, the air tightness of the cavity is improved, and the reliability standard which is the same as that of metal bonding can be achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a chip packaging structure and a chip packaging method. Background Art

[0002] Wafer-level airtight bonding generally adopts dielectric-free bonding, metal dielectric bonding or polymer bonding. Among them, dielectric-free bonding, such as silicon-silicon, silicon oxide-silicon oxide or anodic bonding, etc., all have extremely high flatness and cleanliness requirements for the two wafers to be bonded, so expensive pre-treatment processes and bonding equipment are required to ensure the bonding effect. Metal bonding, such as aluminum germanium or gold-gold, gold-tin, etc., all require the surfaces of the two wafers to be bonded to have nanometer-level flatness, and pre-place two metals for bonding on the flat surfaces of the two wafers. The bonding pre-treatment is complicated and the bonding requires high temperature and pressure. Although polymer bonding has low cost and low requirements for wafer surface flatness, it can fill some concave and convex morphologies on the wafer surface. However, because the high molecular components of the polymer itself are difficult to isolate the penetration of small molecules, it is easy to cause the cavity formed by it to have poor airtightness.

[0003] For BAW filters, the industry standard packaging method is usually to form a cavity by gold-gold bonding between the chip and the cover. However, the gold-gold bonding method is expensive and has high requirements for the supporting equipment required.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a chip packaging structure and a chip packaging method, which can improve the airtightness of the formed cavity, achieve the same reliability standard as gold-gold bonding, and have low cost.

[0006] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0007] A chip packaging structure, comprising:

[0008] substrate;

[0009] A chip module is arranged on the surface of the substrate, the chip module comprises a chip and a cover plate, the chip has a functional area, the cover plate covers the functional area and forms a cavity, a polymer bonding layer is formed between the cover plate and the chip, an annular metal cofferdam is formed in the polymer bonding layer, and the functional area is located within the range surrounded by the annular metal cofferdam;

[0010] A first metal layer, formed at least on the peripheral surface of the chip module and covering the polymer bonding layer;

[0011] A plastic package is formed on the surface of the substrate and covers the chip module and the first metal layer.

[0012] In one or more embodiments of the present invention, the first metal layer completely covers the peripheral surface of the chip module; or,

[0013] The first metal layer completely covers the peripheral surface of the chip module and extends to a surface of the chip module facing away from the substrate; or,

[0014] The first metal layer completely covers the peripheral surface of the chip module and extends to completely cover a surface of a side of the chip module away from the substrate.

[0015] In one or more embodiments of the present invention, the thickness of the first metal layer is less than or equal to 1 μm; and / or;

[0016] The polymer bonding layer comprises a glue bonding layer; and / or

[0017] The annular metal cofferdam is an annular inorganic metal cofferdam; and / or

[0018] The first metal layer is an inorganic metal layer; and / or

[0019] The cover plate includes a silicon cover plate.

[0020] In one or more embodiments of the present invention, the chip has a first surface, the functional area is formed on the first surface, a first bonding area is formed on the first surface, and the first bonding area is arranged around the functional area;

[0021] The cover plate is disposed on the first surface of the chip, and the cover plate has a second bonding area bonded to the first bonding area;

[0022] The polymer bonding layer is disposed between the first bonding region and the second bonding region;

[0023] The annular metal dam is disposed on the first bonding area and / or the second bonding area and is located within the polymer bonding layer.

[0024] In one or more embodiments of the present invention, a circuit structure is formed in the substrate;

[0025] A conductive structure is formed on a side of the chip facing away from the cover plate, and the conductive structure is electrically connected to the circuit structure.

[0026] A chip packaging method, comprising:

[0027] A chip module is provided, the chip module comprising a chip and a cover plate, the chip having a functional area, the cover plate covering the functional area and forming a cavity, a polymer bonding layer formed between the cover plate and the chip, an annular metal cofferdam formed in the polymer bonding layer, and the functional area is located within a range enclosed by the annular metal cofferdam;

[0028] Providing a temporary substrate, and placing one or more chip modules on the temporary substrate, wherein the chip side of the chip module is in contact with the temporary substrate;

[0029] forming a first metal layer covering the chip module on the temporary substrate;

[0030] Peeling off the temporary substrate and the chip module;

[0031] Providing a substrate, and placing the chip module on a surface of the substrate;

[0032] A plastic package covering the chip module and the first metal layer is formed on the surface of the substrate.

[0033] A chip packaging structure, comprising:

[0034] substrate;

[0035] A chip module is arranged on the surface of the substrate, the chip module comprises a chip and a cover plate, the chip has a functional area, the cover plate covers the functional area and forms a cavity, a polymer bonding layer is formed between the cover plate and the chip, an annular metal cofferdam is formed in the polymer bonding layer, and the functional area is located within the range surrounded by the annular metal cofferdam;

[0036] A plastic package is formed on the surface of the substrate and covers the chip module;

[0037] The second metal layer is formed on the surface of the plastic package body and extends to the peripheral surface of the substrate.

[0038] In one or more embodiments of the present invention, the annular metal cofferdam is an annular inorganic metal cofferdam; and / or

[0039] The second metal layer is an inorganic metal layer; and / or

[0040] The polymer bonding layer comprises a glue bonding layer; and / or

[0041] The cover plate includes a silicon cover plate.

[0042] In one or more embodiments of the present invention, the chip has a first surface, the functional area is formed on the first surface, a first bonding area is formed on the first surface, and the first bonding area is arranged around the functional area;

[0043] The cover plate is disposed on the first surface of the chip, and the cover plate has a second bonding area bonded to the first bonding area;

[0044] The polymer bonding layer is disposed between the first bonding region and the second bonding region;

[0045] The annular metal dam is disposed on the first bonding area and / or the second bonding area and is located within the polymer bonding layer.

[0046] In one or more embodiments of the present invention, a circuit structure is formed in the substrate;

[0047] A conductive structure is formed on a side of the chip facing away from the cover plate, and the conductive structure is electrically connected to the circuit structure.

[0048] A chip packaging method, comprising:

[0049] A chip module is provided, the chip module comprising a chip and a cover plate, the chip having a functional area, the cover plate covering the functional area and forming a cavity, a polymer bonding layer formed between the cover plate and the chip, an annular metal cofferdam formed in the polymer bonding layer, and the functional area is located within a range enclosed by the annular metal cofferdam;

[0050] Providing a substrate, and placing the chip module on a surface of the substrate;

[0051] Forming a plastic package covering the chip module on the surface of the substrate;

[0052] Providing a temporary substrate, placing one or more plastic-encapsulated chip modules on the temporary substrate, wherein the base is bonded to the temporary substrate;

[0053] forming a second metal layer covering the plastic-sealed chip module on the temporary substrate;

[0054] The temporary substrate is removed.

[0055] Compared with the prior art, the chip packaging structure and chip packaging method of the present invention use polymer bonding to form a cavity, and then increase the annular metal cofferdam and side wall metal plugging on the bonding surface to reduce costs while improving the airtightness of the cavity, and can achieve the same reliability standards as metal bonding.

[0056] In the chip packaging structure and the chip packaging method of the present invention, the cover plate adopts a silicon cover plate, which is easy to process and has low cost.

[0057] The chip packaging structure and chip packaging method of the present invention, the annular metal cofferdam or the sidewall metal blocking method can be randomly added during the chip packaging process without adding new processes and equipment, and there is no need to purchase high-cost bonding equipment separately. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 is a cross-sectional schematic diagram of a chip packaging structure in Embodiment 1 of the present invention;

[0060] Figure 2a-2k A schematic diagram of the steps of a packaging method for a chip packaging structure in Embodiment 1 of the present invention;

[0061] Figure 3 is a cross-sectional schematic diagram of a chip packaging structure in Embodiment 2 of the present invention;

[0062] Figure 4a-4f Schematic diagram of the steps of the packaging method of the chip packaging structure in Example 2 of the present invention. DETAILED DESCRIPTION

[0063] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0064] like Figure 1 As shown, the chip packaging structure in Embodiment 1 of the present invention includes a substrate 10, a chip module 20, a first metal layer 30 and a plastic package 40. The chip module 20 includes a chip 210, a cover plate 220, a polymer bonding layer 230 and an annular metal dam 240.

[0065] The substrate 10 is preferably a PCB board, and a circuit structure is formed in the substrate 10 .

[0066] The chip module 20 is disposed on the surface of the substrate 10 . A conductive structure 250 and a metal solder ball 260 are formed on the side of the chip 210 in the chip module 20 away from the cover plate 220 . The conductive structure 250 is electrically connected to the circuit structure through the metal solder ball 260 .

[0067] Figure 2f FIG. 2 is a cross-sectional schematic diagram of the chip module 20 in the chip packaging structure in the first embodiment.

[0068] refer to Figure 2f As shown, the chip 210 may be a bulk acoustic wave filter chip. The chip 210 has a first surface 210a, and the first surface 210a has a functional area A and a first bonding area B, and the first bonding area B is arranged around the functional area A. A pad 211 is also arranged on the first surface 210a in the first bonding area B, and the pad 211 is electrically connected to the functional components in the functional area A.

[0069] A through hole 212 is provided on the surface of the chip 210 opposite to the first surface 210a, and the through hole 212 exposes the pad 211. A conductive structure 250 is formed in the through hole 212, which can electrically lead the pad 211. The conductive structure 250 may include a barrier layer 251, a conductive metal layer 252, and an insulating layer 253. A metal solder ball 260 electrically connected to the conductive structure 250 is also provided on the surface of the chip 210 opposite to the first surface 210a. The arrangement of the conductive structure 250 and the metal solder ball 260 can adopt the existing technology, but since it is not the main inventive point of the present invention, the present invention will not elaborate on it in detail.

[0070] The cover plate 220 has a second surface 220a, the second surface 220a has a second bonding area C, and a groove 221 surrounded by the second bonding area C is formed on the second surface 220a. The second surface 220a of the cover plate 220 is arranged in contact with the first surface 210a of the chip 210, the groove 221 corresponds to and covers the functional area A to form a cavity, and the second bonding area C is bonded to the first bonding area B.

[0071] The polymer bonding layer 230 is disposed between the first bonding area B and the second bonding area C. The polymer bonding layer 230 is preferably a glue bonding layer.

[0072] The annular metal cofferdam 240 is disposed on the first bonding area B or the second bonding area C and is located in the polymer bonding layer 230. Preferably, the pad 211 and the functional area A are both located within the range surrounded by the annular metal cofferdam 240. The height of the annular metal cofferdam 240 is not higher than the thickness of the polymer bonding layer 230, and the width of the annular metal cofferdam 240 is not greater than the width of the polymer bonding layer 230.

[0073] Exemplarily, the number of turns of the annular metal cofferdam 240 may be one or more turns. When the number of turns of the annular metal cofferdam 240 is multiple turns, the multiple turns of the annular metal cofferdam 240 are arranged in a concentric ring-like interval. Part of the multiple turns of the annular metal cofferdam 240 may be formed on the first bonding area B, and the remaining annular metal cofferdam 240 may be formed on the second bonding area C, and the annular metal cofferdam 240 arranged on the first bonding area B and the annular metal cofferdam 240 arranged on the second bonding area C are mutually staggered or alternately staggered.

[0074] In a preferred embodiment, the material of the annular metal cofferdam 240 is selected from inorganic metals to further improve the air tightness.

[0075] refer to Figure 1 As shown, the first metal layer 30 is formed on the peripheral surface of the chip module 20 and completely covers the peripheral surface of the chip module 20, and extends to and completely covers the surface of the chip module 20 on one side away from the substrate 10. The thickness of the first metal layer 30 is less than or equal to 1 μm. The first metal layer 30 is preferably an inorganic metal layer. The provision of the first metal layer 30 blocks the area where the polymer bonding layer 230 is located in the chip module 20, greatly improving the airtightness of the chip module 20.

[0076] It is understandable that the first metal layer 30 may also be formed on the peripheral surface of the chip module 20 and only cover the polymer bonding layer 230. Alternatively, the first metal layer 30 may also only completely cover the peripheral surface of the chip module 20. Alternatively, the first metal layer 30 may completely cover the peripheral surface of the chip module 20 and extend to the side surface of the chip module 20 away from the substrate 10.

[0077] The plastic package 40 is formed on the surface of the substrate 10 and completely covers the chip module 20 and the first metal layer 30 .

[0078] Figure 2a-2k Schematic diagram of the steps of the packaging method of the chip packaging structure in Embodiment 1 of the present invention. Figure 2a to Figure 2k , the chip packaging method of embodiment 1 of the present invention is described in detail.

[0079] refer to Figure 2a As shown, a wafer-level chip 210 is provided. The chip 210 may be a bulk acoustic wave filter chip. The chip 210 has a first surface 210a, and the first surface 210a has a functional area A and a first bonding area B, and the first bonding area B is arranged around the functional area A. A pad 211 is also arranged on the first surface 210a in the first bonding area B, and the pad 211 is electrically connected to the functional components in the functional area A.

[0080] refer to Figure 2bAs shown, an annular metal cofferdam 240 is formed in the first bonding area B on the first surface 210a of the chip 210. The annular metal cofferdam 240 is arranged to surround the pad 211 and the functional area A. A polymer coating, such as glue, is coated in the first bonding area B on the first surface 210a of the chip 210, wherein the thickness of the polymer coating is flush with the height of the annular metal cofferdam 240, or the thickness of the polymer coating is slightly higher than the height of the annular metal cofferdam 240.

[0081] refer to Figure 2c As shown, a cover plate 220 is provided, the cover plate 220 has a second surface 220a, the second surface 220a has a second bonding area C, and a groove 221 surrounded by the second bonding area C is formed on the second surface 220a. The second surface 220a of the cover plate 220 is attached to the first surface 210a of the chip 210. The groove 221 corresponds to the functional area A and covers the functional area A to form a cavity, and the second bonding area C is bonded to the first bonding area B through the polymer coating.

[0082] refer to Figure 2d and Figure 2e As shown, a through hole 212 is provided on the surface of the chip 210 opposite to the first surface 210a, and the through hole 212 exposes the pad 211. A barrier layer 251, a conductive metal layer 252 and an insulating layer 253 are sequentially formed in the through hole 212, wherein the conductive metal layer 252 is electrically connected to the pad 211. The barrier layer 251, the conductive metal layer 252 and the insulating layer 253 constitute a conductive structure 250 for electrically extracting the pad 211.

[0083] refer to Figure 2f As shown, the above-mentioned packaging structure is cut to form a single chip module 20 .

[0084] refer to Figure 2g As shown, a temporary substrate 50 is provided, and one or more chip modules 20 are arranged on the same surface of the temporary substrate 50, wherein the chip side of the chip module 20 is attached to the temporary substrate 50, and the multiple chip modules 20 are arranged at intervals.

[0085] Exemplarily, the temporary substrate 50 may be a tape, and the plurality of chip modules 20 are adhered to the surface of the tape by a semiconductor tape process.

[0086] refer to Figure 2hAs shown, a first metal layer 30 covering the chip module 20 is formed on the temporary substrate 50. The formation process of the first metal layer 30 may be a physical vapor deposition sputtering process. The first metal layer 30 is formed on the peripheral surface of the chip module 20 and completely covers the peripheral surface of the chip module 20, and extends to and completely covers the side surface of the chip module 20 away from the substrate 10. Of course, in other embodiments, the first metal layer 30 may also be formed on the peripheral surface of the chip module 20 and only cover the polymer bonding layer 230. Alternatively, the first metal layer 30 may also only completely cover the peripheral surface of the chip module 20. Alternatively, the first metal layer 30 may completely cover the peripheral surface of the chip module 20 and extend to the side surface of the chip module 20 away from the substrate 10.

[0087] refer to Figure 2i As shown, the temporary substrate 20 and the chip module 20 are peeled off to obtain the chip module 20 with the first metal layer 30 disposed on the peripheral surface and the upper surface.

[0088] refer to Figure 2j As shown, metal solder balls 260 electrically connected to the conductive structure 250 are arranged on the chip side surface of the chip module 20 using ball grid array packaging technology.

[0089] refer to Figure 2k As shown, a substrate 10 is provided, and one or more chip modules 20 provided with a first metal layer 30 are arranged on the surface of the substrate 10 , wherein the conductive structure 250 is electrically connected to the circuit structure of the substrate 10 through the metal solder ball 260 .

[0090] refer to Figure 1 As shown, a plastic package body 40 covering the chip module 20 and the first metal layer 30 is formed on the surface of the substrate 10, and finally cut to complete the packaging of the chip packaging structure in the present invention.

[0091] like Figure 3 As shown, the chip packaging structure in Embodiment 2 of the present invention includes a substrate 10, a chip module 20, a plastic package 40 and a second metal layer 300. The chip module 20 includes a chip 210, a cover plate 220, a polymer bonding layer 230 and an annular metal dam 240.

[0092] The substrate 10 is preferably a PCB board, and a circuit structure is formed in the substrate 10 .

[0093] The chip module 20 is disposed on the surface of the substrate 10 . A conductive structure 250 and a metal solder ball 260 are formed on the side of the chip 210 in the chip module 20 away from the cover plate 220 . The conductive structure 250 is electrically connected to the circuit structure through the metal solder ball 260 .

[0094] Figure 4a FIG. 2 is a cross-sectional diagram of a chip module 20 in a chip packaging structure in the second embodiment.

[0095] refer to Figure 4a As shown, the chip 210 may be a bulk acoustic wave filter chip. The chip 210 has a first surface 210a, and the first surface 210a has a functional area A and a first bonding area B, and the first bonding area B is arranged around the functional area A. A pad 211 is also arranged on the first surface 210a in the first bonding area B, and the pad 211 is electrically connected to the functional components in the functional area A.

[0096] A through hole 212 is provided on the surface of the chip 210 opposite to the first surface 210a, and the through hole 212 exposes the pad 211. A conductive structure 250 is formed in the through hole 212, which can electrically lead the pad 211. The conductive structure 250 may include a barrier layer 251, a conductive metal layer 252, and an insulating layer 253. A metal solder ball 260 electrically connected to the conductive structure 250 is also provided on the surface of the chip 210 opposite to the first surface 210a. The arrangement of the conductive structure 250 and the metal solder ball 260 can adopt the existing technology, but since it is not the main inventive point of the present invention, the present invention will not elaborate on it in detail.

[0097] The cover plate 220 has a second surface 220a, the second surface 220a has a second bonding area C, and a groove 221 surrounded by the second bonding area C is formed on the second surface 220a. The second surface 220a of the cover plate 220 is arranged in contact with the first surface 210a of the chip 210, the groove 221 corresponds to and covers the functional area A to form a cavity, and the second bonding area C is bonded to the first bonding area B.

[0098] The polymer bonding layer 230 is disposed between the first bonding area B and the second bonding area C. The polymer bonding layer 230 is preferably a glue bonding layer.

[0099] The annular metal cofferdam 240 is disposed on the first bonding area B or the second bonding area C and is located in the polymer bonding layer 230. Preferably, the pad 211 and the functional area A are both located within the range surrounded by the annular metal cofferdam 240. The height of the annular metal cofferdam 240 is not higher than the thickness of the polymer bonding layer 230, and the width of the annular metal cofferdam 240 is not greater than the width of the polymer bonding layer 230.

[0100] Exemplarily, the number of turns of the annular metal cofferdam 240 may be one or more turns. When the number of turns of the annular metal cofferdam 240 is multiple turns, the multiple turns of the annular metal cofferdam 240 are arranged in a concentric ring-like interval. Part of the multiple turns of the annular metal cofferdam 240 may be formed on the first bonding area B, and the remaining annular metal cofferdam 240 may be formed on the second bonding area C, and the annular metal cofferdam 240 arranged on the first bonding area B and the annular metal cofferdam 240 arranged on the second bonding area C are mutually staggered or alternately staggered.

[0101] In a preferred embodiment, the material of the annular metal cofferdam 240 is selected from inorganic metals to further improve the air tightness.

[0102] refer to Figure 3 As shown, the plastic package 40 is formed on the surface of the substrate 10 and completely covers the chip module 20 .

[0103] The second metal layer 300 is formed on the surface of the plastic package 40, including the peripheral surface and the upper surface (on the surface away from the substrate 10) and extends to the peripheral surface of the substrate 10. The second metal layer 300 is preferably an inorganic metal layer. The second metal layer 300 is provided to seal the plastic package 40 and the chip module 20, greatly improving the airtightness of the chip module 20.

[0104] Figure 4a-4f FIG. 2 is a schematic diagram of the steps of the packaging method of the chip packaging structure in Embodiment 2 of the present invention. Figures 4a to 4f , the chip packaging method of embodiment 2 of the present invention is described in detail.

[0105] It should be noted that the steps for making the chip module 20 in this embodiment 2 are the same as those in embodiment 1, so the detailed making process can be referred to the attached diagram in embodiment 1. Figure 2a To Attachment Figure 2e Description.

[0106] refer to Figure 4a As shown, a chip module 20 is provided.

[0107] refer to Figure 4b As shown, metal solder balls 260 electrically connected to the conductive structure 250 are arranged on the chip side (the side where the chip is located) of the chip module 20 using ball grid array packaging technology.

[0108] refer to Figure 4c As shown, a substrate 10 is provided, and one or more chip modules 20 are arranged on the surface of the substrate 10 , wherein the conductive structure 250 is electrically connected to the circuit structure of the substrate 10 through the metal solder balls 260 .

[0109] refer to Figure 4d As shown, a plastic package body 40 is formed on the surface of the substrate 10 to completely cover the chip module 20. When there are multiple plastic-encapsulated chip modules 20, they can be cut after the plastic encapsulation is completed to obtain a single plastic-encapsulated structure.

[0110] refer to Figure 4e As shown, a temporary substrate 50 is provided, and one or more structures after the chip module 20 is plastic-sealed are arranged on the same surface of the temporary substrate 50, wherein the substrate side is in contact with the temporary substrate 50, and multiple structures are arranged at intervals.

[0111] Exemplarily, the temporary substrate 50 may be a tape, and the plurality of structures are adhered to the surface of the tape by a semiconductor tape process.

[0112] refer to Figure 4f As shown, a second metal layer 300 covering the chip module after plastic packaging is formed on the temporary substrate 50. The second metal layer 300 can be formed by a physical vapor deposition sputtering process. The second metal layer 300 is formed on the surface of the plastic packaging body 40, including the peripheral surface and the upper surface (on the surface away from the substrate 10) and extends to the peripheral surface of the substrate 10.

[0113] refer to Figure 3 As shown, the temporary substrate 20 and the encapsulated chip module 20 are peeled off to obtain a packaging structure with the second metal layer 300 disposed on the circumference and the upper surface. Thus, the packaging of the chip packaging structure in the present invention is completed.

[0114] Compared with the prior art, the chip packaging structure and chip packaging method of the present invention use polymer bonding to form a cavity, and then increase the annular metal cofferdam and side wall metal plugging on the bonding surface to reduce costs while improving the airtightness of the cavity, and can achieve the same reliability standards as metal bonding.

[0115] In the chip packaging structure and the chip packaging method of the present invention, the cover plate adopts a silicon cover plate, which is easy to process and has low cost.

[0116] The chip packaging structure and chip packaging method of the present invention, the annular metal cofferdam or the sidewall metal blocking method can be randomly added during the chip packaging process without adding new processes and equipment, and there is no need to purchase high-cost bonding equipment separately.

[0117] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0118] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A chip module is arranged on the surface of the substrate, the chip module comprises a chip and a cover plate, the chip has a functional area, the cover plate covers the functional area and forms a cavity, a polymer bonding layer is formed between the cover plate and the chip, an annular metal cofferdam is formed in the polymer bonding layer, and the functional area is located within the range surrounded by the annular metal cofferdam; A first metal layer, formed at least on the peripheral surface of the chip module and covering the polymer bonding layer; A plastic package is formed on the surface of the substrate and covers the chip module and the first metal layer.

2. The chip packaging structure according to claim 1, characterized in that: The first metal layer completely covers the peripheral surface of the chip module; or, The first metal layer completely covers the peripheral surface of the chip module and extends to a surface of the chip module facing away from the substrate; or, The first metal layer completely covers the peripheral surface of the chip module and extends to completely cover a surface of a side of the chip module away from the substrate.

3. The chip packaging structure according to claim 1, characterized in that: The thickness of the first metal layer is less than or equal to 1 μm; and / or; The polymer bonding layer comprises a glue bonding layer; and / or The annular metal cofferdam is an annular inorganic metal cofferdam; and / or The first metal layer is an inorganic metal layer.

4. The chip packaging structure according to claim 1, characterized in that: The chip has a first surface, the functional area is formed on the first surface, a first bonding area is formed on the first surface, and the first bonding area is arranged around the functional area; The cover plate is disposed on the first surface of the chip, and the cover plate has a second bonding area bonded to the first bonding area; The polymer bonding layer is disposed between the first bonding region and the second bonding region; The annular metal dam is disposed on the first bonding area and / or the second bonding area and is located within the polymer bonding layer.

5. The chip packaging structure according to claim 1, characterized in that: A circuit structure is formed in the substrate; A conductive structure is formed on a side of the chip facing away from the cover plate, and the conductive structure is electrically connected to the circuit structure.

6. A chip packaging method, characterized in that: include: A chip module is provided, the chip module comprising a chip and a cover plate, the chip having a functional area, the cover plate covering the functional area and forming a cavity, a polymer bonding layer formed between the cover plate and the chip, an annular metal cofferdam formed in the polymer bonding layer, and the functional area is located within a range enclosed by the annular metal cofferdam; Providing a temporary substrate, and placing one or more chip modules on the temporary substrate, wherein the chip side of the chip module is in contact with the temporary substrate; forming a first metal layer covering the chip module on the temporary substrate; Peeling off the temporary substrate and the chip module; Providing a substrate, and placing the chip module on a surface of the substrate; A plastic package covering the chip module and the first metal layer is formed on the surface of the substrate.

7. A chip packaging structure, characterized in that: include: substrate; A chip module is arranged on the surface of the substrate, the chip module comprises a chip and a cover plate, the chip has a functional area, the cover plate covers the functional area and forms a cavity, a polymer bonding layer is formed between the cover plate and the chip, an annular metal cofferdam is formed in the polymer bonding layer, and the functional area is located within the range surrounded by the annular metal cofferdam; A plastic package is formed on the surface of the substrate and covers the chip module; The second metal layer is formed on the surface of the plastic package body and extends to the peripheral surface of the substrate.

8. The chip packaging structure according to claim 7, characterized in that: The annular metal cofferdam is an annular inorganic metal cofferdam; and / or The second metal layer is an inorganic metal layer; and / or The polymer bonding layer includes a glue bonding layer.

9. The chip packaging structure according to claim 7, characterized in that: The chip has a first surface, the functional area is formed on the first surface, a first bonding area is formed on the first surface, and the first bonding area is arranged around the functional area; The cover plate is disposed on the first surface of the chip, and the cover plate has a second bonding area bonded to the first bonding area; The polymer bonding layer is disposed between the first bonding region and the second bonding region; The annular metal dam is disposed on the first bonding area and / or the second bonding area and is located within the polymer bonding layer.

10. The chip packaging structure according to claim 7, characterized in that: A circuit structure is formed in the substrate; A conductive structure is formed on a side of the chip facing away from the cover plate, and the conductive structure is electrically connected to the circuit structure.

11. A chip packaging method, characterized in that: include: A chip module is provided, the chip module comprising a chip and a cover plate, the chip having a functional area, the cover plate covering the functional area and forming a cavity, a polymer bonding layer formed between the cover plate and the chip, an annular metal cofferdam formed in the polymer bonding layer, and the functional area is located within a range enclosed by the annular metal cofferdam; Providing a substrate, and placing the chip module on a surface of the substrate; Forming a plastic package covering the chip module on the surface of the substrate; Providing a temporary substrate, placing one or more plastic-encapsulated chip modules on the temporary substrate, wherein the base is bonded to the temporary substrate; forming a second metal layer covering the plastic-sealed chip module on the temporary substrate; The temporary substrate is removed.

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