Reconfigurable logic unit based on ferroelectric transistor, control method and reconfigurable logic system

Abstract

The invention discloses a reconfigurable logic unit based on a ferroelectric transistor, a control method and a reconfigurable logic system, and belongs to the technical field of integrated circuit design. The reconfigurable logic unit comprises a P-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a first N-type FeFET, a second N-type FeFET and a third N-type FeFET; wherein the first N-type FeFET and the second N-type FeFET are connected in parallel, drain electrodes of the first N-type FeFET and the second N-type FeFET are connected with a drain electrode of the P-type MOSFET, and source electrodes of the first N-type FeFET and the second N-type FeFET are connected with a drain electrode of the third N-type FeFET; the source electrode of the third N-type FeFET is grounded; according to the reconfigurable logic unit, the grid electrode of the N-FeFET serves as an input terminal, the polarization characteristic of a ferroelectric device is fully utilized, high-state threshold voltage and low-state threshold voltage can be separated under the control of polarization voltage, logic reconfiguration is achieved, and the reconfigurable logic unit has the advantages of being small in layout area, low in calculation power consumption, high in reconfiguration capacity, compatible with a CMOS, easy to process integration and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and more specifically, relates to a reconfigurable logic unit based on ferroelectric transistors, a control method and a reconfigurable logic system. Background Art

[0002] The "storage wall" of the von Neumann architecture limits the improvement of chip computing performance. Existing VLSI chips face computing power and energy efficiency bottlenecks. The energy efficiency requirements of high-performance computing chips differ by 2 to 3 orders of magnitude from the energy efficiency computing power that the current von Neumann architecture can provide. Therefore, large-capacity, non-volatile memory devices and non-von architecture technologies are urgently needed to improve chip computing power and energy efficiency. Research shows that among many new non-volatile memories, ferroelectric transistors FeFET have potential huge advantages in power consumption, and can achieve a structure similar to 3D NAND Flash, with potential high integration advantages. Therefore, hafnium-based ferroelectric transistors with short access time, low power consumption, and compatibility with advanced manufacturing have become the most promising candidates for new non-volatile memories.

[0003] In recent years, the research on ferroelectric materials devices and chips has been an important high-tech field in microelectronics research. There are many research reports on FeFET in the fields of non-volatile memory, neural networks, reconfigurable devices, etc. In particular, since the first CMOS process-compatible hafnium-based ferroelectric transistor was proposed in 2011, the research on ferroelectric logic units and logic reconstruction has continued to deepen. For example, in the article "Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security" published by Sourav Dutta et al. in IEEE Transactions on Electron Devices, a circuit module based on 8 FeFETs was proposed for the first time, and a reconfigurable NOR / NAND / XNOR logic gate was realized by programming the threshold voltage of FeFET. Although the design takes logic reconstruction into consideration, the layout area and power consumption cost are large, and the designed structural unit has weak reconstruction capability, which only supports the reconstruction of 3 types of logic, and does not maximize the circuit flexibility advantage brought by reconstruction. Summary of the invention

[0004] In view of the above defects or improvement needs of the prior art, the present invention provides a reconfigurable logic unit, a control method and a reconfigurable logic system based on ferroelectric transistors, the purpose of which is to provide a reconfigurable logic unit with small layout area, low computing power consumption and strong reconstruction capability.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a reconfigurable logic unit based on ferroelectric transistors, comprising: a P-type MOSFET, a first N-type FeFET, a second N-type FeFET and a third N-type FeFET;

[0006] The first N-type FeFET and the second N-type FeFET are connected in parallel, the drains of the two are connected to the drain of the P-type MOSFET, and the sources of the two are connected to the drain of the third N-type FeFET; the source of the third N-type FeFET is grounded;

[0007] The gates of the P-type MOSFET and each N-type FeFET serve as the input end of the reconfigurable logic unit, and are used to receive control signals to control the on-off state of the P-type MOSFET, the polarization state of each N-type FeFET, and the on-off state under the polarization state, so that the reconfigurable logic unit performs the target logic operation; the drain of the P-type MOSFET serves as the output end of the reconfigurable logic unit.

[0008] In a second aspect, the present invention provides a control method for the above-mentioned reconfigurable logic unit, including: controlling the on-off state of the P-type MOSFET in the reconfigurable logic unit, the polarization state of each N-type FeFET and the on-off state under the polarization state, so that the reconfigurable logic unit performs the target logic operation.

[0009] Further preferably, the types of the target logic operation include: true logic operation, false logic operation and logic operation performed on input logic value; wherein the input logic value includes: logic value p and / or logic value q;

[0010] The source and gate of the P-type MOSFET are denoted as the S terminal and the G terminal; the gate of any one of the first N-type FeFET and the second N-type FeFET is denoted as the A terminal, and the gate of the other N-type FeFET is denoted as the B terminal; the gate of the third N-type FeFET is denoted as the E terminal; the drain of the P-type MOSFET is the output terminal of the reconfigurable logic unit;

[0011] The above control method includes:

[0012] When the target logic operation is a true logic operation, the positive power supply voltage VDD is connected to the S terminal, and a low level voltage is applied to the G terminal;

[0013] When the target logic operation is a false logic operation, the S terminal is grounded;

[0014] When the target logic operation is p logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal and E terminal respectively, and negative polarization voltage is applied to the B terminal; then the logic voltage signal is applied to the A terminal Apply a high level voltage or a low level voltage to the B terminal, a high level voltage to the E terminal, and a low level voltage to the G terminal;

[0015] When the target logic operation is q logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the B and E terminals respectively, and negative polarization voltage is applied to the A terminal; then a high level voltage or a low level voltage is applied to the A terminal, and a logic voltage signal is applied to the B terminal. Apply a high level voltage to the E terminal and a high level voltage to the G terminal;

[0016] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal and the E terminal respectively, and a negative polarization voltage is applied to the B terminal; then the logic voltage signal p is applied to the A terminal, a high level voltage or a low level voltage is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal;

[0017] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the B terminal and the E terminal respectively, and a negative polarization voltage is applied to the A terminal; then a high level voltage or a low level voltage is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal;

[0018] When the target logic operation is During logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal, the B terminal, and the E terminal respectively; then a logic voltage signal p is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal;

[0019] When the target logic operation is p·q logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal, B terminal, and E terminal respectively; then the logic voltage signal is applied to the A terminal Apply a logic voltage signal to terminal B Apply a high level voltage to the E terminal and a high level voltage to the G terminal;

[0020] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal, B terminal, and E terminal respectively; then the logic voltage signal is applied to the A terminal. Apply a logic voltage signal q to the B terminal, a high level voltage to the E terminal, and a high level voltage to the G terminal;

[0021] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal, B terminal, and E terminal respectively; then the logic voltage signal p is applied to the A terminal, and the logic voltage signal is applied to the B terminal. Apply a high level voltage to the E terminal and a high level voltage to the G terminal;

[0022] When the target logic operation is During logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal and the E terminal respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a low level voltage is applied to the B terminal, a logic voltage signal q is applied to the E terminal, and a high level voltage is applied to the G terminal;

[0023] When the target logic operation is p+q logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal and E terminal respectively, and negative polarization voltage is applied to the B terminal; then the logic voltage signal is applied to the A terminal Apply a low level voltage to the B terminal and a logic voltage signal to the E terminal Apply a high level voltage to the G terminal;

[0024] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal and E terminal respectively, and negative polarization voltage is applied to the B terminal; then the logic voltage signal is applied to the A terminal. Apply a low level voltage to the B terminal, a logic voltage signal q to the E terminal, and a high level voltage to the G terminal;

[0025] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal and the E terminal respectively, and negative polarization voltage is applied to the B terminal; then the logic voltage signal p is applied to the A terminal, a low level voltage is applied to the B terminal, and a logic voltage signal is applied to the E terminal. Apply a high level voltage to the G terminal.

[0026] Further preferably, when the logic value p is 1, the logic voltage signal p is a high level voltage, and the logic voltage signal is a low level voltage; when the logic value p is 0, the logic voltage signal p is a low level voltage, and the logic voltage signal is a high level voltage;

[0027] When the logic value q is 1, the logic voltage signal q is a high level voltage, and the logic voltage signal is a low level voltage; when the logic value q is 0, the logic voltage signal q is a low level voltage, and the logic voltage signal is a high level voltage.

[0028] Further preferably, in each logic operation, after the operation of applying corresponding polarization voltages at different terminals is completed, the operation of applying corresponding level voltages at different terminals is performed in parallel.

[0029] Further preferably, in each logic operation, operations of applying corresponding polarization voltages at different ends are performed in parallel.

[0030] Further preferably, when the output signal of the reconfigurable logic unit is a high level voltage, the result of the target logic operation is 1; when the output signal of the reconfigurable logic unit is a low level voltage, the result of the target logic operation is 0.

[0031] In a third aspect, the present invention provides a reconfigurable logic system, comprising: a controller, and the reconfigurable logic unit provided in the first aspect of the present invention;

[0032] The controller is used to execute the control method provided in the second aspect of the present invention.

[0033] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0034] 1. The present invention provides a reconfigurable logic unit based on ferroelectric transistors, including a P-type MOSFET and three N-type FeFETs; among the three N-FeFETs, two N-FeFETs are connected in parallel, and their drains are connected to the drains of the P-MOSFETs, and their sources are connected to the drains of the other N-FeFETs. The reconfigurable logic unit uses the gate of the N-FeFET as a logic input terminal, and by making full use of the polarization characteristics of the ferroelectric device, it can separate the high and low state threshold voltages under the control of the polarization voltage. It can realize the dynamic reconstruction of 14 kinds of Boolean logics only through one P-type MOSFET and three N-type FeFETs, and has the advantages of small layout area, low computing power consumption, strong reconstruction capability, compatibility with CMOS, and easy process integration.

[0035] 2. The present invention provides a control method for a reconfigurable logic unit, which can flexibly input corresponding voltage signals into the gates of the P-type MOSFET and each N-type FeFET according to the type of logic operation to be implemented, thereby realizing up to 14 types of logic reconstruction, and can effectively solve the problems of device circuit rigidification and lack of flexibility.

[0036] 3. Furthermore, the present invention provides a control method for a reconfigurable logic unit. In each logic operation, after the operation of applying corresponding polarization voltages at different ends is performed in parallel, the operation of applying corresponding level voltages at different ends is performed in parallel. A logic reconstruction and logic calculation can be completed in two steps without adding a separate calculation result reading step, which greatly shortens the time spent on the entire logic operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structure of a reconfigurable logic unit based on ferroelectric transistors provided in an embodiment of the present invention;

[0038] Figure 2 Schematic diagram of separation of high-state and low-state threshold voltages of N-FeFET provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0040] In order to achieve the above objectives, firstly, Figure 1 As shown, the present invention provides a reconfigurable logic unit based on ferroelectric transistors, comprising: a P-type MOSFET, a first N-type FeFET, a second N-type FeFET and a third N-type FeFET;

[0041] The first N-type FeFET and the second N-type FeFET are connected in parallel, the drains of the two are connected to the drain of the P-type MOSFET, and the sources of the two are connected to the drain of the third N-type FeFET; the source of the third N-type FeFET is grounded;

[0042] Among them, the gates of the P-type MOSFET and each N-type FeFET serve as the input end of the reconfigurable logic unit (wherein the gate of the ferroelectric transistor serves as the logic signal input end), which is used to receive control signals to adjust the on-off state of the P-type MOSFET, as well as the polarization state of each N-type FeFET and the on-off state under the polarization state, so that the reconfigurable logic unit performs the target logic operation; the drain of the P-type MOSFET serves as the output end of the reconfigurable logic unit.

[0043] The reconfigurable logic unit uses a DC voltage as a logic input signal. When the DC voltage applied to the gate of the N-FeFET is greater than 0V, it corresponds to a logic input "1"; when the DC voltage applied to the gate of the N-FeFET is 0V, it corresponds to a logic input "0".

[0044] The logic unit uses the voltage V at the drain of the P-MOSFET out As a logic output signal. out When it is a high level voltage, the corresponding logic output is "1"; when V out When it is a low level voltage, the corresponding logic output is "0".

[0045] The P-MOSFET is used as a pull-up device of the logic unit, and its on or off state is determined by the voltage applied to its gate. Specifically, when the voltage applied to the gate of the P-MOSFET is a high-level voltage, the P-MOSFET works in a blocking state; when the voltage applied to the gate of the P-MOSFET is a low-level voltage, the P-MOSFET works in an on state.

[0046] Due to the special polarization characteristics of the ferroelectric layer, the conduction or blocking state of N-FeFET is determined by the polarization voltage and logic signal voltage applied to its gate in sequence. Specifically, when the polarization voltage applied to the gate of N-FeFET is a positive voltage: if the DC voltage continued to be applied to its gate is a high level, the N-FeFET works in the conduction state; if the DC voltage continued to be applied to its gate is a low level, the N-FeFET works in the blocking state; when the polarization voltage applied to the gate of N-FeFET is a negative voltage: if the DC voltage continued to be applied to its gate is a high level, the N-FeFET works in the blocking state; if the DC voltage continued to be applied to its gate is a low level, the N-FeFET works in the blocking state.

[0047] This is because the polarization voltage can change the polarization state of the ferroelectric layer inside the transistor, causing the threshold voltage of the N-FeFET transistor to shift, resulting in the separation of the high-state and low-state threshold voltages, such as Figure 2 Specifically, when the polarization voltage applied to the gate of the N-FeFET is a forward voltage, the threshold voltage of the N-FeFET shifts to the left, forming a low threshold voltage V TL ; When the polarization voltage applied to the gate of N-FeFET is negative, the threshold voltage of N-FeFET shifts to the right, forming a high threshold voltage V TH The shift of the threshold voltage will cause the N-FeFET to have two possible states: on or off when a logic input signal is applied, thus producing different logic calculation results. The above-mentioned reconfigurable logic unit uses this point to complete the logic reconstruction design.

[0048] When performing a logic calculation, the logic unit needs to be configured according to the logic function, including applying voltage to the P-MOSFET gate to determine its working state and applying polarization voltage to the N-FeFET gate to determine its polarization state. Then, according to the logic function, the gates of two N-FeFETs are selected from the three N-FeFETs as the selection logic signal input terminals, and a DC voltage signal is applied to complete the logic calculation.

[0049] The configurations and logic signal input terminals of the 14 logics that can be realized by the reconfigurable logic unit provided by the present invention are given in Table 1. Among them, "A", "B", and "E" represent optional logic input terminals. Specifically, "A" represents the gate of any one N-type FeFET selected from the first N-type FeFET and the second N-type FeFET, "B" represents the gate of another N-type FeFET in the first N-type FeFET and the second N-type FeFET, and "E" represents the gate of the third N-type FeFET. "p", "q", Indicates the logic input signal, "A", "B", "V p "1" in the "C", "D", and "F" columns indicate the direction of the polarization voltage applied to the N-FeFET. "1" in the "C", "D", and "F" columns indicates the application of a positive polarization voltage, and "0" indicates the application of a negative polarization voltage. V p It represents the gate bias of P-MOSFET, that is, the signal applied to the gate (G terminal) of P-type MOSFET.

[0050] Table 1

[0051]

[0052]

[0053] When the gates of two parallel N-FeFETs are selected as input terminals, the reconfigurable logic cell can realize 10 reconfigurable Boolean logics: logic "1", logic "0", logic "p", logic "q", logic logic logic Logic "p·q", logic logic At this time, the N-FeFET connected in series always remains in the on state.

[0054] When the gates of two series-connected N-FeFETs are selected as input terminals of the reconfigurable logic cell, the logic cell can realize the remaining four reconfigurable Boolean logics: logic Logical "p+q", logical logic At this time, the N-FeFET connected in parallel always remains in a blocked state.

[0055] It should be noted that the above logic "1" is a true logic operation, logic "0" is a false logic operation, logic "p" is a p logic operation, logic "q" is a q logic operation, and logic That is Logical operation, logic That is Logical operation, logic That is Logical operation, logic "p·q" is p·q logical operation, logic That is Logical operation, logic That is Logical operation, logic That is Logical operation, logical "p+q" is p+q logical operation, logical That is Logical operation, logic That is Logical operations.

[0056] When the reconfigurable logic cell performs a logic "1" operation, the P-MOSFET is in the on state, and when other logic operations are performed, the P-MOSFET remains in the off state.

[0057] In view of the reconfigurable logic unit provided in the first aspect, the second aspect of the present invention provides a control method thereof, including: controlling the on-off state of the P-type MOSFET, the polarization state of each N-type FeFET and the on-off state under the polarization state in the reconfigurable logic unit, so that the reconfigurable logic unit performs a target logic operation. The types of the target logic operation include: true logic operation, false logic operation and logic operation on input logic values; the input logic values ​​include: logic value p and / or logic value q;

[0058] In an optional implementation manner, the above control method specifically includes:

[0059] When the target logic operation is a true logic operation, the positive power supply voltage VDD is connected to the S terminal, and a low level voltage is applied to the G terminal;

[0060] When the target logic operation is a false logic operation, the S terminal is grounded;

[0061] When the target logic operation is p logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal and E terminal respectively, and negative polarization voltage is applied to the B terminal; then the logic voltage signal is applied to the A terminal Apply a high level voltage or a low level voltage to the B terminal, a high level voltage to the E terminal, and a low level voltage to the G terminal;

[0062] When the target logic operation is q logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the B and E terminals respectively, and negative polarization voltage is applied to the A terminal; then a high level voltage or a low level voltage is applied to the A terminal, and a logic voltage signal is applied to the B terminal. Apply a high level voltage to the E terminal and a high level voltage to the G terminal;

[0063] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal and the E terminal respectively, and a negative polarization voltage is applied to the B terminal; then the logic voltage signal p is applied to the A terminal, a high level voltage or a low level voltage is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal;

[0064] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the B terminal and the E terminal respectively, and a negative polarization voltage is applied to the A terminal; then a high level voltage or a low level voltage is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal;

[0065] When the target logic operation is During logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal, the B terminal, and the E terminal respectively; then a logic voltage signal p is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal;

[0066] When the target logic operation is p·q logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal, B terminal, and E terminal respectively; then the logic voltage signal is applied to the A terminal Apply a logic voltage signal to terminal B Apply a high level voltage to the E terminal and a high level voltage to the G terminal;

[0067] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal, B terminal, and E terminal respectively; then the logic voltage signal is applied to the A terminal. Apply a logic voltage signal q to the B terminal, a high level voltage to the E terminal, and a high level voltage to the G terminal;

[0068] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal, B terminal, and E terminal respectively; then the logic voltage signal p is applied to the A terminal, and the logic voltage signal is applied to the B terminal. Apply a high level voltage to the E terminal and a high level voltage to the G terminal;

[0069] When the target logic operation is During logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal and the E terminal respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a low level voltage is applied to the B terminal, a logic voltage signal q is applied to the E terminal, and a high level voltage is applied to the G terminal;

[0070] When the target logic operation is p+q logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal and E terminal respectively, and negative polarization voltage is applied to the B terminal; then the logic voltage signal is applied to the A terminal Apply a low level voltage to the B terminal and a logic voltage signal to the E terminal Apply a high level voltage to the G terminal;

[0071] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltage is applied to the A terminal and E terminal respectively, and negative polarization voltage is applied to the B terminal; then the logic voltage signal is applied to the A terminal. Apply a low level voltage to the B terminal, a logic voltage signal q to the E terminal, and a high level voltage to the G terminal;

[0072] When the target logic operation is During logic operation, the positive power supply voltage VDD is connected to the S terminal in advance, and positive polarization voltages are applied to the A terminal and the E terminal respectively, and negative polarization voltage is applied to the B terminal; then the logic voltage signal p is applied to the A terminal, a low level voltage is applied to the B terminal, and a logic voltage signal is applied to the E terminal. Apply a high level voltage to the G terminal.

[0073] In an optional implementation manner, when the logic value p is 1, the logic voltage signal p is a high level voltage, and the logic voltage signal is a low level voltage; when the logic value p is 0, the logic voltage signal p is a low level voltage, and the logic voltage signal is a high level voltage;

[0074] When the logic value q is 1, the logic voltage signal q is a high level voltage, and the logic voltage signal is a low level voltage; when the logic value q is 0, the logic voltage signal q is a low level voltage, and the logic voltage signal is a high level voltage.

[0075] In an optional implementation manner, when the output signal of the reconfigurable logic unit is a high level voltage, the result of the logic operation is 1; when the output signal of the reconfigurable logic unit is a low level voltage, the result of the logic operation is 0.

[0076] Preferably, the polarization voltage and the logic voltage signal applied to the gate of the N-FeFET are serially input, and the voltage applied to the gate of the P-MOSFET and the logic voltage signal applied to the gate of the N-FeFET are parallel inputs, and only two steps are required to perform a logic reconstruction and logic calculation. Specifically, in an optional implementation, in each logic operation, after the operation of applying the corresponding polarization voltage at different ends is performed, the operation of applying the corresponding level voltage at different ends is performed in parallel. In an optional implementation, in each logic operation, the operation of applying the corresponding polarization voltage at different ends is performed in parallel.

[0077] In an optional implementation manner, the high level voltage is 1 to 1.2 V, and the low level voltage is 0 to 0.2 V. Preferably, the high level voltage is set to 1 V, and the low level voltage is set to 0 V.

[0078] In an optional implementation, the positive polarization voltage is 3 to 5 V, and the negative polarization voltage is -5 to -3 V. Preferably, the positive polarization voltage is 4 V, and the negative polarization voltage is -4 V.

[0079] In an optional implementation manner, the positive power supply voltage VDD is 1.5V.

[0080] In a third aspect, the present invention provides a reconfigurable logic system, comprising: a controller, and the reconfigurable logic unit provided in the first aspect of the present invention;

[0081] The controller is used to execute the control method provided in the second aspect of the present invention.

[0082] The related technical solutions are the same as the reconfigurable logic unit provided in the first aspect of the present invention and the control method provided in the second aspect of the present invention, and are not described in detail here.

[0083] The present invention provides a reconfigurable logic unit design based on ferroelectric transistors, which flexibly uses the gate of the ferroelectric transistor as an input terminal, fully utilizes the polarization characteristics of the ferroelectric device, and realizes logic reconstruction by applying polarization voltage to control the separation of high-state and low-state threshold voltages.

[0084] Compared with traditional CMOS logic gates, the reconfigurable logic unit provided by the present invention has the advantages of small area, low power consumption, easy process integration and dynamic reconfiguration, providing technical support for the development of low-power reconfigurable logic circuit systems.

[0085] Compared with other reconfigurable logic gates, the reconfigurable logic unit provided by the present invention can complete a logic reconstruction and logic calculation in two steps, without adding a separate calculation result reading step, which greatly shortens the time spent on the entire logic operation. At the same time, it has a strong reconstruction capability and can complete up to 14 types of logic reconstruction, which can effectively solve the problem of device circuit solidification and lack of flexibility.

[0086] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A reconfigurable logic unit based on ferroelectric transistors, characterized in that: include: A P-type MOSFET, a first N-type FeFET, a second N-type FeFET, and a third N-type FeFET; The first N-type FeFET and the second N-type FeFET are connected in parallel, the drains of both are connected to the drain of the P-type MOSFET, and the sources of both are connected to the drain of the third N-type FeFET; the source of the third N-type FeFET is grounded; The gates of the P-type MOSFET and each of the N-type FeFETs are used to receive control signals to control the on-off state of the P-type MOSFET and the polarization state and the on-off state under the polarization state of each of the N-type FeFETs, so that the reconfigurable logic unit performs the target logic operation; the drain of the P-type MOSFET serves as the output end of the reconfigurable logic unit.

2. The control method of the reconfigurable logic unit according to claim 1, characterized in that: include: The on-off state of the P-type MOSFET, the polarization state of each N-type FeFET, and the on-off state under the polarization state in the reconfigurable logic unit are controlled to enable the reconfigurable logic unit to perform a target logic operation.

3. The control method according to claim 2, characterized in that: The types of the target logic operation include: true logic operation, false logic operation and logic operation performed on input logic value; the input logic value includes: logic value p and / or logic value q; The source and gate of the P-type MOSFET are denoted as the S terminal and the G terminal; the gate of any one of the first N-type FeFET and the second N-type FeFET in the reconfigurable logic unit is denoted as the A terminal, and the gate of the other N-type FeFET is denoted as the B terminal; the gate of the third N-type FeFET in the reconfigurable logic unit is denoted as the E terminal; The control method comprises: When the target logic operation is a true logic operation, a positive power supply voltage VDD is connected to the S terminal, and a low level voltage is applied to the G terminal; When the target logic operation is a false logic operation, grounding the S terminal; When the target logic operation is a p logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and a positive polarization voltage is applied to the A terminal and the E terminal respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal is applied to the A terminal. Apply a high level voltage or a low level voltage to the B terminal, apply a high level voltage to the E terminal, and apply a high level voltage to the G terminal; When the target logic operation is a q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the B terminal and the E terminal, respectively, and a negative polarization voltage is applied to the A terminal; then a high level voltage or a low level voltage is applied to the A terminal, and a logic voltage signal is applied to the B terminal. Apply a high level voltage to the E terminal and a high level voltage to the G terminal; When the target logic operation is During logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A terminal and the E terminal, respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a high level voltage or a low level voltage is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal; When the target logic operation is During logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the B terminal and the E terminal, respectively, and a negative polarization voltage is applied to the A terminal; then a high level voltage or a low level voltage is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal; When the target logic operation is During logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A terminal, the B terminal, and the E terminal, respectively; then a logic voltage signal p is applied to the A terminal, a logic voltage signal q is applied to the B terminal, a high level voltage is applied to the E terminal, and a high level voltage is applied to the G terminal; When the target logic operation is a p·q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and a positive polarization voltage is applied to the A terminal, the B terminal, and the E terminal respectively; then a logic voltage signal is applied to the A terminal. Apply a logic voltage signal at the B terminal Apply a high level voltage to the E terminal and a high level voltage to the G terminal; When the target logic operation is During logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal, the B terminal and the E terminal respectively; then a logic voltage signal is applied to the A terminal. Apply a logic voltage signal q to the B terminal, apply a high level voltage to the E terminal, and apply a high level voltage to the G terminal; When the target logic operation is During logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal, the B terminal, and the E terminal respectively; then a logic voltage signal p is applied to the A terminal, and a logic voltage signal is applied to the B terminal. Apply a high level voltage to the E terminal and a high level voltage to the G terminal; When the target logic operation is During logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A terminal and the E terminal, respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a low level voltage is applied to the B terminal, a logic voltage signal q is applied to the E terminal, and a high level voltage is applied to the G terminal; When the target logic operation is a p+q logic operation, a positive power supply voltage VDD is pre-connected to the S terminal, and positive polarization voltages are applied to the A terminal and the E terminal, respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal is applied to the A terminal. A low level voltage is applied to the B terminal and a logic voltage signal is applied to the E terminal. Applying a high level voltage to the G terminal; When the target logic operation is During logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal and the E terminal respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal is applied to the A terminal. Apply a low level voltage to the B terminal, apply a logic voltage signal q to the E terminal, and apply a high level voltage to the G terminal; When the target logic operation is During logic operation, a positive power supply voltage VDD is connected to the S terminal in advance, and a positive polarization voltage is applied to the A terminal and the E terminal respectively, and a negative polarization voltage is applied to the B terminal; then a logic voltage signal p is applied to the A terminal, a low level voltage is applied to the B terminal, and a logic voltage signal is applied to the E terminal. A high level voltage is applied to the G terminal.

4. The control method according to claim 3, characterized in that: When the logic value p is 1, the logic voltage signal p is a high level voltage. is a low level voltage; when the logic value p is 0, the logic voltage signal p is a low level voltage, the logic voltage signal is a high level voltage; When the logic value q is 1, the logic voltage signal q is a high level voltage. is a low level voltage; when the logic value q is 0, the logic voltage signal q is a low level voltage, and the logic voltage signal is a high level voltage.

5. The control method according to any one of claim 4, characterized in that: In each logic operation, after the operation of applying the corresponding polarization voltage at different terminals is completed, the operation of applying the corresponding level voltage at different terminals is performed in parallel.

6. The control method according to claim 5, characterized in that: In each logic operation, the operation of applying corresponding polarization voltages at different terminals is performed in parallel.

7. The control method according to any one of claims 2 to 6, characterized in that: When the output signal of the reconfigurable logic unit is a high level voltage, the result of the target logic operation is 1; when the output signal of the reconfigurable logic unit is a low level voltage, the result of the target logic operation is 0.

8. A reconfigurable logic system, characterized in that: include: A controller, and a reconfigurable logic unit as claimed in claim 1; The controller is used to execute the control method described in any one of claims 2-7.

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