N-channel enhanced gallium nitride transistor structure and manufacturing method thereof
By adopting a multi-layer structure and a polysilicon gate in a gallium nitride transistor, the problem of voltage and size adaptation of gallium nitride transistors in consumer wireless communication devices is solved, and a small-size device with high performance and low power consumption is realized.
Patent Information
- Application Number
- CN202411584855.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2025-02-14
AI Technical Summary
GaN transistors are used in consumer wireless communication devices due to voltage and structural size limitations, making it difficult to meet the needs of low power consumption and small volumes.
Using an N-channel enhanced gallium nitride transistor structure, a multi-layer structure is formed on the epitaxial chip, including a channel layer, a gate dielectric layer, a gate, a barrier layer and a side wall, combined with polysilicon as a gate metal, to achieve a small amount of Size, high performance devices.
Low voltage operation and small size N-channel enhanced gallium nitride transistors are achieved, reducing the operating voltage and size of the device while improving circuit density and system integration.
Smart Images
Figure CN119451167A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to an N-channel enhancement-type gallium nitride transistor structure and a manufacturing method thereof. Background Art
[0002] With the rapid development of modern electronic technology, the demand for high-performance, low-power electronic devices is growing. Gallium nitride (GaN), as a new type of semiconductor material, has shown great application potential in the fields of RF power amplifiers, power electronic circuits, etc. due to its excellent physical and chemical properties, such as high breakdown electric field strength, high saturated electron mobility and high thermal conductivity.
[0003] Traditional GaN transistors, although they have high current drive capability and good RF performance, have relatively high operating voltages and large transistor sizes, which limits their use in general consumer wireless communication devices, as these devices usually use silicon integrated circuits in low-voltage power supply mode to accommodate smaller size and lower power consumption requirements.
[0004] If the excellent performance of GaN transistors is to be introduced into consumer wireless communication devices such as mobile phones and wireless routers, the problems of high operating voltage and large size must be solved. The use of enhanced GaN devices can not only effectively meet this challenge, but also simplify circuit design and reduce costs. In addition, enhanced GaN transistors are more compatible with existing CMOS processes, making it possible to realize all-GaN circuits.
[0005] All-GaN circuits are an attractive development direction, especially in the field of high-density GaN digital circuits. Small-sized, low-voltage N-channel enhancement-type GaN devices are key components to achieve this goal. They not only provide high performance and low power consumption, but also significantly reduce circuit size and improve system integration. Therefore, the development of a small-sized, low-voltage N-channel enhancement-type GaN transistor device is of great significance to promoting the application of GaN technology in consumer wireless communication devices. Summary of the invention
[0006] The purpose of the present invention is to provide an N-channel enhancement-type gallium nitride transistor structure and a manufacturing method thereof, so as to solve the voltage and structural size adaptation problem of gallium nitride devices used in consumer-grade wireless communication devices.
[0007] The purpose of the present invention can be achieved through the following technical solutions:
[0008] An N-channel enhancement-mode gallium nitride transistor structure, comprising:
[0009] an epitaxial wafer including a channel layer;
[0010] A gate dielectric layer, formed on the channel layer;
[0011] A gate, formed above the gate dielectric layer;
[0012] Barrier layers, formed on both sides of the gate dielectric layer;
[0013] Gate sidewalls, formed on both sides of the gate and connected to the barrier layers;
[0014] A source and a drain, formed above the channel layer and located outside the gate sidewalls on both sides.
[0015] As a further aspect of the present invention: The epitaxial wafer includes a substrate, a nucleation layer is disposed above the substrate, a buffer layer is disposed above the nucleation layer, a high-resistance layer is disposed above the buffer layer, and a channel layer is disposed above the high-resistance layer.
[0016] As a further aspect of the present invention: The bottom of the barrier layer is connected to the channel layer, the inner ends of the barrier layer are connected to the gate dielectric layer and the gate sidewalls, the source and the drain pass through the barrier layer and are connected to the channel layer, and the outer ends of the barrier layer are connected to the corresponding source or drain.
[0017] As a further aspect of the present invention: The nucleation layer is a gallium nitride layer or an aluminum nitride layer, the buffer layer is an Al X GaN layer, where 0 < x < 1, the high-resistance layer is a gallium nitride layer doped with iron or carbon, and the channel layer is a gallium nitride layer with a thickness of 100 - 500 nm.
[0018] As a further aspect of the present invention: The gate dielectric layer is a silicon nitride layer with a thickness of 5 - 20 nm.
[0019] As a further aspect of the present invention: The barrier layer is an Al z Ga 1-z N layer, where 0.2 < z < 0.4 and the thickness is 10 - 20 nm.
[0020] As a further aspect of the present invention: The gate is a polysilicon layer with a thickness of 500 - 1000 nm, and the gate sidewalls are a single-layer silicon dioxide or a multi-layer structure of silicon dioxide / silicon nitride with a thickness of 200 - 500 nm.
[0021] As a further aspect of the present invention: Both the source and the drain are Ti / Al / Ti / TiN stacked structures.
[0022] As a further solution of the present invention: a method for manufacturing an N-channel enhancement-mode gallium nitride transistor structure, characterized in that the method is used to manufacture the above-mentioned N-channel enhancement-mode gallium nitride transistor structure, comprising the following steps:
[0023] Step 1: providing or preparing an epitaxial wafer;
[0024] Step 2: deposit silicon nitride on the channel layer to form a gate dielectric layer, then deposit polysilicon to form a gate, then perform photolithography on the gate pattern, and etch the polysilicon to form a polysilicon gate strip;
[0025] Step 3: Oxidize the polysilicon to form a silicon oxide layer of a certain thickness on the outer layer of the gate, and then use a wet etching process to remove the silicon nitride dielectric in the source and drain regions;
[0026] Step 4: selectively epitaxially grow a barrier layer in the source and drain regions;
[0027] Step 5: deposit a sidewall dielectric layer to form a gate sidewall, and then etch back to the channel layer and the top of the gate;
[0028] Step 6: depositing source and drain metal layers, removing the source and drain metal layers on the gate by a planarization process, and performing annealing to form source and drain ohmic contacts, thereby forming source and drain electrodes;
[0029] Step 7: After that, an intermetallic dielectric layer is deposited, and then the rear-end through-hole and metal interconnection processes are completed to finally form an N-channel enhancement-mode gallium nitride transistor device.
[0030] As a further solution of the present invention: a method for manufacturing an N-channel enhancement-mode gallium nitride transistor structure, characterized in that the method is used to manufacture the above-mentioned N-channel enhancement-mode gallium nitride transistor structure, comprising the following steps:
[0031] Step 1: providing or preparing an epitaxial wafer;
[0032] Step 2: deposit silicon nitride on the channel layer to form a gate dielectric layer, then deposit polysilicon to form a gate, then perform photolithography on the gate pattern, and etch the polysilicon to form a polysilicon gate strip;
[0033] Step 3: oxidize the polysilicon in step 2 to form a silicon oxide layer of a certain thickness on the outer layer of the gate, and then use a wet etching process to remove the silicon nitride dielectric in the source and drain regions;
[0034] Step 4: selectively epitaxially grow a barrier layer in the source and drain regions;
[0035] Step 5: deposit a sidewall dielectric layer to form a gate sidewall, and then etch back to the barrier layer and the top of the gate;
[0036] Step 6: depositing source and drain metal layers, removing the source and drain metal layers on the gate by a planarization process, and performing annealing to form source and drain ohmic contacts, thereby forming source and drain electrodes;
[0037] Step 7: After that, an intermetallic dielectric layer is deposited, and then the rear-end through-hole and metal interconnection processes are completed to finally form an N-channel enhancement-mode gallium nitride transistor device.
[0038] As a further solution of the present invention: the epitaxial wafer is formed by providing a substrate, and epitaxially growing a core layer, a buffer layer, a high resistance layer and a channel layer in sequence from bottom to top on the surface of the substrate.
[0039] As a further solution of the present invention: the epitaxial wafer is prefabricated.
[0040] Beneficial effects of the present invention:
[0041] The present invention uses polysilicon as the gate metal, which can ensure the performance while taking into account the thickness of the gate, and combines the sidewall process and the self-alignment process to form a small-sized gate-source and gate-drain structure (the gate, source and drain are all separated by the sidewall spacer. Since the sidewall is relatively thin, the gate source and the gate drain can be spaced very small, and the spacing is only controlled by the film thickness. The repeatability of the device structure is relatively high), so that the alignment accuracy between the gate and the source and drain is very high, thereby further reducing the size of the device, reducing the device operating voltage, and further improving the circuit density. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] The present invention will be further described below in conjunction with the accompanying drawings.
[0043] Figure 1 is a schematic diagram of the structure of a transistor manufactured by the method of Embodiment 2 of the present invention;
[0044] Figure 2 It is a schematic diagram of the structure of the epitaxial wafer of the present invention;
[0045] Figure 3 is a schematic structural diagram of forming a gate dielectric layer and a gate in step 2 of embodiment 2 of the present invention;
[0046] Figure 4 It is a schematic diagram of the structure of forming a silicon oxide layer and etching back to the channel layer in step 3 of the second embodiment of the present invention;
[0047] Figure 5 It is a schematic structural diagram of the secondary epitaxial growth barrier layer in step 4 of the second embodiment of the present invention;
[0048] Figure 6 It is a schematic diagram of the structure of forming gate sidewalls and etching back to the channel layer in step five of the second embodiment of the present invention;
[0049] Figure 7 It is a schematic diagram of the structure of forming gate sidewalls and etching back to the barrier layer in step five of embodiment four of the present invention.
[0050] In the figure: 1. substrate; 2. nucleation layer; 3. buffer layer; 4. high resistance layer; 5. channel layer; 6. gate dielectric layer; 7. gate; 8. silicon oxide layer; 9. barrier layer; 10. gate sidewall; 11. source; 12. drain. DETAILED DESCRIPTION
[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0052] Embodiment 1
[0053] like Figure 1 As shown, the present invention provides an N-channel enhancement-type gallium nitride transistor structure, which includes an epitaxial wafer, a gate dielectric layer 6 is arranged in the middle of the epitaxial wafer, barrier layers 9 are arranged on both sides of the gate dielectric layer 6, and a gate 7 is arranged above the gate dielectric layer 6, gate sidewalls 10 are arranged on both sides of the gate 7, the gate sidewalls 10 on both sides are connected to the corresponding barrier layers 9, and source electrodes 11 and drain electrodes 12 are correspondingly arranged on the outer sides of the gate sidewalls 10 on both sides, and the source electrodes 11 and the drain electrodes 12 are formed on the epitaxial wafer.
[0054] Preferably, the epitaxial wafer comprises a substrate 1, a nucleation layer 2, a buffer layer 3, a high resistance layer 4 and a channel layer 5, wherein a nucleation layer 2 is arranged above the substrate 1, a buffer layer 3 is arranged above the nucleation layer 2, a high resistance layer 4 is arranged above the buffer layer 3, and a channel layer 5 is arranged above the high resistance layer 4; the gate dielectric layer 6 is located in the middle above the channel layer 5, the bottoms of the barrier layers 9 on both sides are connected to the channel layer 5, and the inner ends of the barrier layers 9 are connected to the gate dielectric layer 6 and the gate sidewalls 10.
[0055] Preferably, the substrate 1 can be a silicon substrate, a silicon carbide substrate, a sapphire substrate or a diamond substrate, etc. In this embodiment, the substrate 1 is a silicon substrate. By using silicon as a substrate, heteroepitaxial growth of gallium nitride materials can be achieved on large-size wafers, saving the epitaxial growth cost per unit size.
[0056] Preferably, the source electrode 11 and the drain electrode 12 pass through the barrier layer 9 to connect with the channel layer 5 , and the outer end of the barrier layer 9 is connected with the corresponding source electrode 11 or drain electrode 12 .
[0057] Preferably, the nucleation layer 2 may be a gallium nitride layer or an aluminum nitride layer; the buffer layer 3 may be an AlX A GaN layer, where 0 < x < 1; the above-mentioned high-resistance layer 4 can be a gallium nitride layer doped with iron or carbon.
[0058] Preferably, the above-mentioned channel layer 5 is a gallium nitride layer with a thickness of 100 - 500 nm; the above-mentioned gate dielectric layer 6 is a silicon nitride layer, and the film thickness of the gate dielectric layer 6 is set according to the device performance requirements, ranging from 5 - 20 nm; the above-mentioned barrier layer 9 is an Al z Ga 1-z N layer (or a wider bandgap material such as AlN, InAlN, InAlGaN, etc.), where 0.2 < z < 0.4 and the thickness is 10 - 20 nm;
[0059] Preferably, the above-mentioned gate 7 is a polysilicon layer with a thickness of 500 - 1000 nm, and is in-situ doped (such as boron) according to requirements; the above-mentioned gate sidewall 10 can be a single-layer silicon dioxide or a multi-layer structure of silicon dioxide / silicon nitride with a thickness of 200 - 500 nm; the above-mentioned source 11 and drain 12 are both source-drain metal layers, and the source-drain metal layer can adopt a Ti / Al / Ti / TiN stacked structure.
[0060] Embodiment 2
[0061] As Figure 1-Figure 6 shown, the present invention provides a manufacturing method for an N-channel enhancement-mode gallium nitride transistor structure, and the manufacturing method includes the following steps:
[0062] Step 1: Prepare an epitaxial wafer by providing a substrate 1 and epitaxially growing a nucleation layer 2, a buffer layer 3, a high-resistance layer 4, and a channel layer 5 on the surface of the substrate 1 from bottom to top to form an epitaxial wafer;
[0063] Step 2: Deposit high-temperature silicon nitride on the channel layer 5 of the epitaxial wafer to form a gate dielectric layer 6, where the deposition thickness of the gate dielectric layer 6 is set according to performance requirements, ranging from 5 - 20 nm. Then deposit polysilicon to form a gate 7, where the deposition thickness of the polysilicon is 500 - 1000 nm, and in-situ doping is performed according to actual requirements. Then perform photolithography on the gate pattern and etch the polysilicon to form polysilicon gate bars;
[0064] Step 3: Oxidize the polysilicon to form a silicon dioxide layer 8 with a certain thickness on the outer layer of the gate 7, and its thickness is 5 - 20 nm. Then use a wet etching process to remove the silicon nitride dielectric in the source-drain region (the region outside the bottom of the gate 7);
[0065] Step 4: Selectively perform secondary epitaxial growth of a barrier layer 9 in the source-drain region, and the growth thickness ranges from 10 - 20 nm;
[0066] Step 5: depositing a sidewall dielectric layer to form a gate sidewall 10. The sidewall dielectric layer may be a single layer of silicon dioxide or a multilayer structure of silicon dioxide / silicon nitride, with a total thickness of about 200 to 500 nm, and then etching back to the channel layer 5 of the epitaxial wafer and the top of the gate 7;
[0067] Step 6: deposit source and drain metal layers (Ti / Al / Ti / TiN stacked structure may be used), remove the source and drain metal layers on the gate 7 by a planarization process (such as photoresist reflow-etch back planarization, or CMP technology), anneal, form source and drain ohmic contacts, and then form source 11 and drain 12;
[0068] Step 7: After step 6, an intermetallic dielectric layer is deposited, and then the rear-end via and metal interconnection processes are completed to finally form an N-channel enhancement-mode gallium nitride transistor device.
[0069] Embodiment 3
[0070] The difference between this embodiment and embodiment 2 is that the epitaxial wafers in this embodiment are purchased from outside (customized according to the process requirements such as the epitaxial wafer structure in embodiment 2), or are prefabricated using the method of step one in embodiment 2 before the manufacturing process, thereby shortening the overall production process (the integrated process is carried out in sections and simultaneously), shortening the actual process time, and improving the efficiency of production and manufacturing.
[0071] Embodiment 4
[0072] like Figure 7 As shown, the difference between this embodiment and the second or third embodiment is that in step five of this embodiment, after depositing the sidewall dielectric layer to form the gate sidewall 10, the sidewall dielectric layer is etched back to the top of the barrier layer 9 and the gate 7, and the other steps are completely the same.
[0073] The present invention uses polysilicon as the gate metal and a secondary epitaxial process, thereby avoiding the formation of a two-dimensional electron gas (2DEG) under the gate metal, and forms a two-dimensional electron gas (2DEG) on both sides of the gate metal (source and drain regions) as gate-source and gate-drain access regions, thereby forming an enhanced N-channel device.
[0074] The N-channel enhancement-mode gallium nitride transistor device formed by the method of the present invention has a gate dielectric layer 6. During the manufacturing process of the transistor, the gate dielectric layer 6 can effectively block the direct attack of the etching process on the gallium nitride surface, thereby avoiding the process problem of etching damage on the gallium nitride surface at the gate 7. The semiconductor interface at the gate 7 is good, which can improve the reliability of the device.
[0075] The length of the gate 7 in the present invention can be as small as tens of nanometers, which reduces the capacitance between the gate 7 and the channel, thereby reducing the switching time of the transistor and increasing the operating frequency, thereby obtaining a device with a higher operating frequency;
[0076] The present invention can adjust the device threshold voltage by regulating the polysilicon doping concentration in the gate 7, thereby reducing the device operating voltage.
[0077] The present invention uses polysilicon as the gate metal, which can ensure the performance while taking into account the thickness of the gate 7, and combines the sidewall process and the self-alignment process to form a small-size gate-source and gate-drain structure, so that the alignment accuracy between the gate 7 and the source 11 and the drain 12 is very high, thereby further reducing the size of the device (for example, for a device with a gate length of 100nm, the source-drain spacing of the present invention can be 150-200nm, while the source-drain spacing of a device using a conventional process is at least 300-400nm, and the repeatability is relatively poor), reducing the device operating voltage, and further improving the circuit density.
[0078] Since gallium nitride has higher breakdown performance, compared with RF switches of silicon or GaAs process types, under the same size, the gallium nitride device in this embodiment has a higher breakdown voltage as a RF switch. In addition, the device also has a better quality factor (FOM).
[0079] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, and a specific direction structure and operation, and therefore, cannot be understood as a limitation on the present invention. In addition, "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.
[0080] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0081] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.
Claims
1. An N-channel enhancement-mode gallium nitride transistor structure, characterized in that: include: An epitaxial wafer comprising a channel layer (5); A gate dielectric layer (6) formed on the channel layer (5); A gate (7) formed above the gate dielectric layer (6); A barrier layer (9) formed on both sides of the gate dielectric layer (6); Gate sidewalls (10) are formed on both sides of the gate (7) and are connected to the barrier layer (9); The source electrode (11) and the drain electrode (12) are formed on the channel layer (5) and are located outside the gate sidewalls (10) on both sides.
2. The N-channel enhancement-mode gallium nitride transistor structure according to claim 1, characterized in that: The epitaxial wafer comprises a substrate (1), a nucleation layer (2) is arranged above the substrate (1), a buffer layer (3) is arranged above the nucleation layer (2), a high resistance layer (4) is arranged above the buffer layer (3), and a channel layer (5) is arranged above the high resistance layer (4).
3. The N-channel enhancement-mode gallium nitride transistor structure according to claim 2, characterized in that: The bottom of the barrier layer (9) is connected to the channel layer (5), and the inner end of the barrier layer (9) is connected to the gate dielectric layer (6) and the gate sidewall (10); The source electrode (11) and the drain electrode (12) pass through the barrier layer (9) and are connected to the channel layer (5), and the outer end of the barrier layer (9) is connected to the corresponding source electrode (11) or drain electrode (12).
4. The N-channel enhancement-mode gallium nitride transistor structure according to claim 2, characterized in that: The nucleation layer (2) is a gallium nitride layer or an aluminum nitride layer, and the buffer layer (3) is an Al X GaN layer, where 0 < x < 1. The high-resistance layer (4) is a gallium nitride layer doped with iron or carbon, and the channel layer (5) is a gallium nitride layer with a thickness of 100 to 500 nm.
5. An N-channel enhancement-mode gallium nitride transistor structure according to claim 1 or 2, characterized in that: The gate dielectric layer (6) is a silicon nitride layer with a thickness of 5 - 20 nm, and the barrier layer (9) is an Al z Ga 1-z N layer, where 0.2 < z < 0.4 and the thickness is 10 - 20 nm.
6. An N-channel enhancement-mode gallium nitride transistor structure according to any one of claims 1 to 3, characterized in that: The gate (7) is a polysilicon layer with a thickness of 500-1000 nm, and the gate sidewall (10) is a silicon dioxide single layer or a silicon dioxide / silicon nitride multilayer structure with a thickness of 200-500 nm.
7. An N-channel enhancement-mode gallium nitride transistor structure according to any one of claims 1 to 3, characterized in that: The source electrode (11) and the drain electrode (12) are both Ti / Al / Ti / TiN stacked layer structures.
8. A method for manufacturing an N-channel enhancement-mode gallium nitride transistor structure, characterized in that: The method for manufacturing an N-channel enhancement-mode gallium nitride transistor structure as claimed in any one of claims 1 to 7 comprises the following steps: Step 1: providing or preparing an epitaxial wafer; Step 2: depositing silicon nitride on the channel layer (5) to form a gate dielectric layer (6), then depositing polysilicon to form a gate (7), then photolithography the gate pattern, and etching the polysilicon to form a polysilicon gate strip; Step 3: oxidize the polysilicon to form a silicon oxide layer (8) on the outer layer of the gate (7), and then use a wet etching process to remove the silicon nitride dielectric in the source and drain regions; Step 4: selectively epitaxially growing a barrier layer (9) in the source and drain regions; Step 5: depositing a sidewall dielectric layer to form a gate sidewall (10), and then etching back to the channel layer (5) and the top of the gate (7); Step 6: depositing a source and drain metal layer, removing the source and drain metal layer on the gate (7) by a planarization process, and performing an annealing process to form a source and drain ohmic contact, thereby forming a source electrode (11) and a drain electrode (12); Step 7: After that, an intermetallic dielectric layer is deposited, and then the rear-end through-hole and metal interconnection processes are completed to finally form an N-channel enhancement-mode gallium nitride transistor device.
9. The method for manufacturing an N-channel enhancement-mode gallium nitride transistor structure according to claim 8, characterized in that: The method for preparing the epitaxial wafer comprises: providing a substrate (1), and epitaxially growing a core layer (2), a buffer layer (3), a high resistance layer (4) and a channel layer (5) in sequence from bottom to top on the surface of the substrate (1).
10. A method for manufacturing an N-channel enhancement-mode gallium nitride transistor structure, characterized in that: The method for manufacturing an N-channel enhancement-mode gallium nitride transistor structure as claimed in any one of claims 1 to 7 comprises the following steps: Step 1: providing or preparing an epitaxial wafer; Step 2: depositing silicon nitride on the channel layer (5) to form a gate dielectric layer (6), then depositing polysilicon to form a gate (7), then photolithography the gate pattern, and etching the polysilicon to form a polysilicon gate strip; Step 3: oxidize the polysilicon to form a silicon oxide layer (8) on the outer layer of the gate (7), and then use a wet etching process to remove the silicon nitride dielectric in the source and drain regions; Step 4: selectively epitaxially growing a barrier layer (9) in the source and drain regions; Step 5: depositing a sidewall dielectric layer to form a gate sidewall (10), and then etching back to the barrier layer (9) and the top of the gate (7); Step 6: depositing a source and drain metal layer, removing the source and drain metal layer on the gate (7) by a planarization process, and performing an annealing process to form a source and drain ohmic contact, thereby forming a source electrode (11) and a drain electrode (12); Step 7: After that, an intermetallic dielectric layer is deposited, and then the rear-end through-hole and metal interconnection processes are completed to finally form an N-channel enhancement-mode gallium nitride transistor device.