Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. According to the invention, by optimizing the device structure and setting the distance between two adjacent storage tubes to be smaller than the preset distance threshold, the area of the device is reduced; the source regions of the storage units are connected through the doping layer to form the source line, and only one leading-out structure needs to be formed at one end of the source line, so that the preparation process of a plurality of source contact structures is avoided, and the process risk is reduced; each drain region is led out through a drain contact structure, and the drain contact structures of the storage units are connected to form a bit line. The source lines and the bit lines are vertically distributed, so that the process feasibility is improved, and the device area is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Flash memory (also known as flash memory) is an electrically erasable programmable read-only memory (EEPROM), which has the characteristics of non-volatility, fast read and write speed, shock resistance, low power consumption, and small size. It is currently widely used in embedded systems. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) structure flash memory is a simple structure and high reliability memory. Its storage unit (Cell) is usually a 2T structure composed of a selection tube (SG) and a storage tube (MG), which is widely used in embedded flash memory.

[0003] In the storage unit of the existing SONOS structure flash memory, a drain contact structure (DCT) is formed above the drain region on one side of the selection tube (SG), and a source contact structure (SCT) is formed above the source region between two adjacent storage tubes (MG); the drain contact structures (DCT) in each storage unit are connected to form a bit line (BL), and the source contact structures (SCT) in each storage unit are connected to form a source line (SL).

[0004] With the pursuit of smaller memory cell area and lower manufacturing cost, the layout of forming a source contact structure (SCT) above the source region between two adjacent memory tubes (MG) will increase the memory cell area; and a source contact structure (SCT) needs to be formed above the source region between every two adjacent memory tubes (MG), and a large number of them will also increase the process risk. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor structure and a preparation method thereof, which can reduce the storage unit area and reduce the process risk by optimizing the device structure.

[0006] In order to solve the above problems, the present invention provides a method for preparing a semiconductor structure, the method comprising the following steps: forming a base, the base comprising a substrate, an active region extending along a first direction and spaced along a second direction is defined in the substrate by a shallow trench isolation structure, a drain region and a source region are formed in the active region, a storage unit composed of a selection tube and a storage tube and arranged symmetrically is formed on the surface of the active region, and the spacing between two adjacent storage tubes is less than a preset spacing threshold, wherein the first direction and the second direction are both parallel to the surface of the substrate, and the first direction intersects with the second direction; etching and removing the shallow trench isolation structure in the region between the two adjacent storage tubes to expose the substrate in the region; performing ion implantation on the region between the two adjacent storage tubes to form a doping layer as a source line, the doping layer is continuously distributed along the second direction and connects the source regions of each storage unit; and forming a drain contact structure in contact with the drain region above the drain region, and forming a connecting line as a bit line, the connecting line is continuously distributed along the first direction and connects the drain contact structure in each storage unit.

[0007] In order to solve the above problems, the present invention further provides a semiconductor structure, which is prepared by the preparation method of the present invention.

[0008] The above technical solution optimizes the device structure and sets the spacing between two adjacent storage tubes to be less than a preset spacing threshold, thereby reducing the device area; the source regions of each storage unit are connected through a doping layer to form a source line, and only one lead-out structure needs to be formed at one end of the source line, thereby avoiding the preparation process of multiple source contact structures and reducing the process risk; each drain region is led out through a drain contact structure, and the drain contact structures of each storage unit are connected to form a bit line. The source line and the bit line are vertically distributed, thereby improving the process feasibility and reducing the device area. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 A schematic diagram of the layout of an existing SONOS structure flash memory;

[0011] Figure 2 For along Figure 1 Sectional view along line A-A';

[0012] Figure 3 A schematic diagram of the steps of a method for preparing a semiconductor structure in one embodiment of the present invention;

[0013] Figure 4 A schematic diagram of a layout of a semiconductor structure according to an embodiment of the present invention;

[0014] Figure 5 The substrate provided by one embodiment of the present invention is Figure 4 Sectional view along line B-B';

[0015] Figure 6 The method for forming an ONO layer and a gate oxide layer trailing edge according to an embodiment of the present invention Figure 4 Sectional view along line B-B';

[0016] Figure 7 The gate layer trailing edge forming method according to an embodiment of the present invention Figure 4 Sectional view along line B-B';

[0017] Figure 8 The protective sidewall rear edge is formed according to an embodiment of the present invention. Figure 4 Sectional view along line B-B';

[0018] Fig. 9 The etching method for removing the front edge of the shallow trench isolation structure according to an embodiment of the present invention Figure 4 Sectional view along line C-C';

[0019] Fig.10 The etching method for removing the back edge of the shallow trench isolation structure according to an embodiment of the present invention is as follows: Figure 4 Sectional view along line C-C';

[0020] Fig.11 The method for forming the trailing edge of the doped layer according to an embodiment of the present invention Figure 4 Sectional view along line C-C';

[0021] Fig.12 The present invention is to form a drain contact structure and a connection line trailing edge according to an embodiment of the present invention. Figure 4 Sectional view along line B-B';

[0022] Fig.13 The invention is an embodiment of the present invention to form a lead structure trailing edge Figure 4 Sectional view along line C-C'. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] like Figure 1-2 In the existing SONOS structure flash memory shown, the storage cell (Cell) is a 2T structure composed of a selection tube (SG) and a storage tube (MG), and the device is formed on a silicon substrate. A shallow trench isolation structure (STI) is formed on the silicon substrate to isolate the active area AA, and the active area AA is a strip-shaped structure, in which an active area 101 and a drain area 102 are formed. An ONO layer 11 is formed between the first gate layer 13 of the storage tube (MG) and the active area AA, and a gate oxide layer 12 is formed between the second gate layer 14 of the selection tube (SG) and the active area AA. The side walls of the selection tube (SG) and the storage tube (MG) are both formed with protective sidewalls 15. Among them, the constituent materials of the first gate layer 13 and the second gate layer 14 are both polysilicon. A drain contact structure (DCT) 16 is formed above the drain region 102 on one side of the selection tube SG, and a source contact structure (SCT) 17 is formed above the source region 101 between two adjacent storage tubes (MG); the drain contact structures 16 in each storage cell are connected to form a bit line (not shown), and the source contact structures 17 in each storage cell are connected to form a source line (not shown).

[0025] The layout of the existing SONOS structure flash memory where the source contact structure is formed above the source region between two adjacent storage tubes will increase the storage unit area; and a source contact structure needs to be formed above the source region between each two adjacent storage tubes, and a large number of source contact structures will also increase the process risk. In order to reduce the storage unit area and reduce the process risk, the embodiment of the present invention provides a semiconductor structure and a preparation method thereof.

[0026] Please also read Figure 3 to Figure 13 ,in, Figure 3 A schematic diagram of the steps of a method for preparing a semiconductor structure in one embodiment of the present invention; Figure 4 A schematic diagram of a layout of a semiconductor structure according to an embodiment of the present invention;

[0027] Figure 5 The substrate provided by one embodiment of the present invention is Figure 4 Sectional view along line B-B'; Figure 6 The method for forming an ONO layer and a gate oxide layer trailing edge according to an embodiment of the present invention Figure 4 Sectional view along line B-B'; Figure 7 The gate layer trailing edge forming method according to an embodiment of the present invention Figure 4 Sectional view along line B-B'; Figure 8 The protective sidewall rear edge is formed according to an embodiment of the present invention. Figure 4 Sectional view along line B-B'; Fig. 9 The etching method for removing the front edge of the shallow trench isolation structure according to an embodiment of the present invention Figure 4 Sectional view along line C-C'; Fig.10The etching method for removing the back edge of the shallow trench isolation structure according to an embodiment of the present invention Figure 4 Sectional view along line C-C';

[0028] Fig.11 The method for forming the trailing edge of the doped layer according to an embodiment of the present invention Figure 4 Sectional view along line C-C'; Fig.12 The present invention is to form a drain contact structure and a connection line trailing edge according to an embodiment of the present invention. Figure 4 Sectional view along line B-B'; Fig.13 The invention is an embodiment of the present invention to form a lead structure trailing edge Figure 4 Cross-sectional view along line C-C'.

[0029] like Figure 3 As shown, the preparation method of the semiconductor structure described in this embodiment includes the following steps: S1, forming a base, the base includes a substrate, an active area extending along a first direction and spaced along a second direction is defined in the substrate by a shallow trench isolation structure, a drain area and a source area are formed in the active area, and a storage unit composed of a selection tube and a storage tube, which is symmetrically arranged, is formed on the surface of the active area, and the spacing between two adjacent storage tubes is less than a preset spacing threshold; S2, etching and removing the shallow trench isolation structure in the area between two adjacent storage tubes to expose the substrate in the area; S3, ion implanting the area between two adjacent storage tubes to form a doping layer as a source line, the doping layer is continuously distributed along the second direction and connects the source areas of each storage unit; and S4, forming a drain contact structure contacting the drain area above the drain area, and forming a connecting line as a bit line, the connecting line is continuously distributed along the first direction and connects the drain contact structure in each storage unit.

[0030] For convenience of explanation, in the following embodiments, the first direction D1 and the second direction D2 are parallel to the substrate surface and intersect each other; the third direction D3 is perpendicular to the substrate surface (the third direction D3 is the device stacking direction) and intersects both the first direction D1 and the second direction D2. Specifically, the first direction D1 is the X-axis direction in the Cartesian coordinate system, the second direction D2 is the Y-axis direction in the Cartesian coordinate system, and the third direction D3 is the Z-axis direction in the Cartesian coordinate system.

[0031] Please refer to step S1 and Figure 8 , forming a substrate, the substrate comprising a substrate 40, the substrate 40 is provided with a shallow trench isolation structure STI (refer to Fig. 9As shown in the figure, an active area AA extending along a first direction D1 and spaced along a second direction D2 is defined; a drain area 402 and a source area 403 are formed in the active area AA; a storage unit composed of a selection tube (SG) and a storage tube (MG) arranged symmetrically is formed on the surface of the active area. The spacing W1 between two adjacent storage tubes (MG) is less than a preset spacing threshold. This embodiment optimizes the device structure and sets the spacing W1 between two adjacent storage tubes (MG) to be less than the preset spacing threshold, thereby reducing the device area and the process risk.

[0032] In this embodiment, the step of forming a substrate specifically includes: (1) providing a substrate 40, wherein the substrate 40 includes a front side and a back side that are relatively distributed, and the front side of the substrate 40 is defined by a shallow trench isolation structure STI to have an active area AA extending along a first direction D1 and spaced along a second direction D2, wherein a drain area 402 and a source area 403 are formed in the active area AA, such as Fig. 9 as well as Figure 5 (2) forming the ONO layer 41 of the storage tube and the gate oxide layer 42 of the selection tube on the surface of the active area AA, as shown in FIG. Figure 6 (3) depositing polysilicon material and etching, respectively, forming the first gate layer 43 of the storage tube on the surface of the ONO layer 41, and forming the second gate layer 44 of the selection tube on the surface of the gate oxide layer 42, as shown in FIG. Figure 7 (4) forming a protective side wall 45 on the side wall of the selection tube and the storage tube, as shown Figure 8 shown.

[0033] The substrate 40 is used to support the device structure above it, and the device structure may also be formed in the substrate 40. In this embodiment, the substrate 40 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 40 may also be a stacked structure, such as a silicon / germanium silicon stack, etc. This embodiment is described by taking the substrate 40 as a silicon substrate as an example.

[0034] In this embodiment, the step of providing the substrate 40 specifically includes: (11) defining an active area AA extending along a first direction D1 and spaced along a second direction D2 on the front side of the substrate 40 through a shallow trench isolation structure STI; (12) performing a first ion implantation to form a deep well isolation layer 401 of a first conductivity type in the substrate 40 to isolate and protect the active area AA; (13) performing a second ion implantation to form a well region (not shown) of a second conductivity type in the active area AA; (14) performing a third ion implantation to form a drain region 402 and a source region 403 of a first conductivity type in the well region. Specifically, the first conductivity type is P type, and the second conductivity type is N type. N-type ion implantation is performed on the substrate to form a deep well isolation layer. The shallow trench isolation structure STI and the deep well isolation layer cooperate to well isolate and protect the active area AA; P-type ion implantation is performed in the active area to form a P-type well to adjust the threshold voltage; N-type ion implantation is performed in the P-type well to form a drain region 402 and a source region 403. The drain region 402 and the source region 403 are separated by a distance and parallel to each other. The P-type well between the drain region 402 and the source region 403 constitutes a channel region. In other embodiments, it can also be: the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the drain region 402 and the source region 403 can also be formed in the P-type well under the self-alignment of the protective sidewall 45 of the selection tube and the storage tube.

[0035] In this embodiment, the active area AA is a stripe-shaped structure, and the shallow trench isolation structure STI is also a stripe-shaped structure and is arranged alternately with the active area AA.

[0036] In some embodiments, the ONO layer 41 , the gate oxide layer 42 , and the protective spacer 45 are all formed by a thermal oxidation process.

[0037] In this embodiment, the steps of forming the ONO layer 41 of the storage tube and the gate oxide layer 42 of the selection tube on the surface of the active area AA include: (21) forming a first silicon oxide layer, a second silicon nitride layer and a third silicon oxide layer in sequence on the surface of the active area AA by a thermal oxidation process, and forming a tunneling oxide layer 411, a trap nitride layer 412 and a blocking oxide layer 413 as the ONO layer 41 by photolithography and etching; (22) forming a gate oxide material layer on the surface of the active area AA by a thermal oxidation process, and forming the gate oxide layer 42 by photolithography and etching, as shown in FIG. Figure 6As shown. And, the ONO layer 41 is formed by stacking a tunneling oxide layer 411, a trap nitride layer 412, and a blocking oxide layer 413 from bottom to top. The storage tube is formed by stacking a silicon substrate, a tunneling oxide layer, a trap nitride layer, a blocking oxide layer and polysilicon from bottom to top; the selection tube is formed by stacking a silicon substrate, a gate oxide layer and polysilicon from bottom to top. The thickness of the first silicon oxide (e.g., silicon dioxide) layer and the third silicon oxide (e.g., silicon dioxide) layer can be less than the thickness of the second silicon nitride layer. The first silicon oxide layer covers the top surface of the substrate 40, which can prevent subsequent processes from causing damage to the top surface of the substrate 40. Silicon nitride is a commonly used and relatively good etching mask layer and barrier layer, which can protect the surface of the substrate 40 from being damaged.

[0038] In this embodiment, the step of forming the protective sidewall 45 on the sidewalls of the selection tube and the storage tube specifically includes: using a rapid thermal oxidation process to grow a silicon dioxide layer on the sidewalls of the selection tube and the storage tube as the protective sidewall 45, such as Figure 8 shown.

[0039] Please refer to step S2 and Fig.10 , the shallow trench isolation structure STI in the area between two adjacent storage tubes is etched away to expose the substrate 40 in the area.

[0040] In this embodiment, the step of etching away the shallow trench isolation structure STI in the region between two adjacent storage tubes to expose the substrate 40 in the region specifically includes: (1) forming a photomask on the surface of the substrate, the photomask having an opening for exposing the shallow trench isolation structure in the region between two adjacent storage tubes; (2) using the photomask as a shield, etching away the shallow trench isolation structure in the region between two adjacent storage tubes along the opening to expose the substrate in the region. Specifically, the etching away the shallow trench isolation structure in the region between two adjacent storage tubes adopts a dry etching process.

[0041] In some embodiments, a mask layer and a photoresist layer can be formed on the surface of the substrate, and the space (Space) between two adjacent storage tubes (MG) on the photoresist layer is opened by photolithography, and other areas are covered to form a patterned photoresist layer having a pattern exposing the shallow trench isolation structure in the area between the two adjacent storage tubes; the mask layer is etched using the patterned photoresist layer as a shield to form a patterned mask layer having an opening exposing the shallow trench isolation structure in the area between the two adjacent storage tubes; the shallow trench isolation structure STI in the opening area is etched cleanly by dry etching using the patterned mask layer as a shield, and at the same time, there is no or little loss of the silicon substrate.

[0042] Please refer to step S3 and Fig.11, ion implantation is performed on the region between two adjacent storage tubes to form a doping layer 49 as a source line (SL), the doping layer 49 is continuously distributed along the second direction D2 and connects the source region 403 of each storage unit (refer to Figure 4 as well as Fig.12 Specifically, the substrate of the space region between the two storage tubes (MG) is doped by ion implantation (after STI is etched clean), and the surface of the substrate 40, the side wall of the deep well isolation layer 401, and the side wall of the active area AA exposed after etching are doped to form a doping layer 49 as a source line (SL). The doping layer 49 is continuously distributed along the second direction D2 and connects the source area 403 of each storage unit, so as to avoid forming multiple source contact structures above the source area between two adjacent storage tubes (MG), thereby reducing the process risk; and the spacing W1 between two adjacent storage tubes (MG) is less than the preset spacing threshold, thereby reducing the device area.

[0043] In some embodiments, in the second direction D2, the resistance value of the source line is lower than a preset resistance threshold value. That is, by ion implantation, the surface of the substrate 40, the sidewall of the deep well isolation layer 401, and the sidewall of the active area AA exposed after etching between the two storage tubes (MG) are doped to a low resistance value to form a doping layer 49 as the source line (SL).

[0044] In some embodiments, the method further comprises: forming a lead-out structure 47 in contact with the source line above one end of the source line in the second direction D2, such as Fig.13 That is, in this embodiment, only one lead-out structure 47 needs to be formed at one end of the source line, avoiding the preparation process of multiple source contact structures and reducing the process risk. Specifically, the lead-out structure 47 can be formed at the far end of the source line and on an active area AA.

[0045] Please refer to step S4 and Fig.12 A drain contact structure 46 in contact with the drain region 402 is formed above the drain region 402, and a connecting line 48 is formed as a bit line (BL). The connecting line 48 is continuously distributed along the first direction D1 and connects the drain contact structure 46 in each memory cell.

[0046] In this embodiment, the source regions of each memory cell are connected through a doping layer 49 to form a source line (SL); each drain region is led out through a drain contact structure 46, and the drain contact structures 46 of each memory cell are connected to form a bit line (BL). In this embodiment, the source line (SL) and the bit line (BL) are vertically distributed. The lead-out structure 47 and the drain contact structure 46 can be metal structures of the material system.

[0047] The method for preparing the semiconductor structure described in this embodiment can be applied to a flash memory with a SONOS structure, and has a simple structure and high reliability.

[0048] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor structure, which is manufactured by the above method of the present invention.

[0049] Please also read Figure 4 , Fig.12 , Fig.13 , which is a schematic diagram of a semiconductor structure provided by an embodiment of the present invention. Specifically, the semiconductor structure provided by this embodiment is prepared by the above method of the present invention, and includes: a substrate 40, an active area AA, a drain area 402, a source area 403, a doping layer 49, a lead-out structure 47, a drain contact structure 46 and a connecting line 48.

[0050] In some embodiments, the substrate 40 is defined by a shallow trench isolation structure STI to have an active area AA extending along a first direction D1 and spaced along a second direction D2; a drain area 402 and a source area 403 are formed in the active area AA; and a symmetrically arranged storage unit composed of a selection tube (SG) and a storage tube (MG) is formed on the surface of the active area. The spacing W1 between two adjacent storage tubes (MG) is less than a preset spacing threshold.

[0051] In some embodiments, a deep well isolation layer is formed on the substrate by performing N-type ion implantation, and the shallow trench isolation structure STI and the deep well isolation layer cooperate to well isolate and protect the active area AA; a P-type well is formed in the active area by performing P-type ion implantation to adjust the threshold voltage; a drain area 402 and a source area 403 are formed in the P-type well by performing N-type ion implantation, the drain area 402 and the source area 403 are separated by a distance and parallel to each other, and the P-type well between the drain area 402 and the source area 403 constitutes a channel area. The active area AA is a strip structure, and the shallow trench isolation structure STI is also a strip structure and is arranged alternately with the active area AA.

[0052] In some embodiments, the ONO layer 41 is formed from the bottom up by stacking a tunneling oxide layer 411, a trap nitride layer 412, and a blocking oxide layer 413. The storage tube is formed from the bottom up by stacking a silicon substrate, a tunneling oxide layer, a trap nitride layer, a blocking oxide layer, and polysilicon; the selection tube is formed from the bottom up by stacking a silicon substrate, a gate oxide layer, and polysilicon.

[0053] In some embodiments, the region between two adjacent storage tubes is formed by ion implantation to form a doping layer 49 as a source line (SL), and the doping layer 49 is continuously distributed along the second direction D2 and connects the source region 403 of each storage unit; wherein the shallow trench isolation structure STI in the region between two adjacent storage tubes is etched away to form a groove of the substrate 40 exposing the region, and the base of the space region between the two MGs (the groove is formed after the STI is etched cleanly) is doped by ion implantation, and the surface of the substrate 40, the side wall of the deep well isolation layer 401, and the side wall of the active area AA exposed after etching are doped to form a doping layer 49 as a source line (SL). In the second direction D2, a lead-out structure 47 in contact with the source line is formed above one end of the source line.

[0054] In some embodiments, a drain contact structure 46 in contact with the drain region 402 is formed above the drain region 402 , and a connecting line 48 is formed as a bit line (BL). The connecting line 48 is continuously distributed along the first direction D1 and connects the drain contact structure 46 in each memory cell.

[0055] In this embodiment, the semiconductor structure is a SONOS structure flash memory. SONOS structure flash memory is a memory with simple structure and high reliability, and its storage cell (Cell) is usually a 2T structure composed of a selection tube (SG) and a storage tube (MG), which is widely used in embedded flash memory.

[0056] The base of the space region between the two storage tubes (after STI etching) is doped by ion implantation, and the surface of the substrate 40, the side wall of the deep well isolation layer 401, and the side wall of the active area AA exposed after etching are doped to form a doping layer 49 as a source line (SL). The doping layer 49 is continuously distributed along the second direction D2 and connects the source area 403 of each storage unit, thereby avoiding the formation of multiple source contact structures above the source area between two adjacent storage tubes (MG), thereby reducing the process risk; and the spacing W1 between two adjacent storage tubes (MG) is less than the preset spacing threshold, thereby reducing the device area.

[0057] Specifically, the substrate 40 is provided with a shallow trench isolation structure STI (see Fig. 9 As shown in the figure, an active area AA extending along a first direction D1 and spaced apart along a second direction D2 is defined; a drain area 402 and a source area 403 are formed in the active area AA; and a storage unit composed of a selection tube (SG) and a storage tube (MG) arranged symmetrically is formed on the surface of the active area.

[0058] In the semiconductor structure prepared in this embodiment, by optimizing the device structure, the spacing W1 between two adjacent storage tubes (MG) is set to be less than the preset spacing threshold, thereby reducing the device area; the source regions of each storage unit are connected through a doping layer to form a source line, and only one lead-out structure needs to be formed at one end of the source line, thereby avoiding the preparation process of multiple source contact structures and reducing the process risk; each drain region is led out through a drain contact structure, and the drain contact structures of each storage unit are connected to form a bit line. The source line (SL) and the bit line (BL) are distributed vertically, thereby improving the process feasibility and reducing the device area.

[0059] In the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0060] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, there is a sentence "also includes a ..." The elements limited do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises the following steps: Forming a substrate, the substrate comprising a substrate, wherein an active region extending along a first direction and spaced apart along a second direction is defined in the substrate by a shallow trench isolation structure, a drain region and a source region are formed in the active region, a storage unit composed of a selection tube and a storage tube and arranged symmetrically is formed on the surface of the active region, and a spacing between two adjacent storage tubes is less than a preset spacing threshold, wherein the first direction and the second direction are both parallel to the substrate surface, and the first direction intersects with the second direction; Etching and removing the shallow trench isolation structure in the area between two adjacent storage tubes to expose the substrate in the area; Performing ion implantation on the area between two adjacent storage tubes to form a doped layer as a source line, wherein the doped layer is continuously distributed along the second direction and connects the source regions of each storage unit; and A drain contact structure contacting the drain region is formed above the drain region, and a connecting line is formed as a bit line. The connecting line is continuously distributed along a first direction and connects the drain contact structures in each storage unit.

2. The method according to claim 1, characterized in that The step of forming the base specifically includes: providing a substrate, the substrate including a front side and a back side that are relatively distributed, the front side of the substrate is defined by a shallow trench isolation structure with an active region extending along a first direction and spaced apart along a second direction, the active region having a drain region and a source region formed therein; Forming an ONO layer of the storage tube and a gate oxide layer of the selection tube on the surface of the active area respectively; Depositing polysilicon material and etching to form a first gate layer of the storage tube on the surface of the ONO layer and a second gate layer of the selection tube on the surface of the gate oxide layer; A protective side wall is formed on the side walls of the selection tube and the storage tube.

3. The method according to claim 2, characterized in that The step of providing a substrate specifically includes: defining active areas extending along a first direction and spaced apart along a second direction on the front side of the substrate through a shallow trench isolation structure; Performing a first ion implantation to form a deep well isolation layer of a first conductivity type in the substrate to isolate and protect the active area; Performing a second ion implantation to form a well region of a second conductivity type in the active region; A third ion implantation is performed to form a drain region and a source region of the first conductivity type in the well region.

4. The method according to claim 3, characterized in that The first conductivity type is P type, and the second conductivity type is N type; or the first conductivity type is N type, and the second conductivity type is P type.

5. The method according to claim 2, characterized in that: The steps of respectively forming the ONO layer of the storage tube and the gate oxide layer of the selection tube on the surface of the active area specifically include: A first silicon oxide layer, a second silicon nitride layer and a third silicon oxide layer are sequentially formed on the surface of the active area by a thermal oxidation process, and a tunneling oxide layer, a trap nitride layer and a blocking oxide layer are formed as the ONO layer by photolithography and etching; A gate oxide material layer is formed on the surface of the active area by adopting a thermal oxidation process, and the gate oxide layer is formed by photolithography and etching.

6. The method according to claim 2, characterized in that The step of forming a protective side wall on the side walls of the selection tube and the storage tube specifically includes: A silicon dioxide layer is grown on the side walls of the selection tube and the storage tube by using a rapid thermal oxidation process as the protection side wall.

7. The method according to claim 1, characterized in that The step of etching and removing the shallow trench isolation structure in the area between two adjacent storage tubes to expose the substrate in the area specifically includes: forming a photomask on the surface of the substrate, wherein the photomask has an opening exposing the shallow trench isolation structure in the area between two adjacent storage tubes; Using the photomask as a shield, the shallow trench isolation structure in the area between two adjacent storage tubes is removed by etching along the opening to expose the substrate in the area.

8. The method according to claim 1 or 7, characterized in that: The etching to remove the shallow trench isolation structure in the area between two adjacent storage tubes adopts a dry etching process.

9. The method according to claim 1, characterized in that: In the second direction, the resistance value of the source line is lower than a preset resistance threshold.

10. The method according to claim 1, characterized in that The method further comprises: In the second direction, a lead-out structure contacting the source line is formed above one end of the source line.

11. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 10.

12. The semiconductor structure according to claim 11, characterized in that: The semiconductor structure is a SONOS structure flash memory.

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